2 * From Coreboot src/southbridge/intel/bd82x6x/me.h
4 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
6 * SPDX-License-Identifier: GPL-2.0
9 #ifndef _ASM_INTEL_ME_H
10 #define _ASM_INTEL_ME_H
12 #include <linux/compiler.h>
13 #include <linux/types.h>
15 #define ME_RETRY 100000 /* 1 second */
16 #define ME_DELAY 10 /* 10 us */
19 * Management Engine PCI registers
22 #define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */
23 #define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */
25 #define PCI_ME_HFS 0x40
26 #define ME_HFS_CWS_RESET 0
27 #define ME_HFS_CWS_INIT 1
28 #define ME_HFS_CWS_REC 2
29 #define ME_HFS_CWS_NORMAL 5
30 #define ME_HFS_CWS_WAIT 6
31 #define ME_HFS_CWS_TRANS 7
32 #define ME_HFS_CWS_INVALID 8
33 #define ME_HFS_STATE_PREBOOT 0
34 #define ME_HFS_STATE_M0_UMA 1
35 #define ME_HFS_STATE_M3 4
36 #define ME_HFS_STATE_M0 5
37 #define ME_HFS_STATE_BRINGUP 6
38 #define ME_HFS_STATE_ERROR 7
39 #define ME_HFS_ERROR_NONE 0
40 #define ME_HFS_ERROR_UNCAT 1
41 #define ME_HFS_ERROR_IMAGE 3
42 #define ME_HFS_ERROR_DEBUG 4
43 #define ME_HFS_MODE_NORMAL 0
44 #define ME_HFS_MODE_DEBUG 2
45 #define ME_HFS_MODE_DIS 3
46 #define ME_HFS_MODE_OVER_JMPR 4
47 #define ME_HFS_MODE_OVER_MEI 5
48 #define ME_HFS_BIOS_DRAM_ACK 1
49 #define ME_HFS_ACK_NO_DID 0
50 #define ME_HFS_ACK_RESET 1
51 #define ME_HFS_ACK_PWR_CYCLE 2
52 #define ME_HFS_ACK_S3 3
53 #define ME_HFS_ACK_S4 4
54 #define ME_HFS_ACK_S5 5
55 #define ME_HFS_ACK_GBL_RESET 6
56 #define ME_HFS_ACK_CONTINUE 7
62 u32 operation_state:3;
63 u32 fw_init_complete:1;
65 u32 update_in_progress:1;
69 u32 boot_options_present:1;
74 #define PCI_ME_UMA 0x44
84 #define PCI_ME_H_GS 0x4c
85 #define ME_INIT_DONE 1
86 #define ME_INIT_STATUS_SUCCESS 0
87 #define ME_INIT_STATUS_NOMEM 1
88 #define ME_INIT_STATUS_ERROR 2
97 #define PCI_ME_GMES 0x48
98 #define ME_GMES_PHASE_ROM 0
99 #define ME_GMES_PHASE_BUP 1
100 #define ME_GMES_PHASE_UKERNEL 2
101 #define ME_GMES_PHASE_POLICY 3
102 #define ME_GMES_PHASE_MODULE 4
103 #define ME_GMES_PHASE_UNKNOWN 5
104 #define ME_GMES_PHASE_HOST 6
110 u32 cpu_replaced_sts:1;
113 u32 warm_rst_req_for_df:1;
114 u32 cpu_replaced_valid:1;
119 u32 current_pmevent:4;
123 #define PCI_ME_HERES 0xbc
124 #define PCI_ME_EXT_SHA1 0x00
125 #define PCI_ME_EXT_SHA256 0x02
126 #define PCI_ME_HER(x) (0xc0+(4*(x)))
129 u32 extend_reg_algorithm:4;
131 u32 extend_feature_present:1;
132 u32 extend_reg_valid:1;
136 * Management Engine MEI registers
139 #define MEI_H_CB_WW 0x00
140 #define MEI_H_CSR 0x04
141 #define MEI_ME_CB_RW 0x08
142 #define MEI_ME_CSR_HA 0x0c
145 u32 interrupt_enable:1;
146 u32 interrupt_status:1;
147 u32 interrupt_generate:1;
151 u32 buffer_read_ptr:8;
152 u32 buffer_write_ptr:8;
156 #define MEI_ADDRESS_CORE 0x01
157 #define MEI_ADDRESS_AMT 0x02
158 #define MEI_ADDRESS_RESERVED 0x03
159 #define MEI_ADDRESS_WDT 0x04
160 #define MEI_ADDRESS_MKHI 0x07
161 #define MEI_ADDRESS_ICC 0x08
162 #define MEI_ADDRESS_THERMAL 0x09
164 #define MEI_HOST_ADDRESS 0
167 u32 client_address:8;
174 #define MKHI_GROUP_ID_CBM 0x00
175 #define MKHI_GROUP_ID_FWCAPS 0x03
176 #define MKHI_GROUP_ID_MDES 0x08
177 #define MKHI_GROUP_ID_GEN 0xff
179 #define MKHI_GLOBAL_RESET 0x0b
181 #define MKHI_FWCAPS_GET_RULE 0x02
183 #define MKHI_MDES_ENABLE 0x09
185 #define MKHI_GET_FW_VERSION 0x02
186 #define MKHI_END_OF_POST 0x0c
187 #define MKHI_FEATURE_OVERRIDE 0x14
197 struct me_fw_version {
200 u16 code_build_number;
204 u16 recovery_build_number;
205 u16 recovery_hot_fix;
209 #define HECI_EOP_STATUS_SUCCESS 0x0
210 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
212 #define CBM_RR_GLOBAL_RESET 0x01
214 #define GLOBAL_RESET_BIOS_MRC 0x01
215 #define GLOBAL_RESET_BIOS_POST 0x02
216 #define GLOBAL_RESET_MEBX 0x03
218 struct me_global_reset {
227 ME_RECOVERY_BIOS_PATH,
228 ME_DISABLE_BIOS_PATH,
229 ME_FIRMWARE_UPDATE_BIOS_PATH,
232 struct __packed mbp_fw_version_name {
233 u32 major_version:16;
234 u32 minor_version:16;
235 u32 hotfix_version:16;
236 u32 build_version:16;
239 struct __packed mbp_icc_profile {
241 u8 icc_profile_soft_strap;
242 u8 icc_profile_index;
244 u32 register_lock_mask[3];
247 struct __packed mefwcaps_sku {
251 u32 small_business:1;
252 u32 l3manageability:1;
257 u32 icc_over_clocking:1;
270 struct __packed tdt_state_flag {
272 u16 authenticate_module:1;
273 u16 s3authentication:1;
274 u16 flash_wear_out:1;
275 u16 flash_variable_security:1;
281 struct __packed tdt_state_info {
283 u8 last_theft_trigger;
284 struct tdt_state_flag flags;
287 struct __packed platform_type_rule_data {
288 u32 platform_target_usage_type:4;
289 u32 platform_target_market_type:2;
292 u32 intel_me_fw_image_type:4;
293 u32 platform_brand:4;
297 struct __packed mbp_fw_caps {
298 struct mefwcaps_sku fw_capabilities;
302 struct __packed mbp_rom_bist_data {
308 struct __packed mbp_platform_key {
312 struct __packed mbp_plat_type {
313 struct platform_type_rule_data rule_data;
317 struct __packed me_bios_payload {
318 struct mbp_fw_version_name fw_version_name;
319 struct mbp_fw_caps fw_caps_sku;
320 struct mbp_rom_bist_data rom_bist_data;
321 struct mbp_platform_key platform_key;
322 struct mbp_plat_type fw_plat_type;
323 struct mbp_icc_profile icc_profile;
324 struct tdt_state_info at_state;
328 struct __packed mbp_header {
334 struct __packed mbp_item_header {
341 struct __packed me_fwcaps {
344 struct mefwcaps_sku caps_sku;
348 /* Defined in me_status.c for both romstage and ramstage */
349 void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
351 void intel_early_me_status(void);
352 int intel_early_me_init(void);
353 int intel_early_me_uma_size(void);
354 int intel_early_me_init_done(u8 status);