2 * From Coreboot file of the same name
4 * Copyright (C) 2011 The ChromiumOS Authors.
6 * SPDX-License-Identifier: GPL-2.0
9 #ifndef _ASM_ARCH_MODEL_206AX_H
10 #define _ASM_ARCH_MODEL_206AX_H
12 /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
13 #define SANDYBRIDGE_BCLK 100
15 #define CPUID_VMX (1 << 5)
16 #define CPUID_SMX (1 << 6)
17 #define MSR_FEATURE_CONFIG 0x13c
18 #define IA32_PLATFORM_DCA_CAP 0x1f8
19 #define IA32_MISC_ENABLE 0x1a0
20 #define MSR_TEMPERATURE_TARGET 0x1a2
21 #define IA32_THERM_INTERRUPT 0x19b
22 #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
23 #define ENERGY_POLICY_PERFORMANCE 0
24 #define ENERGY_POLICY_NORMAL 6
25 #define ENERGY_POLICY_POWERSAVE 15
26 #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
27 #define MSR_LT_LOCK_MEMORY 0x2e7
28 #define IA32_MC0_STATUS 0x401
30 #define MSR_MISC_PWR_MGMT 0x1aa
31 #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
33 #define MSR_PKGC3_IRTL 0x60a
34 #define MSR_PKGC6_IRTL 0x60b
35 #define MSR_PKGC7_IRTL 0x60c
36 #define IRTL_VALID (1 << 15)
37 #define IRTL_1_NS (0 << 10)
38 #define IRTL_32_NS (1 << 10)
39 #define IRTL_1024_NS (2 << 10)
40 #define IRTL_32768_NS (3 << 10)
41 #define IRTL_1048576_NS (4 << 10)
42 #define IRTL_33554432_NS (5 << 10)
43 #define IRTL_RESPONSE_MASK (0x3ff)
45 #define MSR_PP0_CURRENT_CONFIG 0x601
46 #define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */
47 #define MSR_PP1_CURRENT_CONFIG 0x602
48 #define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */
49 #define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */
50 #define MSR_PKG_POWER_SKU 0x614
52 #define IVB_CONFIG_TDP_MIN_CPUID 0x306a2
53 #define MSR_CONFIG_TDP_LEVEL1 0x649
54 #define MSR_CONFIG_TDP_LEVEL2 0x64a
55 #define MSR_CONFIG_TDP_CONTROL 0x64b
57 /* P-state configuration */
58 #define PSS_MAX_ENTRIES 8
59 #define PSS_RATIO_STEP 2
60 #define PSS_LATENCY_TRANSITION 10
61 #define PSS_LATENCY_BUSMASTER 10
63 /* Configure power limits for turbo mode */
64 void set_power_limits(u8 power_limit_1_time);
65 int cpu_config_tdp_levels(void);