2 * Copyright (c) 2014 Google, Inc
4 * From Coreboot src/southbridge/intel/bd82x6x/pch.h
6 * Copyright (C) 2008-2009 coresystems GmbH
7 * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
9 * SPDX-License-Identifier: GPL-2.0
12 #ifndef _ASM_ARCH_PCH_H
13 #define _ASM_ARCH_PCH_H
18 #define PCH_TYPE_CPT 0x1c /* CougarPoint */
19 #define PCH_TYPE_PPT 0x1e /* IvyBridge */
21 /* PCH stepping values for LPC device */
28 #define DEFAULT_GPIOBASE 0x0480
29 #define DEFAULT_PMBASE 0x0500
31 #define SMBUS_IO_BASE 0x0400
33 #define MAINBOARD_POWER_OFF 0
34 #define MAINBOARD_POWER_ON 1
35 #define MAINBOARD_POWER_KEEP 2
37 /* PCI Configuration Space (D30:F0): PCI2PCI */
47 #define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
48 #define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
49 #define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
50 #define PCH_ME_DEV PCI_BDF(0, 0x16, 0)
51 #define PCH_PCIE_DEV_SLOT 28
53 #define PCH_DEV PCI_BDF(0, 0, 0)
54 #define PCH_VIDEO_DEV PCI_BDF(0, 2, 0)
56 /* PCI Configuration Space (D31:F0): LPC */
57 #define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
58 #define SERIRQ_CNTL 0x64
60 #define GEN_PMCON_1 0xa0
61 #define GEN_PMCON_2 0xa2
62 #define GEN_PMCON_3 0xa4
64 #define ETR3_CWORWRE (1 << 18)
65 #define ETR3_CF9GR (1 << 20)
67 /* GEN_PMCON_3 bits */
68 #define RTC_BATTERY_DEAD (1 << 2)
69 #define RTC_POWER_FAILED (1 << 1)
70 #define SLEEP_AFTER_POWER_FAIL (1 << 0)
72 #define BIOS_CNTL 0xDC
73 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
74 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
75 #define GPIO_ROUT 0xb8
77 #define PIRQA_ROUT 0x60
78 #define PIRQB_ROUT 0x61
79 #define PIRQC_ROUT 0x62
80 #define PIRQD_ROUT 0x63
81 #define PIRQE_ROUT 0x68
82 #define PIRQF_ROUT 0x69
83 #define PIRQG_ROUT 0x6A
84 #define PIRQH_ROUT 0x6B
86 #define GEN_PMCON_1 0xa0
87 #define GEN_PMCON_2 0xa2
88 #define GEN_PMCON_3 0xa4
90 #define ETR3_CWORWRE (1 << 18)
91 #define ETR3_CF9GR (1 << 20)
94 #define ACPI_CNTL 0x44
95 #define BIOS_CNTL 0xDC
96 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
97 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
98 #define GPIO_ROUT 0xb8
100 /* PCI Configuration Space (D31:F1): IDE */
101 #define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
102 #define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2)
103 #define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5)
105 #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
106 #define IDE_SSDE1 (1 << 3)
107 #define IDE_SSDE0 (1 << 2)
108 #define IDE_PSDE1 (1 << 1)
109 #define IDE_PSDE0 (1 << 0)
111 #define IDE_SDMA_TIM 0x4a
113 #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
114 #define SIG_MODE_SEC_NORMAL (0 << 18)
115 #define SIG_MODE_SEC_TRISTATE (1 << 18)
116 #define SIG_MODE_SEC_DRIVELOW (2 << 18)
117 #define SIG_MODE_PRI_NORMAL (0 << 16)
118 #define SIG_MODE_PRI_TRISTATE (1 << 16)
119 #define SIG_MODE_PRI_DRIVELOW (2 << 16)
120 #define FAST_SCB1 (1 << 15)
121 #define FAST_SCB0 (1 << 14)
122 #define FAST_PCB1 (1 << 13)
123 #define FAST_PCB0 (1 << 12)
124 #define SCB1 (1 << 3)
125 #define SCB0 (1 << 2)
126 #define PCB1 (1 << 1)
127 #define PCB0 (1 << 0)
129 #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
130 #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
131 #define SATA_SP 0xd0 /* Scratchpad */
133 /* SATA IOBP Registers */
134 #define SATA_IOBP_SP0G3IR 0xea000151
135 #define SATA_IOBP_SP1G3IR 0xea000051
137 #define VCH 0x0000 /* 32bit */
138 #define VCAP1 0x0004 /* 32bit */
139 #define VCAP2 0x0008 /* 32bit */
140 #define PVC 0x000c /* 16bit */
141 #define PVS 0x000e /* 16bit */
143 #define V0CAP 0x0010 /* 32bit */
144 #define V0CTL 0x0014 /* 32bit */
145 #define V0STS 0x001a /* 16bit */
147 #define V1CAP 0x001c /* 32bit */
148 #define V1CTL 0x0020 /* 32bit */
149 #define V1STS 0x0026 /* 16bit */
151 #define RCTCL 0x0100 /* 32bit */
152 #define ESD 0x0104 /* 32bit */
153 #define ULD 0x0110 /* 32bit */
154 #define ULBA 0x0118 /* 64bit */
156 #define RP1D 0x0120 /* 32bit */
157 #define RP1BA 0x0128 /* 64bit */
158 #define RP2D 0x0130 /* 32bit */
159 #define RP2BA 0x0138 /* 64bit */
160 #define RP3D 0x0140 /* 32bit */
161 #define RP3BA 0x0148 /* 64bit */
162 #define RP4D 0x0150 /* 32bit */
163 #define RP4BA 0x0158 /* 64bit */
164 #define HDD 0x0160 /* 32bit */
165 #define HDBA 0x0168 /* 64bit */
166 #define RP5D 0x0170 /* 32bit */
167 #define RP5BA 0x0178 /* 64bit */
168 #define RP6D 0x0180 /* 32bit */
169 #define RP6BA 0x0188 /* 64bit */
171 #define RPC 0x0400 /* 32bit */
172 #define RPFN 0x0404 /* 32bit */
174 #define TRSR 0x1e00 /* 8bit */
175 #define TRCR 0x1e10 /* 64bit */
176 #define TWDR 0x1e18 /* 64bit */
178 #define IOTR0 0x1e80 /* 64bit */
179 #define IOTR1 0x1e88 /* 64bit */
180 #define IOTR2 0x1e90 /* 64bit */
181 #define IOTR3 0x1e98 /* 64bit */
183 #define TCTL 0x3000 /* 8bit */
191 #define DIR_IDR 12 /* Interrupt D Pin Offset */
192 #define DIR_ICR 8 /* Interrupt C Pin Offset */
193 #define DIR_IBR 4 /* Interrupt B Pin Offset */
194 #define DIR_IAR 0 /* Interrupt A Pin Offset */
205 /* IO Buffer Programming */
206 #define IOBPIRI 0x2330
209 #define IOBPS_RW_BX ((1 << 9)|(1 << 10))
210 #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10))
211 #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
213 #define D31IP 0x3100 /* 32bit */
214 #define D31IP_TTIP 24 /* Thermal Throttle Pin */
215 #define D31IP_SIP2 20 /* SATA Pin 2 */
216 #define D31IP_SMIP 12 /* SMBUS Pin */
217 #define D31IP_SIP 8 /* SATA Pin */
218 #define D30IP 0x3104 /* 32bit */
219 #define D30IP_PIP 0 /* PCI Bridge Pin */
220 #define D29IP 0x3108 /* 32bit */
221 #define D29IP_E1P 0 /* EHCI #1 Pin */
222 #define D28IP 0x310c /* 32bit */
223 #define D28IP_P8IP 28 /* PCI Express Port 8 */
224 #define D28IP_P7IP 24 /* PCI Express Port 7 */
225 #define D28IP_P6IP 20 /* PCI Express Port 6 */
226 #define D28IP_P5IP 16 /* PCI Express Port 5 */
227 #define D28IP_P4IP 12 /* PCI Express Port 4 */
228 #define D28IP_P3IP 8 /* PCI Express Port 3 */
229 #define D28IP_P2IP 4 /* PCI Express Port 2 */
230 #define D28IP_P1IP 0 /* PCI Express Port 1 */
231 #define D27IP 0x3110 /* 32bit */
232 #define D27IP_ZIP 0 /* HD Audio Pin */
233 #define D26IP 0x3114 /* 32bit */
234 #define D26IP_E2P 0 /* EHCI #2 Pin */
235 #define D25IP 0x3118 /* 32bit */
236 #define D25IP_LIP 0 /* GbE LAN Pin */
237 #define D22IP 0x3124 /* 32bit */
238 #define D22IP_KTIP 12 /* KT Pin */
239 #define D22IP_IDERIP 8 /* IDE-R Pin */
240 #define D22IP_MEI2IP 4 /* MEI #2 Pin */
241 #define D22IP_MEI1IP 0 /* MEI #1 Pin */
242 #define D20IP 0x3128 /* 32bit */
243 #define D20IP_XHCIIP 0
244 #define D31IR 0x3140 /* 16bit */
245 #define D30IR 0x3142 /* 16bit */
246 #define D29IR 0x3144 /* 16bit */
247 #define D28IR 0x3146 /* 16bit */
248 #define D27IR 0x3148 /* 16bit */
249 #define D26IR 0x314c /* 16bit */
250 #define D25IR 0x3150 /* 16bit */
251 #define D22IR 0x315c /* 16bit */
252 #define D20IR 0x3160 /* 16bit */
253 #define OIC 0x31fe /* 16bit */
255 #define SPI_FREQ_SWSEQ 0x3893
256 #define SPI_DESC_COMP0 0x38b0
257 #define SPI_FREQ_WR_ERA 0x38b4
259 #define DIR_ROUTE(a, b, c, d) \
260 (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
261 ((b) << DIR_IBR) | ((a) << DIR_IAR))
263 #define HPTC 0x3404 /* 32bit */
264 #define BUC 0x3414 /* 32bit */
265 #define PCH_DISABLE_GBE (1 << 5)
266 #define FD 0x3418 /* 32bit */
267 #define DISPBDF 0x3424 /* 16bit */
268 #define FD2 0x3428 /* 32bit */
269 #define CG 0x341c /* 32bit */
271 /* Function Disable 1 RCBA 0x3418 */
272 #define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
273 #define PCH_DISABLE_P2P (1 << 1)
274 #define PCH_DISABLE_SATA1 (1 << 2)
275 #define PCH_DISABLE_SMBUS (1 << 3)
276 #define PCH_DISABLE_HD_AUDIO (1 << 4)
277 #define PCH_DISABLE_EHCI2 (1 << 13)
278 #define PCH_DISABLE_LPC (1 << 14)
279 #define PCH_DISABLE_EHCI1 (1 << 15)
280 #define PCH_DISABLE_PCIE(x) (1 << (16 + x))
281 #define PCH_DISABLE_THERMAL (1 << 24)
282 #define PCH_DISABLE_SATA2 (1 << 25)
283 #define PCH_DISABLE_XHCI (1 << 27)
285 /* Function Disable 2 RCBA 0x3428 */
286 #define PCH_DISABLE_KT (1 << 4)
287 #define PCH_DISABLE_IDER (1 << 3)
288 #define PCH_DISABLE_MEI2 (1 << 2)
289 #define PCH_DISABLE_MEI1 (1 << 1)
290 #define PCH_ENABLE_DBDF (1 << 0)
293 #define GPIO_USE_SEL 0x00
294 #define GP_IO_SEL 0x04
296 #define GPO_BLINK 0x18
298 #define GPIO_USE_SEL2 0x30
299 #define GP_IO_SEL2 0x34
301 #define GPIO_USE_SEL3 0x40
302 #define GP_IO_SEL3 0x44
304 #define GP_RST_SEL1 0x60
305 #define GP_RST_SEL2 0x64
306 #define GP_RST_SEL3 0x68
310 #define WAK_STS (1 << 15)
311 #define PCIEXPWAK_STS (1 << 14)
312 #define PRBTNOR_STS (1 << 11)
313 #define RTC_STS (1 << 10)
314 #define PWRBTN_STS (1 << 8)
315 #define GBL_STS (1 << 5)
316 #define BM_STS (1 << 4)
317 #define TMROF_STS (1 << 0)
319 #define PCIEXPWAK_DIS (1 << 14)
320 #define RTC_EN (1 << 10)
321 #define PWRBTN_EN (1 << 8)
322 #define GBL_EN (1 << 5)
323 #define TMROF_EN (1 << 0)
325 #define SLP_EN (1 << 13)
326 #define SLP_TYP (7 << 10)
332 #define GBL_RLS (1 << 2)
333 #define BM_RLD (1 << 1)
334 #define SCI_EN (1 << 0)
336 #define PROC_CNT 0x10
340 #define PM2_CNT 0x50 /* mobile only */
341 #define GPE0_STS 0x20
342 #define PME_B0_STS (1 << 13)
343 #define PME_STS (1 << 11)
344 #define BATLOW_STS (1 << 10)
345 #define PCI_EXP_STS (1 << 9)
346 #define RI_STS (1 << 8)
347 #define SMB_WAK_STS (1 << 7)
348 #define TCOSCI_STS (1 << 6)
349 #define SWGPE_STS (1 << 2)
350 #define HOT_PLUG_STS (1 << 1)
352 #define PME_B0_EN (1 << 13)
353 #define PME_EN (1 << 11)
354 #define TCOSCI_EN (1 << 6)
356 #define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */
357 #define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */
358 #define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
359 #define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
360 #define MCSMI_EN (1 << 11) /* Trap microcontroller range access */
361 #define BIOS_RLS (1 << 7) /* asserts SCI on bit set */
362 #define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */
363 #define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */
364 #define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */
365 #define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */
366 #define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */
367 #define EOS (1 << 1) /* End of SMI (deassert SMI#) */
368 #define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */
370 #define ALT_GP_SMI_EN 0x38
371 #define ALT_GP_SMI_STS 0x3a
372 #define GPE_CNTL 0x42
373 #define DEVACT_STS 0x44
376 #define TCO1_STS 0x64
377 #define DMISCI_STS (1 << 9)
378 #define TCO2_STS 0x66
381 * pch_silicon_revision() - Read silicon device ID from the PCH
384 * @return silicon device ID
386 int pch_silicon_type(struct udevice *dev);
389 * pch_pch_iobp_update() - Update a pch register
392 * @address: Address to update
393 * @andvalue: Value to AND with existing value
394 * @orvalue: Value to OR with existing value
396 void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,