2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 /* Message Bus Ports */
11 #define MSG_PORT_MEM_ARBITER 0x00
12 #define MSG_PORT_HOST_BRIDGE 0x03
13 #define MSG_PORT_RMU 0x04
14 #define MSG_PORT_MEM_MGR 0x05
15 #define MSG_PORT_USB_AFE 0x14
16 #define MSG_PORT_PCIE_AFE 0x16
17 #define MSG_PORT_SOC_UNIT 0x31
19 /* Port 0x00: Memory Arbiter Message Port Registers */
21 /* Enhanced Configuration Space */
24 /* Port 0x03: Host Bridge Message Port Registers */
26 /* Host Miscellaneous Controls 2 */
29 #define HMISC2_SEGE 0x00000002
30 #define HMISC2_SEGF 0x00000004
31 #define HMISC2_SEGAB 0x00000010
33 /* Host Memory I/O Boundary */
35 #define HM_BOUND_LOCK 0x00000001
37 /* Extended Configuration Space */
40 /* Port 0x04: Remote Management Unit Message Port Registers */
42 /* ACPI PBLK Base Address Register */
45 /* SPI DMA Base Address Register */
46 #define SPI_DMA_BA 0x7a
48 /* Port 0x05: Memory Manager Message Port Registers */
50 /* eSRAM Block Page Control */
51 #define ESRAM_BLK_CTRL 0x82
52 #define ESRAM_BLOCK_MODE 0x10000000
54 /* Port 0x14: USB2 AFE Unit Port Registers */
56 #define USB2_GLOBAL_PORT 0x4001
57 #define USB2_PLL1 0x7f02
58 #define USB2_PLL2 0x7f03
59 #define USB2_COMPBG 0x7f04
61 /* Port 0x16: PCIe AFE Unit Port Registers */
63 #define PCIE_RXPICTRL0_L0 0x2080
64 #define PCIE_RXPICTRL0_L1 0x2180
66 /* Port 0x31: SoC Unit Port Registers */
68 /* PCIe Controller Config */
70 #define PCIE_CTLR_PRI_RST 0x00010000
71 #define PCIE_PHY_SB_RST 0x00020000
72 #define PCIE_CTLR_SB_RST 0x00040000
73 #define PCIE_PHY_LANE_RST 0x00090000
74 #define PCIE_CTLR_MAIN_RST 0x00100000
77 #define DRAM_BASE 0x00000000
78 #define DRAM_MAX_SIZE 0x80000000
81 #define ESRAM_SIZE 0x80000
83 /* Memory BAR Enable */
84 #define MEM_BAR_EN 0x00000001
87 #define IO_BAR_EN 0x80000000
89 /* 64KiB of RMU binary in flash */
90 #define RMU_BINARY_SIZE 0x10000
92 /* PCIe Root Port Configuration Registers */
94 #define PCIE_RP_CCFG 0xd0
95 #define CCFG_UPRS (1 << 14)
96 #define CCFG_UNRS (1 << 15)
97 #define CCFG_UNSD (1 << 23)
98 #define CCFG_UPSD (1 << 24)
100 #define PCIE_RP_MPC2 0xd4
101 #define MPC2_IPF (1 << 11)
103 #define PCIE_RP_MBC 0xf4
104 #define MBC_SBIC (3 << 16)
106 /* Legacy Bridge PCI Configuration Registers */
108 #define LB_PM1BLK 0x48
109 #define LB_GPE0BLK 0x4c
111 #define LB_PABCDRC 0x60
112 #define LB_PEFGHRC 0x64
113 #define LB_WDTBA 0x84
118 /* USB EHCI memory-mapped registers */
119 #define EHCI_INSNREG01 0x94
121 /* USB device memory-mapped registers */
122 #define USBD_INT_MASK 0x410
123 #define USBD_EP_INT_STS 0x414
124 #define USBD_EP_INT_MASK 0x418
128 /* Root Complex Register Block */
143 * qrk_pci_read_config_dword() - Read a configuration value
145 * @dev: PCI device address: bus, device and function
146 * @offset: Dword offset within the device's configuration space
147 * @valuep: Place to put the returned value
149 * Note: This routine is inlined to provide better performance on Quark
151 static inline void qrk_pci_read_config_dword(pci_dev_t dev, int offset,
154 outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
155 *valuep = inl(PCI_REG_DATA);
159 * qrk_pci_write_config_dword() - Write a PCI configuration value
161 * @dev: PCI device address: bus, device and function
162 * @offset: Dword offset within the device's configuration space
163 * @value: Value to write
165 * Note: This routine is inlined to provide better performance on Quark
167 static inline void qrk_pci_write_config_dword(pci_dev_t dev, int offset,
170 outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
171 outl(value, PCI_REG_DATA);
175 * board_assert_perst() - Assert the PERST# pin
177 * The CPU interface to the PERST# signal on Quark is platform dependent.
178 * Board-specific codes need supply this routine to assert PCIe slot reset.
180 * The tricky part in this routine is that any APIs that may trigger PCI
181 * enumeration process are strictly forbidden, as any access to PCIe root
182 * port's configuration registers will cause system hang while it is held
185 void board_assert_perst(void);
188 * board_deassert_perst() - De-assert the PERST# pin
190 * The CPU interface to the PERST# signal on Quark is platform dependent.
191 * Board-specific codes need supply this routine to de-assert PCIe slot reset.
193 * The tricky part in this routine is that any APIs that may trigger PCI
194 * enumeration process are strictly forbidden, as any access to PCIe root
195 * port's configuration registers will cause system hang while it is held
198 void board_deassert_perst(void);
200 #endif /* __ASSEMBLY__ */
202 #endif /* _QUARK_H_ */