3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
5 * SPDX-License-Identifier: GPL-2.0+
8 /* i8259.h i8259 PIC Registers */
10 #ifndef _ASMI386_I8259_H_
11 #define _ASMI386_I8959_H_
13 /* PIC I/O mapped registers */
14 #define IRR 0x0 /* Interrupt Request Register */
15 #define ISR 0x0 /* In-Service Register */
16 #define ICW1 0x0 /* Initialization Control Word 1 */
17 #define OCW2 0x0 /* Operation Control Word 2 */
18 #define OCW3 0x0 /* Operation Control Word 3 */
19 #define ICW2 0x1 /* Initialization Control Word 2 */
20 #define ICW3 0x1 /* Initialization Control Word 3 */
21 #define ICW4 0x1 /* Initialization Control Word 4 */
22 #define IMR 0x1 /* Interrupt Mask Register */
24 /* IRR, IMR, ISR and ICW3 bits */
25 #define IR7 0x80 /* IR7 */
26 #define IR6 0x40 /* IR6 */
27 #define IR5 0x20 /* IR5 */
28 #define IR4 0x10 /* IR4 */
29 #define IR3 0x08 /* IR3 */
30 #define IR2 0x04 /* IR2 */
31 #define IR1 0x02 /* IR1 */
32 #define IR0 0x01 /* IR0 */
35 #define SEOI_IR7 0x07 /* IR7 */
36 #define SEOI_IR6 0x06 /* IR6 */
37 #define SEOI_IR5 0x05 /* IR5 */
38 #define SEOI_IR4 0x04 /* IR4 */
39 #define SEOI_IR3 0x03 /* IR3 */
40 #define SEOI_IR2 0x02 /* IR2 */
41 #define SEOI_IR1 0x01 /* IR1 */
42 #define SEOI_IR0 0x00 /* IR0 */
45 #define OCW2_RCLR 0x00 /* Rotate/clear */
46 #define OCW2_NEOI 0x20 /* Non specific EOI */
47 #define OCW2_NOP 0x40 /* NOP */
48 #define OCW2_SEOI 0x60 /* Specific EOI */
49 #define OCW2_RSET 0x80 /* Rotate/set */
50 #define OCW2_REOI 0xa0 /* Rotate on non specific EOI */
51 #define OCW2_PSET 0xc0 /* Priority Set Command */
52 #define OCW2_RSEOI 0xe0 /* Rotate on specific EOI */
55 #define ICW1_SEL 0x10 /* Select ICW1 */
56 #define ICW1_LTIM 0x08 /* Level-Triggered Interrupt Mode */
57 #define ICW1_ADI 0x04 /* Address Interval */
58 #define ICW1_SNGL 0x02 /* Single PIC */
59 #define ICW1_EICW4 0x01 /* Expect initilization ICW4 */
62 * ICW2 is the starting vector number
64 * ICW2 is bit-mask of present slaves for a master device,
65 * or the slave ID for a slave device
69 #define ICW4_AEOI 0x02 /* Automatic EOI Mode */
70 #define ICW4_PM 0x01 /* Microprocessor Mode */
77 #endif /* _ASMI386_I8959_H_ */