2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <dt-bindings/interrupt-router/intel-irq.h>
13 * Intel interrupt router configuration mechanism
15 * There are two known ways of Intel interrupt router configuration mechanism
16 * so far. On most cases, the IRQ routing configuraiton is controlled by PCI
17 * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0).
18 * On some newer platforms like BayTrail and Braswell, the IRQ routing is now
19 * in the IBASE register block where IBASE is memory-mapped.
27 * Intel interrupt router control block
29 * Its members' value will be filled in based on device tree's input.
31 * @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE
32 * @link_base: link value base number
33 * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means
34 * IRQ N is available to be routed
35 * @lb_bdf: irq router's PCI bus/device/function number encoding
36 * @ibase: IBASE register block base address
52 /* PIRQ link number and value conversion */
53 #define LINK_V2N(link, base) (link - base)
54 #define LINK_N2V(link, base) (link + base)
56 #define PIRQ_BITMAP 0xdef8
59 * irq_router_common_init() - Perform common x86 interrupt init
61 * This creates the PIRQ routing table and routes the IRQs
63 int irq_router_common_init(struct udevice *dev);
65 #endif /* _ARCH_IRQ_H_ */