1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
9 #include <dt-bindings/interrupt-router/intel-irq.h>
12 * Intel interrupt router configuration mechanism
14 * There are two known ways of Intel interrupt router configuration mechanism
15 * so far. On most cases, the IRQ routing configuraiton is controlled by PCI
16 * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0).
17 * On some newer platforms like BayTrail and Braswell, the IRQ routing is now
18 * in the IBASE register block where IBASE is memory-mapped.
26 * Intel interrupt router control block
28 * Its members' value will be filled in based on device tree's input.
30 * @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE
31 * @link_base: link value base number
32 * @link_num: number of PIRQ links supported
33 * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means
34 * IRQ N is available to be routed
35 * @lb_bdf: irq router's PCI bus/device/function number encoding
36 * @ibase: IBASE register block base address
37 * @actl_8bit: ACTL register width is 8-bit (for ICH series chipset)
38 * @actl_addr: ACTL register offset
58 * pirq_reg_to_linkno() - Convert a PIRQ routing register offset to link number
60 * @reg: PIRQ routing register offset from the base address
61 * @base: PIRQ routing register block base address
62 * @return: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc)
64 static inline int pirq_reg_to_linkno(int reg, int base)
70 * pirq_linkno_to_reg() - Convert a PIRQ link number to routing register offset
72 * @linkno: PIRQ link number (0 for PIRQA, 1 for PIRQB, etc)
73 * @base: PIRQ routing register block base address
74 * @return: PIRQ routing register offset from the base address
76 static inline int pirq_linkno_to_reg(int linkno, int base)
81 #define PIRQ_BITMAP 0xdef8
83 #endif /* _ARCH_IRQ_H_ */