2 * From Coreboot src/southbridge/intel/bd82x6x/me.h
4 * Coreboot copies lots of code around. Here we are trying to keep the common
5 * code in a separate file to reduce code duplication and hopefully make it
6 * easier to add new platform.
8 * Copyright (C) 2016 Google, Inc
10 * SPDX-License-Identifier: GPL-2.0
13 #ifndef __ASM_ME_COMMON_H
14 #define __ASM_ME_COMMON_H
16 #include <linux/compiler.h>
17 #include <linux/types.h>
20 #define MCHBAR_PEI_VERSION 0x5034
22 #define ME_RETRY 100000 /* 1 second */
23 #define ME_DELAY 10 /* 10 us */
26 * Management Engine PCI registers
29 #define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */
30 #define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */
32 #define PCI_ME_HFS 0x40
33 #define ME_HFS_CWS_RESET 0
34 #define ME_HFS_CWS_INIT 1
35 #define ME_HFS_CWS_REC 2
36 #define ME_HFS_CWS_NORMAL 5
37 #define ME_HFS_CWS_WAIT 6
38 #define ME_HFS_CWS_TRANS 7
39 #define ME_HFS_CWS_INVALID 8
40 #define ME_HFS_STATE_PREBOOT 0
41 #define ME_HFS_STATE_M0_UMA 1
42 #define ME_HFS_STATE_M3 4
43 #define ME_HFS_STATE_M0 5
44 #define ME_HFS_STATE_BRINGUP 6
45 #define ME_HFS_STATE_ERROR 7
46 #define ME_HFS_ERROR_NONE 0
47 #define ME_HFS_ERROR_UNCAT 1
48 #define ME_HFS_ERROR_IMAGE 3
49 #define ME_HFS_ERROR_DEBUG 4
50 #define ME_HFS_MODE_NORMAL 0
51 #define ME_HFS_MODE_DEBUG 2
52 #define ME_HFS_MODE_DIS 3
53 #define ME_HFS_MODE_OVER_JMPR 4
54 #define ME_HFS_MODE_OVER_MEI 5
55 #define ME_HFS_BIOS_DRAM_ACK 1
56 #define ME_HFS_ACK_NO_DID 0
57 #define ME_HFS_ACK_RESET 1
58 #define ME_HFS_ACK_PWR_CYCLE 2
59 #define ME_HFS_ACK_S3 3
60 #define ME_HFS_ACK_S4 4
61 #define ME_HFS_ACK_S5 5
62 #define ME_HFS_ACK_GBL_RESET 6
63 #define ME_HFS_ACK_CONTINUE 7
69 u32 operation_state:3;
70 u32 fw_init_complete:1;
72 u32 update_in_progress:1;
76 u32 boot_options_present:1;
81 #define PCI_ME_UMA 0x44
91 #define PCI_ME_H_GS 0x4c
92 #define ME_INIT_DONE 1
93 #define ME_INIT_STATUS_SUCCESS 0
94 #define ME_INIT_STATUS_NOMEM 1
95 #define ME_INIT_STATUS_ERROR 2
100 u32 rapid_start:1; /* Broadwell only */
105 #define PCI_ME_GMES 0x48
106 #define ME_GMES_PHASE_ROM 0
107 #define ME_GMES_PHASE_BUP 1
108 #define ME_GMES_PHASE_UKERNEL 2
109 #define ME_GMES_PHASE_POLICY 3
110 #define ME_GMES_PHASE_MODULE 4
111 #define ME_GMES_PHASE_UNKNOWN 5
112 #define ME_GMES_PHASE_HOST 6
118 u32 cpu_replaced_sts:1;
121 u32 warm_rst_req_for_df:1;
122 u32 cpu_replaced_valid:1;
127 u32 current_pmevent:4;
131 #define PCI_ME_HERES 0xbc
132 #define PCI_ME_EXT_SHA1 0x00
133 #define PCI_ME_EXT_SHA256 0x02
134 #define PCI_ME_HER(x) (0xc0+(4*(x)))
137 u32 extend_reg_algorithm:4;
139 u32 extend_feature_present:1;
140 u32 extend_reg_valid:1;
144 * Management Engine MEI registers
147 #define MEI_H_CB_WW 0x00
148 #define MEI_H_CSR 0x04
149 #define MEI_ME_CB_RW 0x08
150 #define MEI_ME_CSR_HA 0x0c
153 u32 interrupt_enable:1;
154 u32 interrupt_status:1;
155 u32 interrupt_generate:1;
159 u32 buffer_read_ptr:8;
160 u32 buffer_write_ptr:8;
164 #define MEI_ADDRESS_CORE 0x01
165 #define MEI_ADDRESS_AMT 0x02
166 #define MEI_ADDRESS_RESERVED 0x03
167 #define MEI_ADDRESS_WDT 0x04
168 #define MEI_ADDRESS_MKHI 0x07
169 #define MEI_ADDRESS_ICC 0x08
170 #define MEI_ADDRESS_THERMAL 0x09
172 #define MEI_HOST_ADDRESS 0
175 u32 client_address:8;
182 #define MKHI_GROUP_ID_CBM 0x00
183 #define MKHI_GROUP_ID_FWCAPS 0x03
184 #define MKHI_GROUP_ID_MDES 0x08
185 #define MKHI_GROUP_ID_GEN 0xff
187 #define MKHI_GET_FW_VERSION 0x02
188 #define MKHI_END_OF_POST 0x0c
189 #define MKHI_FEATURE_OVERRIDE 0x14
191 /* Ivybridge only: */
192 #define MKHI_GLOBAL_RESET 0x0b
193 #define MKHI_FWCAPS_GET_RULE 0x02
194 #define MKHI_MDES_ENABLE 0x09
196 /* Broadwell only: */
197 #define MKHI_GLOBAL_RESET 0x0b
198 #define MKHI_FWCAPS_GET_RULE 0x02
199 #define MKHI_GROUP_ID_HMRFPO 0x05
200 #define MKHI_HMRFPO_LOCK 0x02
201 #define MKHI_HMRFPO_LOCK_NOACK 0x05
202 #define MKHI_MDES_ENABLE 0x09
203 #define MKHI_END_OF_POST_NOACK 0x1a
213 struct me_fw_version {
216 u16 code_build_number;
220 u16 recovery_build_number;
221 u16 recovery_hot_fix;
225 #define HECI_EOP_STATUS_SUCCESS 0x0
226 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
228 #define CBM_RR_GLOBAL_RESET 0x01
230 #define GLOBAL_RESET_BIOS_MRC 0x01
231 #define GLOBAL_RESET_BIOS_POST 0x02
232 #define GLOBAL_RESET_MEBX 0x03
234 struct me_global_reset {
243 ME_RECOVERY_BIOS_PATH,
244 ME_DISABLE_BIOS_PATH,
245 ME_FIRMWARE_UPDATE_BIOS_PATH,
248 struct __packed mefwcaps_sku {
252 u32 small_business:1;
253 u32 l3manageability:1;
258 u32 icc_over_clocking:1;
271 struct __packed tdt_state_flag {
273 u16 authenticate_module:1;
274 u16 s3authentication:1;
275 u16 flash_wear_out:1;
276 u16 flash_variable_security:1;
277 u16 wwan3gpresent:1; /* ivybridge only */
278 u16 wwan3goob:1; /* ivybridge only */
282 struct __packed tdt_state_info {
284 u8 last_theft_trigger;
285 struct tdt_state_flag flags;
288 struct __packed mbp_rom_bist_data {
294 struct __packed mbp_platform_key {
298 struct __packed mbp_header {
304 struct __packed mbp_item_header {
311 struct __packed me_fwcaps {
314 struct mefwcaps_sku caps_sku;
319 * intel_me_status() - Check Intel Management Engine status
321 * @me_dev: Management engine PCI device
323 void intel_me_status(struct udevice *me_dev);
326 * intel_early_me_init() - Early Intel Management Engine init
328 * @me_dev: Management engine PCI device
329 * @return 0 if OK, -ve on error
331 int intel_early_me_init(struct udevice *me_dev);
334 * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine
336 * @me_dev: Management engine PCI device
337 * @return UMA size if OK, -EINVAL on error
339 int intel_early_me_uma_size(struct udevice *me_dev);
342 * intel_early_me_init_done() - Complete Intel Management Engine init
344 * @dev: Northbridge device
345 * @me_dev: Management engine PCI device
346 * @status: Status result (ME_INIT_...)
347 * @return 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT
348 * if ME did not respond
350 int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
353 int intel_me_hsio_version(struct udevice *dev, uint16_t *version,
356 static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr,
361 dm_pci_read_config32(me_dev, offset, &dword);
362 memcpy(ptr, &dword, sizeof(dword));
365 static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr,
370 memcpy(&dword, ptr, sizeof(dword));
371 dm_pci_write_config32(me_dev, offset, dword);