3 * Graeme Russ, <graeme.russ@gmail.com>
6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
8 * SPDX-License-Identifier: GPL-2.0+
12 * This file provides the interrupt handling functionality for systems
13 * based on the standard PC/AT architecture using two cascaded i8259
14 * Programmable Interrupt Controllers.
19 #include <asm/i8259.h>
20 #include <asm/ibmpc.h>
21 #include <asm/interrupt.h>
23 #if CONFIG_SYS_NUM_IRQS != 16
24 #error "CONFIG_SYS_NUM_IRQS must equal 16 if CONFIG_SYS_NUM_IRQS is defined"
31 /* Mask all interrupts */
32 outb(0xff, MASTER_PIC + IMR);
33 outb(0xff, SLAVE_PIC + IMR);
36 /* Place master PIC interrupts at INT20 */
37 /* ICW3, One slave PIC is present */
38 outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1);
39 outb(0x20, MASTER_PIC + ICW2);
40 outb(IR2, MASTER_PIC + ICW3);
41 outb(ICW4_PM, MASTER_PIC + ICW4);
43 for (i = 0; i < 8; i++)
44 outb(OCW2_SEOI | i, MASTER_PIC + OCW2);
47 /* Place slave PIC interrupts at INT28 */
49 outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1);
50 outb(0x28, SLAVE_PIC + ICW2);
51 outb(0x02, SLAVE_PIC + ICW3);
52 outb(ICW4_PM, SLAVE_PIC + ICW4);
54 for (i = 0; i < 8; i++)
55 outb(OCW2_SEOI | i, SLAVE_PIC + OCW2);
58 * Enable cascaded interrupts by unmasking the cascade IRQ pin of
63 /* Interrupt 9 should be level triggered (SCI). The OS might do this */
64 configure_irq_trigger(9, true);
69 void mask_irq(int irq)
73 if (irq >= CONFIG_SYS_NUM_IRQS)
77 imr_port = SLAVE_PIC + IMR;
79 imr_port = MASTER_PIC + IMR;
81 outb(inb(imr_port) | (1 << (irq & 7)), imr_port);
84 void unmask_irq(int irq)
88 if (irq >= CONFIG_SYS_NUM_IRQS)
92 imr_port = SLAVE_PIC + IMR;
94 imr_port = MASTER_PIC + IMR;
96 outb(inb(imr_port) & ~(1 << (irq & 7)), imr_port);
99 void specific_eoi(int irq)
101 if (irq >= CONFIG_SYS_NUM_IRQS)
106 * IRQ is on the slave - Issue a corresponding EOI to the
107 * slave PIC and an EOI for IRQ2 (the cascade interrupt)
110 outb(OCW2_SEOI | (irq & 7), SLAVE_PIC + OCW2);
114 outb(OCW2_SEOI | irq, MASTER_PIC + OCW2);
120 void configure_irq_trigger(int int_num, bool is_level_triggered)
122 u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8);
124 debug("%s: current interrupts are 0x%x\n", __func__, int_bits);
125 if (is_level_triggered)
126 int_bits |= (1 << int_num);
128 int_bits &= ~(1 << int_num);
130 /* Write new values */
131 debug("%s: try to set interrupts 0x%x\n", __func__, int_bits);
132 outb((u8)(int_bits & 0xff), ELCR1);
133 outb((u8)(int_bits >> 8), ELCR2);
135 #ifdef PARANOID_IRQ_TRIGGERS
137 * Try reading back the new values. This seems like an error but is
140 if (inb(ELCR1) != (int_bits & 0xff)) {
141 printf("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
142 __func__, (int_bits & 0xff), inb(ELCR1));
145 if (inb(ELCR2) != (int_bits >> 8)) {
146 printf("%s: higher order bits are wrong: want 0x%x, got 0x%x\n",
147 __func__, (int_bits>>8), inb(ELCR2));