1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Google, Inc
16 #include <dm/pinctrl.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 #define GPIO_USESEL_OFFSET(x) (x)
21 #define GPIO_IOSEL_OFFSET(x) (x + 4)
22 #define GPIO_LVL_OFFSET(x) ((x) ? (x) + 8 : 0xc)
25 #define IOPAD_MODE_MASK 0x7
26 #define IOPAD_PULL_ASSIGN_SHIFT 7
27 #define IOPAD_PULL_ASSIGN_MASK (0x3 << IOPAD_PULL_ASSIGN_SHIFT)
28 #define IOPAD_PULL_STRENGTH_SHIFT 9
29 #define IOPAD_PULL_STRENGTH_MASK (0x3 << IOPAD_PULL_STRENGTH_SHIFT)
31 static int ich6_pinctrl_set_value(uint16_t base, unsigned offset, int value)
34 setio_32(base, 1UL << offset);
36 clrio_32(base, 1UL << offset);
41 static int ich6_pinctrl_set_function(uint16_t base, unsigned offset, int func)
44 setio_32(base, 1UL << offset);
46 clrio_32(base, 1UL << offset);
51 static int ich6_pinctrl_set_direction(uint16_t base, unsigned offset, int dir)
54 setio_32(base, 1UL << offset);
56 clrio_32(base, 1UL << offset);
61 static int ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)
70 * GPIO node is not mandatory, so we only do the pinmuxing if the
73 ret = fdtdec_get_int_array(gd->fdt_blob, pin_node, "gpio-offset",
76 /* Do we want to force the GPIO mode? */
77 is_gpio = fdtdec_get_bool(gd->fdt_blob, pin_node, "mode-gpio");
79 ich6_pinctrl_set_function(GPIO_USESEL_OFFSET(gpiobase) +
80 gpio_offset[0], gpio_offset[1],
83 dir = fdtdec_get_int(gd->fdt_blob, pin_node, "direction", -1);
85 ich6_pinctrl_set_direction(GPIO_IOSEL_OFFSET(gpiobase) +
86 gpio_offset[0], gpio_offset[1],
89 val = fdtdec_get_int(gd->fdt_blob, pin_node, "output-value",
92 ich6_pinctrl_set_value(GPIO_LVL_OFFSET(gpiobase) +
93 gpio_offset[0], gpio_offset[1],
96 invert = fdtdec_get_bool(gd->fdt_blob, pin_node, "invert");
98 setio_32(gpiobase + GPI_INV, 1 << gpio_offset[1]);
99 debug("gpio %#x bit %d, is_gpio %d, dir %d, val %d, invert %d\n",
100 gpio_offset[0], gpio_offset[1], is_gpio, dir, val,
104 /* if iobase is present, let's configure the pad */
109 * The offset for the same pin for the IOBASE and GPIOBASE are
110 * different, so instead of maintaining a lookup table,
111 * the device tree should provide directly the correct
112 * value for both mapping.
114 pad_offset = fdtdec_get_int(gd->fdt_blob, pin_node,
116 if (pad_offset == -1)
119 /* compute the absolute pad address */
120 iobase_addr = iobase + pad_offset;
123 * Do we need to set a specific function mode?
124 * If someone put also 'mode-gpio', this option will
125 * be just ignored by the controller
127 val = fdtdec_get_int(gd->fdt_blob, pin_node, "mode-func", -1);
129 clrsetbits_le32(iobase_addr, IOPAD_MODE_MASK, val);
131 /* Configure the pull-up/down if needed */
132 val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-assign", -1);
134 clrsetbits_le32(iobase_addr,
135 IOPAD_PULL_ASSIGN_MASK,
136 val << IOPAD_PULL_ASSIGN_SHIFT);
138 val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-strength",
141 clrsetbits_le32(iobase_addr,
142 IOPAD_PULL_STRENGTH_MASK,
143 val << IOPAD_PULL_STRENGTH_SHIFT);
145 debug("%s: pad cfg [0x%x]: %08x\n", __func__, pad_offset,
152 static int ich6_pinctrl_probe(struct udevice *dev)
160 debug("%s: start\n", __func__);
161 ret = uclass_first_device(UCLASS_PCH, &pch);
168 * Get the memory/io base address to configure every pins.
169 * IOBASE is used to configure the mode/pads
170 * GPIOBASE is used to configure the direction and default value
172 ret = pch_get_gpio_base(pch, &gpiobase);
174 debug("%s: invalid GPIOBASE address (%08x)\n", __func__,
180 * Get the IOBASE, this is not mandatory as this is not
181 * supported by all the CPU
183 ret = pch_get_io_base(pch, &iobase);
184 if (ret && ret != -ENOSYS) {
185 debug("%s: invalid IOBASE address (%08x)\n", __func__, iobase);
189 for (pin_node = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev));
191 pin_node = fdt_next_subnode(gd->fdt_blob, pin_node)) {
192 /* Configure the pin */
193 ret = ich6_pinctrl_cfg_pin(gpiobase, iobase, pin_node);
195 debug("%s: invalid configuration for the pin %d\n",
200 debug("%s: done\n", __func__);
205 static const struct udevice_id ich6_pinctrl_match[] = {
206 { .compatible = "intel,x86-pinctrl", .data = X86_SYSCON_PINCONF },
210 U_BOOT_DRIVER(ich6_pinctrl) = {
211 .name = "ich6_pinctrl",
213 .of_match = ich6_pinctrl_match,
214 .probe = ich6_pinctrl_probe,