2 * Copyright (c) 2012 The Chromium OS Authors.
4 * TSC calibration codes are adapted from Linux kernel
5 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/i8254.h>
14 #include <asm/ibmpc.h>
16 #include <asm/u-boot-x86.h>
18 /* CPU reference clock frequency: in KHz */
20 #define FREQ_100 99840
21 #define FREQ_133 133200
22 #define FREQ_166 166400
24 #define MAX_NUM_FREQS 8
26 DECLARE_GLOBAL_DATA_PTR;
29 * According to Intel 64 and IA-32 System Programming Guide,
30 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
31 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
32 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
33 * so we need manually differentiate SoC families. This is what the
34 * field msr_plat does.
37 u8 x86_family; /* CPU family */
38 u8 x86_model; /* model */
39 u8 msr_plat; /* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
40 u32 freqs[MAX_NUM_FREQS];
43 static struct freq_desc freq_desc_tables[] = {
45 { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
47 { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
49 { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
51 { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
53 { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
56 static int match_cpu(u8 family, u8 model)
60 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
61 if ((family == freq_desc_tables[i].x86_family) &&
62 (model == freq_desc_tables[i].x86_model))
69 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
70 #define id_to_freq(cpu_index, freq_id) \
71 (freq_desc_tables[cpu_index].freqs[freq_id])
74 * Do MSR calibration only for known/supported CPUs.
76 * Returns the calibration value or 0 if MSR calibration failed.
78 static unsigned long try_msr_calibrate_tsc(void)
80 u32 lo, hi, ratio, freq_id, freq;
84 cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
88 if (freq_desc_tables[cpu_index].msr_plat) {
89 rdmsr(MSR_PLATFORM_INFO, lo, hi);
90 ratio = (lo >> 8) & 0x1f;
92 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
93 ratio = (hi >> 8) & 0x1f;
95 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
100 /* Get FSB FREQ ID */
101 rdmsr(MSR_FSB_FREQ, lo, hi);
103 freq = id_to_freq(cpu_index, freq_id);
104 debug("Resolved frequency ID: %u, frequency: %u KHz\n", freq_id, freq);
108 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
109 res = freq * ratio / 1000;
110 debug("TSC runs at %lu MHz\n", res);
115 debug("Fast TSC calibration using MSR failed\n");
119 void timer_set_base(u64 base)
121 gd->arch.tsc_base = base;
125 * Get the number of CPU time counter ticks since it was read first time after
126 * restart. This yields a free running counter guaranteed to take almost 6
127 * years to wrap around even at 100GHz clock rate.
129 u64 __attribute__((no_instrument_function)) get_ticks(void)
131 u64 now_tick = rdtsc();
133 /* We assume that 0 means the base hasn't been set yet */
134 if (!gd->arch.tsc_base)
135 panic("No tick base available");
136 return now_tick - gd->arch.tsc_base;
139 /* Get the speed of the TSC timer in MHz */
140 unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)
142 unsigned long fast_calibrate;
144 fast_calibrate = try_msr_calibrate_tsc();
146 panic("TSC frequency is ZERO");
148 return fast_calibrate;
151 unsigned long get_tbclk(void)
153 return get_tbclk_mhz() * 1000 * 1000;
156 static ulong get_ms_timer(void)
158 return (get_ticks() * 1000) / get_tbclk();
161 ulong get_timer(ulong base)
163 return get_ms_timer() - base;
166 ulong __attribute__((no_instrument_function)) timer_get_us(void)
168 return get_ticks() / get_tbclk_mhz();
171 ulong timer_get_boot_us(void)
173 return timer_get_us();
176 void __udelay(unsigned long usec)
178 u64 now = get_ticks();
181 stop = now + usec * get_tbclk_mhz();
183 while ((int64_t)(stop - get_ticks()) > 0)
189 #ifdef CONFIG_SYS_PCAT_TIMER
190 /* Set up the PCAT timer if required */