2 * (C) Copyright 2008 - 2013 Tensilica Inc.
3 * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
5 * SPDX-License-Identifier: GPL-2.0+
12 * We currently run always with caches enabled when running from memory.
13 * Xtensa version D or later will support changing cache behavior, so
14 * we could implement it if necessary.
17 int dcache_status(void)
22 void dcache_enable(void)
26 void dcache_disable(void)
30 void flush_cache(ulong start_addr, ulong size)
32 __flush_invalidate_dcache_range(start_addr, size);
33 __invalidate_icache_range(start_addr, size);
36 void flush_dcache_all(void)
39 __invalidate_icache_all();
42 void flush_dcache_range(ulong start_addr, ulong end_addr)
44 __flush_invalidate_dcache_range(start_addr, end_addr - start_addr);
47 void invalidate_dcache_range(ulong start, ulong stop)
49 __invalidate_dcache_range(start, stop - start);
52 void invalidate_dcache_all(void)
54 __invalidate_dcache_all();
57 void invalidate_icache_all(void)
59 __invalidate_icache_all();