1 ; General settings that can be overwritten in the host code
2 ; that calls the AISGen library.
5 ; Can be 8 or 16 - used in emifa
8 ; SPIMASTER,I2CMASTER,EMIFA,NAND,EMAC,UART,PCI,HPI,USB,MMC_SD,VLYNQ,RAW
11 ; 8,16,24 - used for SPI,I2C
14 ; NO_CRC,SECTION_CRC,SINGLE_CRC
17 ; This section allows setting the PLL0 system clock with a
18 ; specified multiplier and divider as shown. The clock source
19 ; can also be chosen for internal or external.
20 ; |------24|------16|-------8|-------0|
21 ; PLL0CFG0: | CLKMODE| PLLM | PREDIV | POSTDIV|
22 ; PLL0CFG1: | RSVD | PLLDIV1| PLLDIV3| PLLDIV7|
24 ;PLL0CFG0 = 0x00180001
25 ;PLL0CFG1 = 0x00000205
30 PERIPHCLKCFG = 0x00000051
32 ; This section allows setting up the PLL1. Usually this will
33 ; take place as part of the EMIF3a DDR setup. The format of
34 ; the input args is as follows:
35 ; |------24|------16|-------8|-------0|
36 ; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
37 ; PLL1CFG1: | RSVD | PLLDIV3|
42 ; This section lets us configure the peripheral interface
43 ; of the current booting peripheral (I2C, SPI, or UART).
44 ; Use with caution. The format of the PERIPHCLKCFG field
46 ; SPI: |------24|------16|-------8|-------0|
49 ; I2C: |------24|------16|-------8|-------0|
50 ; | RSVD |PRESCALE| CLKL | CLKH |
52 ; UART: |------24|------16|-------8|-------0|
53 ; | RSVD | OSR | DLH | DLL |
55 PERIPHCLKCFG = 0x00000051
57 ; This section can be used to configure the PLL1 and the EMIF3a registers
58 ; for starting the DDR2 interface.
59 ; See PLL1CONFIG section for the format of the PLL1CFG fields.
60 ; |------24|------16|-------8|-------0|
61 ; PLL1CFG0: | PLL1CFG |
62 ; PLL1CFG1: | PLL1CFG |
63 ; DDRPHYC1R: | DDRPHYC1R |
66 ; SDTIMR2: | SDTIMR2 |
68 ; CLK2XSRC: | CLK2XSRC |
72 DDRPHYC1R = 0x000000C2
79 ; This section can be used to configure the EMIFA to use
80 ; CS0 as an SDRAM interface. The fields required to do this
82 ; |------24|------16|-------8|-------0|
85 ; SDRSRPDEXIT: | SDRSRPDEXIT |
87 ; DIV4p5_CLK_ENABLE: | DIV4p5_CLK_ENABLE |
91 ;SDRSRPDEXIT = 0x00000009
93 ;DIV4p5_CLK_ENABLE = 0x00000001
95 ; This section can be used to configure the async chip selects
96 ; of the EMIFA (CS2-CS5). The fields required to do this
98 ; |------24|------16|-------8|-------0|
103 ; NANDFCR: | NANDFCR |
109 ;NANDFCR = 0x00000000
117 ; This section should be used in place of PLL0CONFIG when
118 ; the I2C, SPI, or UART modes are being used. This ensures that
119 ; the system PLL and the peripheral's clocks are changed together.
120 ; See PLL0CONFIG section for the format of the PLL0CFG fields.
121 ; See PERIPHCLKCFG section for the format of the CLKCFG field.
122 ; |------24|------16|-------8|-------0|
123 ; PLL0CFG0: | PLL0CFG |
124 ; PLL0CFG1: | PLL0CFG |
125 ; PERIPHCLKCFG: | CLKCFG |
127 ;PLL0CFG0 = 0x00180001
128 ;PLL0CFG1 = 0x00000205
129 ;PERIPHCLKCFG = 0x00010032
131 ; This section should be used to setup the power state of modules
132 ; of the two PSCs. This section can be included multiple times to
133 ; allow the configuration of any or all of the device modules.
134 ; |------24|------16|-------8|-------0|
135 ; LPSCCFG: | PSCNUM | MODULE | PD | STATE |
139 ; This section allows setting of a single PINMUX register.
140 ; This section can be included multiple times to allow setting
141 ; as many PINMUX registers as needed.
142 ; |------24|------16|-------8|-------0|
151 ; No Params required - simply include this section for the fast boot
152 ; function to be called
155 ; This section allows setting up the PLL1. Usually this will
156 ; take place as part of the EMIF3a DDR setup. The format of
157 ; the input args is as follows:
158 ; |------24|------16|-------8|-------0|
159 ; PLL1CFG0: | PLLM| POSTDIV| PLLDIV1| PLLDIV2|
160 ; PLL1CFG1: | RSVD | PLLDIV3|
162 ;PLL1CFG0 = 0x15010001
163 ;PLL1CFG1 = 0x00000002
165 ; This section can be used to configure the PLL1 and the EMIF3a registers
166 ; for starting the DDR2 interface on ARM-boot D800K002 devices.
167 ; |------24|------16|-------8|-------0|
168 ; DDRPHYC1R: | DDRPHYC1R |
171 ; SDTIMR2: | SDTIMR2 |
173 ; CLK2XSRC: | CLK2XSRC |
174 ;[ARM_EMIF3DDR_PATCHFXN]
175 ;DDRPHYC1R = 0x000000C2
178 ;SDTIMR2 = 0x4414C722
180 ;CLK2XSRC = 0x00000000
182 ; This section can be used to configure the PLL1 and the EMIF3a registers
183 ; for starting the DDR2 interface on DSP-boot D800K002 devices.
184 ; |------24|------16|-------8|-------0|
185 ; DDRPHYC1R: | DDRPHYC1R |
188 ; SDTIMR2: | SDTIMR2 |
190 ; CLK2XSRC: | CLK2XSRC |
191 ;[DSP_EMIF3DDR_PATCHFXN]
192 ;DDRPHYC1R = 0x000000C4
195 ;SDTIMR2 = 0x0014C722
197 ;CLK2XSRC = 0x00000000
201 ;LOADADDRESS=0xC1080000
202 ;ENTRYPOINTADDRESS=0xC1080000