1 // SPDX-License-Identifier: GPL-2.0+
5 * Board functions for B&R BRXRE1 Board
7 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
8 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/mem.h>
26 #include <power/tps65217.h>
27 #include "../common/bur_common.h"
30 /* -------------------------------------------------------------------------*/
31 /* -- defines for used GPIO Hardware -- */
32 #define ESC_KEY (0+19)
34 #define PUSH_KEY (0+31)
35 /* -------------------------------------------------------------------------*/
36 /* -- PSOC Resetcontroller Register defines -- */
38 /* I2C Address of controller */
39 #define RSTCTRL_ADDR 0x75
40 /* Register for CTRL-word */
41 #define RSTCTRL_CTRLREG 0x01
42 /* Register for giving some information to VxWorks OS */
43 #define RSTCTRL_SCRATCHREG 0x04
45 /* -- defines for RSTCTRL_CTRLREG -- */
46 #define RSTCTRL_FORCE_PWR_NEN 0x0404
47 #define RSTCTRL_CAN_STB 0x4040
49 DECLARE_GLOBAL_DATA_PTR;
51 #if defined(CONFIG_SPL_BUILD)
52 /* TODO: check ram-timing ! */
53 static const struct ddr_data ddr3_data = {
54 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
55 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
56 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
57 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
59 static const struct cmd_control ddr3_cmd_ctrl_data = {
60 .cmd0csratio = MT41K256M16HA125E_RATIO,
61 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
63 .cmd1csratio = MT41K256M16HA125E_RATIO,
64 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
66 .cmd2csratio = MT41K256M16HA125E_RATIO,
67 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
69 static struct emif_regs ddr3_emif_reg_data = {
70 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
71 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
72 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
73 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
74 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
75 .zq_config = MT41K256M16HA125E_ZQ_CFG,
76 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
79 static const struct ctrl_ioregs ddr3_ioregs = {
80 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
81 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
82 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
83 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
84 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
87 #define OSC (V_OSCK/1000000)
88 const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
90 void am33xx_spl_board_init(void)
92 unsigned int oldspeed;
95 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
96 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
98 * enable additional clocks of modules which are accessed later from
101 u32 *const clk_domains[] = { 0 };
103 u32 *const clk_modules_xre1specific[] = {
104 &cmwkup->wkup_adctscctrl,
106 &cmper->dcan0clkctrl,
107 &cmper->dcan1clkctrl,
108 &cmper->epwmss0clkctrl,
109 &cmper->epwmss1clkctrl,
110 &cmper->epwmss2clkctrl,
112 &cmper->lcdcclkstctrl,
115 do_enable_clocks(clk_domains, clk_modules_xre1specific, 1);
116 /* power-OFF LCD-Display */
117 gpio_direction_output(LCD_PWR, 0);
120 enable_i2c_pin_mux();
122 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
124 /* power-ON 3V3 via Resetcontroller */
125 oldspeed = i2c_get_bus_speed();
126 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
127 buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB;
128 i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
129 (uint8_t *)&buf, sizeof(buf));
130 i2c_set_bus_speed(oldspeed);
132 puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
138 const struct dpll_params *get_dpll_ddr_params(void)
143 void sdram_init(void)
145 config_ddr(400, &ddr3_ioregs,
148 &ddr3_emif_reg_data, 0);
150 #endif /* CONFIG_SPL_BUILD */
152 * Basic board specific setup. Pinmux has been handled already.
160 #ifdef CONFIG_BOARD_LATE_INIT
161 int board_late_init(void)
163 const unsigned int toff = 1000;
164 unsigned int cnt = 3;
165 unsigned short buf = 0xAAAA;
166 unsigned char scratchreg = 0;
167 unsigned int oldspeed;
169 /* try to read out some boot-instruction from resetcontroller */
170 oldspeed = i2c_get_bus_speed();
171 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
172 i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
173 &scratchreg, sizeof(scratchreg));
174 i2c_set_bus_speed(oldspeed);
176 puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
179 if (gpio_get_value(ESC_KEY)) {
181 lcd_position_cursor(1, 8);
185 "release ESC-KEY to enter SERVICE-mode.");
189 "release ESC-KEY to enter DIAGNOSE-mode.");
193 "release ESC-KEY to enter BOOT-mode. ");
198 if (!gpio_get_value(ESC_KEY) &&
199 gpio_get_value(PUSH_KEY) && 2 == cnt) {
200 lcd_position_cursor(1, 8);
202 "switching to network-console ... ");
203 env_set("bootcmd", "run netconsole");
206 } else if (!gpio_get_value(ESC_KEY) &&
207 gpio_get_value(PUSH_KEY) && 1 == cnt) {
208 lcd_position_cursor(1, 8);
210 "starting u-boot script from USB ... ");
211 env_set("bootcmd", "run usbscript");
214 } else if ((!gpio_get_value(ESC_KEY) &&
215 gpio_get_value(PUSH_KEY) && cnt == 0) ||
216 (gpio_get_value(ESC_KEY) &&
217 gpio_get_value(PUSH_KEY) && cnt == 0)) {
218 lcd_position_cursor(1, 8);
220 "starting script from network ... ");
221 env_set("bootcmd", "run netscript");
224 } else if (!gpio_get_value(ESC_KEY)) {
228 } else if (scratchreg == 0xCC) {
229 lcd_position_cursor(1, 8);
231 "starting vxworks from network ... ");
232 env_set("bootcmd", "run netboot");
234 } else if (scratchreg == 0xCD) {
235 lcd_position_cursor(1, 8);
237 "starting script from network ... ");
238 env_set("bootcmd", "run netscript");
240 } else if (scratchreg == 0xCE) {
241 lcd_position_cursor(1, 8);
243 "starting AR from eMMC ... ");
244 env_set("bootcmd", "run mmcboot");
248 lcd_position_cursor(1, 8);
251 lcd_puts("entering BOOT-mode. ");
252 env_set("bootcmd", "run defaultAR");
256 lcd_puts("entering DIAGNOSE-mode. ");
260 lcd_puts("entering SERVICE mode. ");
264 lcd_puts("loading OS... ");
268 /* write bootinfo into scratchregister of resetcontroller */
269 oldspeed = i2c_get_bus_speed();
270 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
271 i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
272 (uint8_t *)&buf, sizeof(buf));
273 i2c_set_bus_speed(oldspeed);
275 puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
277 /* setup othbootargs for bootvx-command (vxWorks bootline) */
278 char othbootargs[128];
279 snprintf(othbootargs, sizeof(othbootargs),
280 "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
281 (unsigned int) gd->fb_base-0x20,
282 (u32)env_get_ulong("vx_memtop", 16, gd->fb_base-0x20),
283 (u32)env_get_ulong("vx_romfsbase", 16, 0),
284 (u32)env_get_ulong("vx_romfssize", 16, 0));
285 env_set("othbootargs", othbootargs);
287 * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
288 * expect that vectors are there, original u-boot moves them to _start
290 __asm__("ldr r0,=0x20000");
291 __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
295 #endif /* CONFIG_BOARD_LATE_INIT */