4 * Board functions for B&R KWB Board
6 * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
7 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/omap.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h>
27 #include <power/tps65217.h>
28 #include "../common/bur_common.h"
31 /* -------------------------------------------------------------------------*/
32 /* -- defines for used GPIO Hardware -- */
33 #define ESC_KEY (0+19)
35 #define PUSH_KEY (0+31)
36 /* -------------------------------------------------------------------------*/
37 /* -- PSOC Resetcontroller Register defines -- */
39 /* I2C Address of controller */
40 #define RSTCTRL_ADDR 0x75
41 /* Register for CTRL-word */
42 #define RSTCTRL_CTRLREG 0x01
43 /* Register for giving some information to VxWorks OS */
44 #define RSTCTRL_SCRATCHREG 0x04
46 /* -- defines for RSTCTRL_CTRLREG -- */
47 #define RSTCTRL_FORCE_PWR_NEN 0x0404
48 #define RSTCTRL_CAN_STB 0x4040
50 #define VXWORKS_BOOTLINE 0x80001100
51 #define DEFAULT_BOOTLINE "cpsw(0,0):pme/vxWorks"
52 #define VXWORKS_USER "u=vxWorksFTP pw=vxWorks tn=vxtarget"
54 DECLARE_GLOBAL_DATA_PTR;
56 #if defined(CONFIG_SPL_BUILD)
57 /* TODO: check ram-timing ! */
58 static const struct ddr_data ddr3_data = {
59 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
60 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
61 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
62 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
64 static const struct cmd_control ddr3_cmd_ctrl_data = {
65 .cmd0csratio = MT41K256M16HA125E_RATIO,
66 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
68 .cmd1csratio = MT41K256M16HA125E_RATIO,
69 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
71 .cmd2csratio = MT41K256M16HA125E_RATIO,
72 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
74 static struct emif_regs ddr3_emif_reg_data = {
75 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
76 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
77 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
78 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
79 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
80 .zq_config = MT41K256M16HA125E_ZQ_CFG,
81 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
84 static const struct ctrl_ioregs ddr3_ioregs = {
85 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
86 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
87 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
88 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
89 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
92 #define OSC (V_OSCK/1000000)
93 const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
95 void am33xx_spl_board_init(void)
97 unsigned int oldspeed;
100 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
101 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
103 * enable additional clocks of modules which are accessed later from
106 u32 *const clk_domains[] = { 0 };
108 u32 *const clk_modules_kwbspecific[] = {
109 &cmwkup->wkup_adctscctrl,
111 &cmper->dcan0clkctrl,
112 &cmper->dcan1clkctrl,
113 &cmper->epwmss0clkctrl,
114 &cmper->epwmss1clkctrl,
115 &cmper->epwmss2clkctrl,
117 &cmper->lcdcclkstctrl,
120 do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
121 /* setup LCD-Pixel Clock */
122 writel(0x2, CM_DPLL + 0x34);
123 /* power-OFF LCD-Display */
124 gpio_direction_output(LCD_PWR, 0);
127 enable_i2c_pin_mux();
129 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
131 /* power-ON 3V3 via Resetcontroller */
132 oldspeed = i2c_get_bus_speed();
133 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
134 buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB;
135 i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
136 (uint8_t *)&buf, sizeof(buf));
137 i2c_set_bus_speed(oldspeed);
139 puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
145 const struct dpll_params *get_dpll_ddr_params(void)
150 void sdram_init(void)
152 config_ddr(400, &ddr3_ioregs,
155 &ddr3_emif_reg_data, 0);
157 #endif /* CONFIG_SPL_BUILD */
159 * Basic board specific setup. Pinmux has been handled already.
167 #ifdef CONFIG_BOARD_LATE_INIT
168 int board_late_init(void)
170 const unsigned int toff = 1000;
171 unsigned int cnt = 3;
172 unsigned short buf = 0xAAAA;
173 unsigned char scratchreg = 0;
174 unsigned int oldspeed;
176 /* try to read out some boot-instruction from resetcontroller */
177 oldspeed = i2c_get_bus_speed();
178 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
179 i2c_read(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
180 &scratchreg, sizeof(scratchreg));
181 i2c_set_bus_speed(oldspeed);
183 puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
186 if (gpio_get_value(ESC_KEY)) {
188 lcd_position_cursor(1, 8);
192 "release ESC-KEY to enter SERVICE-mode.");
196 "release ESC-KEY to enter DIAGNOSE-mode.");
200 "release ESC-KEY to enter BOOT-mode. ");
205 if (!gpio_get_value(ESC_KEY) &&
206 gpio_get_value(PUSH_KEY) && 2 == cnt) {
207 lcd_position_cursor(1, 8);
209 "switching to network-console ... ");
210 setenv("bootcmd", "run netconsole");
213 } else if (!gpio_get_value(ESC_KEY) &&
214 gpio_get_value(PUSH_KEY) && 1 == cnt) {
215 lcd_position_cursor(1, 8);
217 "starting u-boot script from USB ... ");
218 setenv("bootcmd", "run usbscript");
221 } else if ((!gpio_get_value(ESC_KEY) &&
222 gpio_get_value(PUSH_KEY) && cnt == 0) ||
223 (gpio_get_value(ESC_KEY) &&
224 gpio_get_value(PUSH_KEY) && cnt == 0)) {
225 lcd_position_cursor(1, 8);
227 "starting script from network ... ");
228 setenv("bootcmd", "run netscript");
231 } else if (!gpio_get_value(ESC_KEY)) {
235 } else if (scratchreg == 0xCC) {
236 lcd_position_cursor(1, 8);
238 "starting vxworks from network ... ");
239 setenv("bootcmd", "run netboot");
241 } else if (scratchreg == 0xCD) {
242 lcd_position_cursor(1, 8);
244 "starting script from network ... ");
245 setenv("bootcmd", "run netscript");
247 } else if (scratchreg == 0xCE) {
248 lcd_position_cursor(1, 8);
250 "starting AR from eMMC ... ");
251 setenv("bootcmd", "run mmcboot");
255 lcd_position_cursor(1, 8);
258 lcd_puts("entering BOOT-mode. ");
259 setenv("bootcmd", "run defaultAR");
263 lcd_puts("entering DIAGNOSE-mode. ");
267 lcd_puts("entering SERVICE mode. ");
271 lcd_puts("loading OS... ");
275 /* write bootinfo into scratchregister of resetcontroller */
276 oldspeed = i2c_get_bus_speed();
277 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
278 i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
279 (uint8_t *)&buf, sizeof(buf));
280 i2c_set_bus_speed(oldspeed);
282 puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
284 /* setup vxworks bootline */
285 char *vxworksbootline = (char *)VXWORKS_BOOTLINE;
287 /* setup default IP, in case if there is nothing in environment */
288 if (!getenv("ipaddr")) {
289 setenv("ipaddr", "192.168.60.1");
290 setenv("netmask", "255.255.255.0");
291 setenv("serverip", "192.168.60.254");
292 setenv("gatewayip", "192.168.60.254");
293 puts("net: had no IP! made default setup.\n");
296 sprintf(vxworksbootline,
297 "%s h=%s e=%s:%s g=%s %s o=0x%08x;0x%08x;0x%08x;0x%08x",
300 getenv("ipaddr"), getenv("netmask"),
303 (unsigned int) gd->fb_base-0x20,
304 (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20),
305 (u32)getenv_ulong("vx_romfsbase", 16, 0),
306 (u32)getenv_ulong("vx_romfssize", 16, 0));
309 * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
310 * expect that vectors are there, original u-boot moves them to _start
312 __asm__("ldr r0,=0x20000");
313 __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
317 #endif /* CONFIG_BOARD_LATE_INIT */