git.sur5r.net Git - u-boot/blob - board/BuR/kwb/board.c

   1 /*
   2  * board.c
   3  *
   4  * Board functions for B&R KWB Board
   5  *
   6  * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
   7  * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  *
  11  */
  12 #include <common.h>
  13 #include <errno.h>
  14 #include <spl.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/hardware.h>
  17 #include <asm/arch/omap.h>
  18 #include <asm/arch/ddr_defs.h>
  19 #include <asm/arch/clock.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/arch/sys_proto.h>
  22 #include <asm/arch/mem.h>
  23 #include <asm/io.h>
  24 #include <asm/emif.h>
  25 #include <asm/gpio.h>
  26 #include <i2c.h>
  27 #include <power/tps65217.h>
  28 #include "../common/bur_common.h"
  29 #include <lcd.h>
  30
  31 /* -------------------------------------------------------------------------*/
  32 /* -- defines for used GPIO Hardware -- */
  33 #define ESC_KEY                                 (0+19)
  34 #define LCD_PWR                                 (0+5)
  35 #define PUSH_KEY                                (0+31)
  36 /* -------------------------------------------------------------------------*/
  37 /* -- PSOC Resetcontroller Register defines -- */
  38
  39 /* I2C Address of controller */
  40 #define RSTCTRL_ADDR                            0x75
  41 /* Register for CTRL-word */
  42 #define RSTCTRL_CTRLREG                         0x01
  43 /* Register for giving some information to VxWorks OS */
  44 #define RSTCTRL_SCRATCHREG                      0x04
  45
  46 /* -- defines for RSTCTRL_CTRLREG  -- */
  47 #define RSTCTRL_FORCE_PWR_NEN                   0x0404
  48 #define RSTCTRL_CAN_STB                         0x4040
  49
  50 #define VXWORKS_BOOTLINE                        0x80001100
  51 #define DEFAULT_BOOTLINE        "cpsw(0,0):pme/vxWorks"
  52 #define VXWORKS_USER            "u=vxWorksFTP pw=vxWorks tn=vxtarget"
  53
  54 DECLARE_GLOBAL_DATA_PTR;
  55
  56 #if defined(CONFIG_SPL_BUILD)
  57 /* TODO: check ram-timing ! */
  58 static const struct ddr_data ddr3_data = {
  59         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  60         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  61         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  62         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  63 };
  64 static const struct cmd_control ddr3_cmd_ctrl_data = {
  65         .cmd0csratio = MT41K256M16HA125E_RATIO,
  66         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  67
  68         .cmd1csratio = MT41K256M16HA125E_RATIO,
  69         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  70
  71         .cmd2csratio = MT41K256M16HA125E_RATIO,
  72         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  73 };
  74 static struct emif_regs ddr3_emif_reg_data = {
  75         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  76         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  77         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  78         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  79         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  80         .zq_config = MT41K256M16HA125E_ZQ_CFG,
  81         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  82 };
  83
  84 static const struct ctrl_ioregs ddr3_ioregs = {
  85         .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  86         .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  87         .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  88         .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  89         .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  90 };
  91
  92 #define OSC     (V_OSCK/1000000)
  93 const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
  94
  95 void am33xx_spl_board_init(void)
  96 {
  97         unsigned int oldspeed;
  98         unsigned short buf;
  99
 100         struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
 101         struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
 102         /*
 103          * enable additional clocks of modules which are accessed later from
 104          * VxWorks OS
 105          */
 106         u32 *const clk_domains[] = { 0 };
 107
 108         u32 *const clk_modules_kwbspecific[] = {
 109                 &cmwkup->wkup_adctscctrl,
 110                 &cmper->spi1clkctrl,
 111                 &cmper->dcan0clkctrl,
 112                 &cmper->dcan1clkctrl,
 113                 &cmper->epwmss0clkctrl,
 114                 &cmper->epwmss1clkctrl,
 115                 &cmper->epwmss2clkctrl,
 116                 &cmper->lcdclkctrl,
 117                 &cmper->lcdcclkstctrl,
 118                 0
 119         };
 120         do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
 121         /* setup LCD-Pixel Clock */
 122         writel(0x2, CM_DPLL + 0x34);
 123         /* power-OFF LCD-Display */
 124         gpio_direction_output(LCD_PWR, 0);
 125
 126         /* setup I2C */
 127         enable_i2c0_pin_mux();
 128         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 129
 130         /* power-ON  3V3 via Resetcontroller */
 131         oldspeed = i2c_get_bus_speed();
 132         if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
 133                 buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB;
 134                 i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
 135                           (uint8_t *)&buf, sizeof(buf));
 136                 i2c_set_bus_speed(oldspeed);
 137         } else {
 138                 puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
 139         }
 140
 141         pmicsetup(0);
 142 }
 143
 144 const struct dpll_params *get_dpll_ddr_params(void)
 145 {
 146         return &dpll_ddr3;
 147 }
 148
 149 void sdram_init(void)
 150 {
 151         config_ddr(400, &ddr3_ioregs,
 152                    &ddr3_data,
 153                    &ddr3_cmd_ctrl_data,
 154                    &ddr3_emif_reg_data, 0);
 155 }
 156 #endif /* CONFIG_SPL_BUILD */
 157 /*
 158  * Basic board specific setup.  Pinmux has been handled already.
 159  */
 160 int board_init(void)
 161 {
 162         gpmc_init();
 163         return 0;
 164 }
 165
 166 #ifdef CONFIG_BOARD_LATE_INIT
 167 int board_late_init(void)
 168 {
 169         const unsigned int toff = 1000;
 170         unsigned int cnt  = 3;
 171         unsigned short buf = 0xAAAA;
 172         unsigned int oldspeed;
 173
 174         tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 175                            TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */
 176
 177         if (gpio_get_value(ESC_KEY)) {
 178                 do {
 179                         lcd_position_cursor(1, 8);
 180                         switch (cnt) {
 181                         case 3:
 182                                 lcd_puts(
 183                                 "release ESC-KEY to enter SERVICE-mode.");
 184                                 break;
 185                         case 2:
 186                                 lcd_puts(
 187                                 "release ESC-KEY to enter DIAGNOSE-mode.");
 188                                 break;
 189                         case 1:
 190                                 lcd_puts(
 191                                 "release ESC-KEY to enter BOOT-mode.    ");
 192                                 break;
 193                         }
 194                         mdelay(toff);
 195                         cnt--;
 196                         if (!gpio_get_value(ESC_KEY) &&
 197                             gpio_get_value(PUSH_KEY) && 2 == cnt) {
 198                                 lcd_position_cursor(1, 8);
 199                                 lcd_puts(
 200                                 "switching to network-console ...       ");
 201                                 setenv("bootcmd", "run netconsole");
 202                                 cnt = 4;
 203                                 break;
 204                         } else if (!gpio_get_value(ESC_KEY) &&
 205                             gpio_get_value(PUSH_KEY) && 1 == cnt) {
 206                                 lcd_position_cursor(1, 8);
 207                                 lcd_puts(
 208                                 "updating U-BOOT from USB ...           ");
 209                                 setenv("bootcmd", "run usbupdate");
 210                                 cnt = 4;
 211                                 break;
 212                         } else if ((!gpio_get_value(ESC_KEY) &&
 213                                     gpio_get_value(PUSH_KEY) && cnt == 0) ||
 214                                     (gpio_get_value(ESC_KEY) &&
 215                                     gpio_get_value(PUSH_KEY) && cnt == 0)) {
 216                                 lcd_position_cursor(1, 8);
 217                                 lcd_puts(
 218                                 "starting script from network ...      ");
 219                                 setenv("bootcmd", "run netscript");
 220                                 cnt = 4;
 221                                 break;
 222                         } else if (!gpio_get_value(ESC_KEY)) {
 223                                 break;
 224                         }
 225                 } while (cnt);
 226         }
 227
 228         lcd_position_cursor(1, 8);
 229         switch (cnt) {
 230         case 0:
 231                 lcd_puts("entering BOOT-mode.                    ");
 232                 setenv("bootcmd", "run defaultAR");
 233                 buf = 0x0000;
 234                 break;
 235         case 1:
 236                 lcd_puts("entering DIAGNOSE-mode.                ");
 237                 buf = 0x0F0F;
 238                 break;
 239         case 2:
 240                 lcd_puts("entering SERVICE mode.                 ");
 241                 buf = 0xB4B4;
 242                 break;
 243         case 3:
 244                 lcd_puts("loading OS...                          ");
 245                 buf = 0x0404;
 246                 break;
 247         }
 248         /* write bootinfo into scratchregister of resetcontroller */
 249         oldspeed = i2c_get_bus_speed();
 250         if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
 251                 i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
 252                           (uint8_t *)&buf, sizeof(buf));
 253                 i2c_set_bus_speed(oldspeed);
 254         } else {
 255                 puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
 256         }
 257         /* setup vxworks bootline */
 258         char *vxworksbootline = (char *)VXWORKS_BOOTLINE;
 259
 260         /* setup default IP, in case if there is nothing in environment */
 261         if (!getenv("ipaddr")) {
 262                 setenv("ipaddr", "192.168.60.1");
 263                 setenv("netmask", "255.255.255.0");
 264                 setenv("serverip", "192.168.60.254");
 265                 setenv("gatewayip", "192.168.60.254");
 266                 puts("net: had no IP! made default setup.\n");
 267         }
 268
 269         sprintf(vxworksbootline,
 270                 "%s h=%s e=%s:%s g=%s %s o=0x%08x;0x%08x;0x%08x;0x%08x",
 271                 DEFAULT_BOOTLINE,
 272                 getenv("serverip"),
 273                 getenv("ipaddr"), getenv("netmask"),
 274                 getenv("gatewayip"),
 275                 VXWORKS_USER,
 276                 (unsigned int) gd->fb_base-0x20,
 277                 (u32)getenv_ulong("vx_memtop", 16, gd->fb_base-0x20),
 278                 (u32)getenv_ulong("vx_romfsbase", 16, 0),
 279                 (u32)getenv_ulong("vx_romfssize", 16, 0));
 280
 281         /*
 282          * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
 283          * expect that vectors are there, original u-boot moves them to _start
 284          */
 285         __asm__("ldr r0,=0x20000");
 286         __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
 287
 288         return 0;
 289 }
 290 #endif /* CONFIG_BOARD_LATE_INIT */