4 * Board functions for B&R KWB Board
6 * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
7 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/omap.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h>
27 #include <power/tps65217.h>
28 #include "../common/bur_common.h"
30 /* -------------------------------------------------------------------------*/
31 /* -- defines for used GPIO Hardware -- */
34 #define PUSH_KEY (0+31)
35 #define USB2SD_NRST (32+29)
36 #define USB2SD_PWR (96+13)
37 /* -------------------------------------------------------------------------*/
38 /* -- PSOC Resetcontroller Register defines -- */
40 /* I2C Address of controller */
41 #define RSTCTRL_ADDR 0x75
42 /* Register for CTRL-word */
43 #define RSTCTRL_CTRLREG 0x01
44 /* Register for giving some information to VxWorks OS */
45 #define RSTCTRL_SCRATCHREG 0x04
47 /* -- defines for RSTCTRL_CTRLREG -- */
48 #define RSTCTRL_FORCE_PWR_NEN 0x0404
50 #if defined(CONFIG_SPL_BUILD)
51 /* TODO: check ram-timing ! */
52 static const struct ddr_data ddr3_data = {
53 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
54 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
55 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
56 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
58 static const struct cmd_control ddr3_cmd_ctrl_data = {
59 .cmd0csratio = MT41K256M16HA125E_RATIO,
60 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
62 .cmd1csratio = MT41K256M16HA125E_RATIO,
63 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
65 .cmd2csratio = MT41K256M16HA125E_RATIO,
66 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
68 static struct emif_regs ddr3_emif_reg_data = {
69 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
70 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
71 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
72 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
73 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
74 .zq_config = MT41K256M16HA125E_ZQ_CFG,
75 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
78 static const struct ctrl_ioregs ddr3_ioregs = {
79 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
80 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
81 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
82 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
83 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
86 #define OSC (V_OSCK/1000000)
87 const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
89 void am33xx_spl_board_init(void)
91 unsigned int oldspeed;
94 struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
95 struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;
97 * enable additional clocks of modules which are accessed later from
100 u32 *const clk_domains[] = { 0 };
102 u32 *const clk_modules_kwbspecific[] = {
103 &cmwkup->wkup_adctscctrl,
105 &cmper->dcan0clkctrl,
106 &cmper->dcan1clkctrl,
107 &cmper->epwmss0clkctrl,
108 &cmper->epwmss1clkctrl,
109 &cmper->epwmss2clkctrl,
112 do_enable_clocks(clk_domains, clk_modules_kwbspecific, 1);
114 /* power-OFF LCD-Display */
115 gpio_direction_output(LCD_PWR, 0);
118 enable_i2c0_pin_mux();
119 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
121 /* power-ON 3V3 via Resetcontroller */
122 oldspeed = i2c_get_bus_speed();
123 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
124 buf = RSTCTRL_FORCE_PWR_NEN;
125 i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1,
126 (uint8_t *)&buf, sizeof(buf));
127 i2c_set_bus_speed(oldspeed);
129 puts("ERROR: i2c_set_bus_speed failed! (turn on PWR_nEN)\n");
132 #if defined(CONFIG_AM335X_USB0)
133 /* power on USB2SD Controller */
134 gpio_direction_output(USB2SD_PWR, 1);
136 /* give a reset Pulse to USB2SD Controller */
137 gpio_direction_output(USB2SD_NRST, 0);
139 gpio_set_value(USB2SD_NRST, 1);
144 const struct dpll_params *get_dpll_ddr_params(void)
149 void sdram_init(void)
151 config_ddr(400, &ddr3_ioregs,
154 &ddr3_emif_reg_data, 0);
156 #endif /* CONFIG_SPL_BUILD */
158 * Basic board specific setup. Pinmux has been handled already.
166 #ifdef CONFIG_BOARD_LATE_INIT
167 int board_late_init(void)
169 const unsigned int ton = 250;
170 const unsigned int toff = 1000;
171 unsigned int cnt = 3;
172 unsigned short buf = 0xAAAA;
173 unsigned int oldspeed;
175 tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
176 TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */
178 if (gpio_get_value(KEY)) {
181 tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
182 TPS65217_WLEDCTRL1, 0x09, 0xFF);
185 tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
186 TPS65217_WLEDCTRL1, 0x01, 0xFF);
189 if (!gpio_get_value(KEY) &&
190 gpio_get_value(PUSH_KEY) && 1 == cnt) {
191 puts("updating from USB ...\n");
192 setenv("bootcmd", "run usbupdate");
194 } else if (!gpio_get_value(KEY)) {
202 puts("3 blinks ... entering BOOT mode.\n");
206 puts("2 blinks ... entering DIAGNOSE mode.\n");
210 puts("1 blinks ... entering SERVICE mode.\n");
214 puts("0 blinks ... entering RUN mode.\n");
220 tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
221 TPS65217_WLEDCTRL1, 0x09, 0xFF);
222 /* write bootinfo into scratchregister of resetcontroller */
223 oldspeed = i2c_get_bus_speed();
224 if (i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC) >= 0) {
225 i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1,
226 (uint8_t *)&buf, sizeof(buf));
227 i2c_set_bus_speed(oldspeed);
229 puts("ERROR: i2c_set_bus_speed failed! (scratchregister)\n");
232 * reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
233 * expect that vectors are there, original u-boot moves them to _start
235 __asm__("ldr r0,=0x20000");
236 __asm__("mcr p15, 0, r0, c12, c0, 0"); /* Set VBAR */
240 #endif /* CONFIG_BOARD_LATE_INIT */