2 * (C) Copyright 2009-2012
3 * Jens Scharsig <esw@bus-elekronik.de>
4 * BuS Elektronik GmbH & Co. KG
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/sizes.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/at91_matrix.h>
16 #include <asm/arch/at91sam9_smc.h>
17 #include <asm/arch/at91_pmc.h>
18 #include <asm/arch/at91_pio.h>
19 #include <asm/arch/at91_rstc.h>
20 #include <asm/arch/at91sam9263.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/at91_common.h>
25 #include <atmel_lcdc.h>
26 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
31 DECLARE_GLOBAL_DATA_PTR;
33 #ifdef CONFIG_CMD_NAND
34 static void vl_ma2sc_nand_hw_init(void)
37 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
38 at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
39 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
41 at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
42 at91_set_pio_output(AT91_PIO_PORTA, 12, 1); /* CAN_STB -> H */
43 at91_set_pio_output(AT91_PIO_PORTA, 11, 1); /* CAN_EN -> H */
46 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
47 writel(csa, &matrix->csa[0]);
49 /* Configure SMC CS3 for NAND/SmartMedia */
50 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
51 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
54 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
55 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
58 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
60 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
62 AT91_SMC_MODE_TDF_CYCLE(2),
64 writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE),
67 /* Configure RDY/BSY */
68 #ifdef CONFIG_SYS_NAND_READY_PIN
69 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
71 /* Enable NandFlash */
72 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
77 static void vl_ma2sc_macb_hw_init(void)
80 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
81 at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
83 writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
85 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
87 /* Need to reset PHY -> 500ms reset */
88 writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
89 AT91_RSTC_MR_URSTEN, &rstc->mr);
91 writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
92 /* Wait for end hardware reset */
93 while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
96 /* Restore NRST value */
97 writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
104 vidinfo_t panel_info = {
108 .vl_sync = ATMEL_LCDC_INVDVAL_INVERTED |
109 ATMEL_LCDC_INVLINE_INVERTED |
110 ATMEL_LCDC_INVVD_INVERTED |
111 ATMEL_LCDC_INVFRAME_INVERTED,
112 .vl_bpix = (ATMEL_LCDC_PIXELSIZE_8 >> 5),
114 .vl_hsync_len = 5, /* Horiz Sync Pulse Width */
115 .vl_left_margin = 68, /* horiz back porch */
116 .vl_right_margin = 20, /* horiz front porch */
117 .vl_vsync_len = 2, /* vert Sync Pulse Width */
118 .vl_upper_margin = 18, /* vert back porch */
119 .vl_lower_margin = 4, /* vert front porch */
120 .mmio = ATMEL_BASE_LCDC,
123 void lcd_enable(void)
127 void lcd_disable(void)
131 static void vl_ma2sc_lcd_hw_init(void)
133 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
135 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
136 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
137 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
138 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
139 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
141 at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD0 */
142 at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD1 */
143 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
144 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
145 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
146 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
147 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
148 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
150 at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD9 */
151 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
152 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
153 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
154 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
155 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
156 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
158 at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD26 */
159 at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD17 */
160 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
161 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
162 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
163 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
164 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
165 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
167 at91_set_pio_output(AT91_PIO_PORTE, 0, 0); /* LCD QXH */
169 at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* LCD SHUT */
170 at91_set_pio_output(AT91_PIO_PORTE, 3, 1); /* LCD TopBottom */
171 at91_set_pio_output(AT91_PIO_PORTE, 4, 0); /* LCD REV */
172 at91_set_pio_output(AT91_PIO_PORTE, 5, 1); /* LCD RightLeft */
173 at91_set_pio_output(AT91_PIO_PORTE, 6, 0); /* LCD Color Mode CM */
174 at91_set_pio_output(AT91_PIO_PORTE, 7, 0); /* LCD BGR */
176 at91_set_pio_output(AT91_PIO_PORTB, 9, 0); /* LCD CC */
178 writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
179 gd->fb_base = ATMEL_BASE_SRAM0;
181 #endif /* Config LCD */
183 #ifdef CONFIG_BOARD_EARLY_INIT_F
184 int board_early_init_f(void)
186 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
188 /* Enable clocks for all PIOs */
189 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
190 (1 << ATMEL_ID_PIOCDE),
193 at91_seriald_hw_init();
201 at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
202 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
206 writel(pin, &pio->pioa.idr);
207 writel(pin, &pio->pioa.pudr);
208 writel(pin, &pio->pioa.per);
209 writel(pin, &pio->pioa.oer);
210 writel(pin, &pio->pioa.sodr);
211 writel((1 << 25), &pio->pioa.codr);
214 writel(pin, &pio->piob.idr);
215 writel(pin, &pio->piob.pudr);
216 writel(pin, &pio->piob.per);
217 writel(pin, &pio->piob.oer);
218 writel(pin, &pio->piob.codr);
219 writel((1 << 24), &pio->piob.sodr);
221 pin = 0x40000000; /* Pullup DRxD enbable */
222 writel(pin, &pio->pioc.puer);
224 pin = 0x0000000F; /* HWversion als Input */
225 writel(pin, &pio->piod.idr);
226 writel(pin, &pio->piod.puer);
227 writel(pin, &pio->piod.per);
228 writel(pin, &pio->piod.odr);
229 writel(pin, &pio->piod.owdr);
231 gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC;
232 /* adress of boot parameters */
233 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
235 writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup);
236 writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle);
237 writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse);
238 writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup);
240 #ifdef CONFIG_CMD_NAND
241 vl_ma2sc_nand_hw_init();
244 vl_ma2sc_macb_hw_init();
246 #ifdef CONFIG_USB_OHCI_NEW
250 vl_ma2sc_lcd_hw_init();
255 #ifdef CONFIG_MISC_INIT_R
256 int misc_init_r(void)
259 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
264 if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0)
265 puts("error reseting rtc clock\n\0");
267 /* read hardware version */
269 pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44;
270 printf("Board: revision %c\n", pin);
273 setenv("revision", (char *) buffer);
275 pin = 0x40000000; /* Pullup DRxD enbable */
276 writel(pin, &pio->pioc.puer);
283 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
284 CONFIG_SYS_SDRAM_SIZE);
288 #ifdef CONFIG_RESET_PHY_R
293 * Initialize ethernet HW addr prior to starting Linux,
301 int board_eth_init(bd_t *bis)
305 rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01);
310 #ifdef CONFIG_SYS_I2C_SOFT
311 void i2c_init_board(void)
315 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
316 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
320 writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
322 writel(pin, &pio->piob.idr); /* Disable Interupt */
323 writel(pin, &pio->piob.pudr);
324 writel(pin, &pio->piob.per);
325 writel(pin, &pio->piob.oer);
326 writel(pin, &pio->piob.sodr);
330 void watchdog_reset(void)
332 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
333 u32 pin = 0x1; /* PA0 */
335 if ((readl(&pio->pioa.odsr) & pin) > 0)
336 writel(pin, &pio->pioa.codr);
338 writel(pin, &pio->pioa.sodr);
341 void enable_caches(void)
343 #ifndef CONFIG_SYS_DCACHE_OFF
348 /*---------------------------------------------------------------------------*/
350 int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
357 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
359 at91_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LCD DIM */
362 writel(pins, &pio->pioa.idr);
363 writel(pins, &pio->pioa.pudr);
364 writel(pins, &pio->pioa.per);
365 writel(pins, &pio->pioa.oer);
366 writel(pins, &pio->pioa.sodr);
369 writel(pinz, &pio->piob.idr);
370 writel(pinz, &pio->piob.pudr);
371 writel(pinz, &pio->piob.per);
372 writel(pinz, &pio->piob.oer);
373 writel(pinz, &pio->piob.sodr);
375 for (row = 0; row < 5; row++) {
376 for (col = 0; col < 5; col++) {
377 writel((0x01000000 << col), &pio->piob.sodr);
378 writel((0x01000000 << row), &pio->pioa.codr);
379 printf("LED Test %d x %d\n", row, col);
381 writel(pinz, &pio->piob.codr);
382 writel(pins, &pio->pioa.sodr);
391 at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
393 at91_set_pio_output(AT91_PIO_PORTA, 12, 0); /* CAN_STB -> L */
395 at91_set_pio_output(AT91_PIO_PORTA, 11, 0); /* CAN_EN -> L */
401 int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
408 int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
419 durate = simple_strtoul(argv[2], NULL, 10);
421 freq = simple_strtoul(argv[1], NULL, 10);
429 durate = durate * freq;
430 freq = 500000 / freq;
431 for (i = 0; i < durate; i++) {
432 at91_set_pio_output(AT91_PIO_PORTB, 29, 1); /* Sound On*/
434 at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
437 at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
441 int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
448 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
449 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
451 writel((1 << ATMEL_ID_PIOA), &pmc->pcer);
454 writel(pins, &pio->pioa.idr);
455 writel(pins, &pio->pioa.pudr);
456 writel(pins, &pio->pioa.per);
457 writel(pins, &pio->pioa.odr);
460 writel(pinz, &pio->piob.idr);
461 writel(pinz, &pio->piob.pudr);
462 writel(pinz, &pio->piob.per);
463 writel(pinz, &pio->piob.oer);
464 writel(pinz, &pio->piob.codr);
468 for (row = 0; row < 4; row++) {
469 writel((0x00010000 << row), &pio->piob.sodr);
472 col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ;
473 writel(pinz, &pio->piob.codr);
476 for (row = 0; row < 16; row++) {
477 printf("%1.1d", col & 1);
481 1 ^ (1 & (readl(&pio->piob.pdsr) >> 20)));
482 if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) {
486 if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0)
493 if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) {
506 /*****************************************************************************/
509 ledtest, 1, 0, do_ledtest,
515 keytest, 1, 0, do_keytest,
516 "test keymatix and special keys, poweroff on pressing ON key",
521 poweroff, 1, 0, do_poweroff,
529 "freq frequence of beep\nduration duration of beep\n"
532 /*****************************************************************************/