2 # Copyright (C) 2011 Simon Guinot <sguinot@lacie.com>
4 # Based on Kirkwood support:
6 # Marvell Semiconductor <www.marvell.com>
7 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 # See file CREDITS for list of people who contributed to this
12 # This program is free software; you can redistribute it and/or
13 # modify it under the terms of the GNU General Public License as
14 # published by the Free Software Foundation; either version 2 of
15 # the License, or (at your option) any later version.
17 # This program is distributed in the hope that it will be useful,
18 # but WITHOUT ANY WARRANTY; without even the implied warranty of
19 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 # GNU General Public License for more details.
22 # Refer doc/README.kwbimage for more details about how-to configure
23 # and create kirkwood boot image
26 # Boot Media configurations
27 BOOT_FROM spi # Boot from SPI flash
29 # SOC registers configuration using bootrom header extension
30 # Maximum KWBIMAGE_MAX_CONFIG configurations allowed
32 # Configure RGMII-0 interface pad voltage to 1.8V
33 DATA 0xFFD100e0 0x1B1B1B9B
35 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
36 DATA 0xFFD01400 0x43000618 # DDR Configuration register
37 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
39 # bit24: 1= enable exit self refresh mode on DDR access
44 DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
45 # bit 4: 0=addr/cmd in smame cycle
46 # bit 5: 0=clk is driven during self refresh, we don't care for APX
47 # bit 6: 0=use recommended falling edge of clk for addr/cmd
48 # bit14: 0=input buffer always powered up
49 # bit18: 1=cpu lock transaction enabled
50 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
51 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
52 # bit30-28: 3 required
53 # bit31: 0=no additional STARTBURST delay
55 DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
65 DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
70 # bit31-13: zero required
72 DATA 0xFFD01410 0x0000000C # DDR Address Control
73 # bit1-0: 00, Cs0width=x8
74 # bit3-2: 11, Cs0size=1Gb
75 # bit5-4: 00, Cs2width=nonexistent
76 # bit7-6: 00, Cs1size =nonexistent
77 # bit9-8: 00, Cs2width=nonexistent
78 # bit11-10: 00, Cs2size =nonexistent
79 # bit13-12: 00, Cs3width=nonexistent
80 # bit15-14: 00, Cs3size =nonexistent
81 # bit16: 0, Cs0AddrSel
82 # bit17: 0, Cs1AddrSel
83 # bit18: 0, Cs2AddrSel
84 # bit19: 0, Cs3AddrSel
85 # bit31-20: 0 required
87 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
88 # bit0: 0, OpenPage enabled
91 DATA 0xFFD01418 0x00000000 # DDR Operation
92 # bit3-0: 0x0, DDR cmd
95 DATA 0xFFD0141C 0x00000632 # DDR Mode
96 # bit2-0: 2, BurstLen=2 required
97 # bit3: 0, BurstType=0 required
99 # bit7: 0, TestMode=0 normal
100 # bit8: 0, DLL reset=0 normal
101 # bit11-9: 6, auto-precharge write recovery ????????????
102 # bit12: 0, PD must be zero
103 # bit31-13: 0 required
105 DATA 0xFFD01420 0x00000004 # DDR Extended Mode
106 # bit0: 0, DDR DLL enabled
107 # bit1: 1, DDR drive strenght reduced
108 # bit2: 1, DDR ODT control lsd enabled
109 # bit5-3: 000, required
110 # bit6: 1, DDR ODT control msb, enabled
111 # bit9-7: 000, required
112 # bit10: 0, differential DQS enabled
114 # bit12: 0, DDR output buffer enabled
115 # bit31-13: 0 required
117 DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
118 # bit2-0: 111, required
119 # bit3 : 1 , MBUS Burst Chop disabled
120 # bit6-4: 111, required
121 # bit7 : 1 , D2P Latency enabled
122 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
123 # bit9 : 0 , no half clock cycle addition to dataout
124 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
125 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
126 # bit15-12: 1111 required
127 # bit31-16: 0 required
129 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
130 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
132 DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
133 DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
134 # bit0: 1, Window enabled
135 # bit1: 0, Write Protect disabled
136 # bit3-2: 00, CS0 hit selected
137 # bit23-4: ones, required
138 # bit31-24: 0x07, Size (i.e. 128MB)
140 DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
141 DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
142 DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
144 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
145 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
146 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
148 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
149 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
150 # bit3-2: 01, ODT1 active NEVER!
151 # bit31-4: zero, required
153 DATA 0xFFD0149C 0x0000E40F # CPU ODT Control
154 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
155 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
156 # bit11-10:1, DQ_ODTSel. ODT select turned on
158 DATA 0xFFD01480 0x00000001 # DDR Initialization Control
159 #bit0=1, enable DDR init upon this register write
161 # End of Header extension