3 * Adam Kowalczyk, ACK Software Controls Inc. akowalczyk@cogeco.ca
5 * Some portions taken from 3c59x.c Written 1996-1999 by Donald Becker.
7 * Outline of the program based on eepro100.c which is
10 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
38 /* 3Com Ethernet PCI definitions*/
40 /* #define PCI_VENDOR_ID_3COM 0x10B7 */
41 #define PCI_DEVICE_ID_3COM_3C905C 0x9200
43 /* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */
45 #define TotalReset (0<<11)
46 #define SelectWindow (1<<11)
47 #define StartCoax (2<<11)
48 #define RxDisable (3<<11)
49 #define RxEnable (4<<11)
50 #define RxReset (5<<11)
51 #define UpStall (6<<11)
52 #define UpUnstall (6<<11)+1
53 #define DownStall (6<<11)+2
54 #define DownUnstall (6<<11)+3
55 #define RxDiscard (8<<11)
56 #define TxEnable (9<<11)
57 #define TxDisable (10<<11)
58 #define TxReset (11<<11)
59 #define FakeIntr (12<<11)
60 #define AckIntr (13<<11)
61 #define SetIntrEnb (14<<11)
62 #define SetStatusEnb (15<<11)
63 #define SetRxFilter (16<<11)
64 #define SetRxThreshold (17<<11)
65 #define SetTxThreshold (18<<11)
66 #define SetTxStart (19<<11)
67 #define StartDMAUp (20<<11)
68 #define StartDMADown (20<<11)+1
69 #define StatsEnable (21<<11)
70 #define StatsDisable (22<<11)
71 #define StopCoax (23<<11)
72 #define SetFilterBit (25<<11)
74 /* The SetRxFilter command accepts the following classes */
81 /* 3Com status word defnitions */
83 #define IntLatch 0x0001
84 #define HostError 0x0002
85 #define TxComplete 0x0004
86 #define TxAvailable 0x0008
87 #define RxComplete 0x0010
88 #define RxEarly 0x0020
90 #define StatsFull 0x0080
91 #define DMADone (1<<8)
92 #define DownComplete (1<<9)
93 #define UpComplete (1<<10)
94 #define DMAInProgress (1<<11) /* DMA controller is still busy.*/
95 #define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/
97 /* Polling Registers */
102 /* Register window 0 offets */
104 #define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */
105 #define Wn0EepromData 12 /* Window 0: EEPROM results register. */
106 #define IntrStatus 0x0E /* Valid in all windows. */
108 /* Register window 0 EEPROM bits */
110 #define EEPROM_Read 0x80
111 #define EEPROM_WRITE 0x40
112 #define EEPROM_ERASE 0xC0
113 #define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */
114 #define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */
116 /* EEPROM locations. */
122 #define EtherLink3ID 7
125 #define NodeAddr01 10
126 #define NodeAddr23 11
127 #define NodeAddr45 12
128 #define DriverTune 13
131 /* Register window 1 offsets, the window used in normal operation */
134 #define RX_FIFOa 0x10
135 #define RxErrors 0x14
136 #define RxStatus 0x18
138 #define TxStatus 0x1B
139 #define TxFree 0x1C /* Remaining free bytes in Tx buffer. */
141 /* Register Window 2 */
143 #define Wn2_ResetOptions 12
145 /* Register Window 3: MAC/config bits */
147 #define Wn3_Config 0 /* Internal Configuration */
148 #define Wn3_MAC_Ctrl 6
149 #define Wn3_Options 8
151 #define BFEXT(value, offset, bitcount) \
152 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
154 #define BFINS(lhs, rhs, offset, bitcount) \
155 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
156 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
158 #define RAM_SIZE(v) BFEXT(v, 0, 3)
159 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
160 #define RAM_SPEED(v) BFEXT(v, 4, 2)
161 #define ROM_SIZE(v) BFEXT(v, 6, 2)
162 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
163 #define XCVR(v) BFEXT(v, 20, 4)
164 #define AUTOSELECT(v) BFEXT(v, 24, 1)
166 /* Register Window 4: Xcvr/media bits */
168 #define Wn4_FIFODiag 4
169 #define Wn4_NetDiag 6
170 #define Wn4_PhysicalMgmt 8
173 #define Media_SQE 0x0008 /* Enable SQE error counting for AUI. */
174 #define Media_10TP 0x00C0 /* Enable link beat and jabber for 10baseT. */
175 #define Media_Lnk 0x0080 /* Enable just link beat for 100TX/100FX. */
176 #define Media_LnkBeat 0x0800
178 /* Register Window 7: Bus Master control */
180 #define Wn7_MasterAddr 0
181 #define Wn7_MasterLen 6
182 #define Wn7_MasterStatus 12
184 /* Boomerang bus master control registers. */
186 #define PktStatus 0x20
187 #define DownListPtr 0x24
188 #define FragAddr 0x28
190 #define TxFreeThreshold 0x2f
191 #define UpPktStatus 0x30
192 #define UpListPtr 0x38
194 /* The Rx and Tx descriptor lists. */
196 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
197 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
199 struct rx_desc_3com {
200 u32 next; /* Last entry points to 0 */
201 u32 status; /* FSH -> Frame Start Header */
202 u32 addr; /* Up to 63 addr/len pairs possible */
203 u32 length; /* Set LAST_FRAG to indicate last pair */
206 /* Values for the Rx status entry. */
208 #define RxDComplete 0x00008000
209 #define RxDError 0x4000
210 #define IPChksumErr (1<<25)
211 #define TCPChksumErr (1<<26)
212 #define UDPChksumErr (1<<27)
213 #define IPChksumValid (1<<29)
214 #define TCPChksumValid (1<<30)
215 #define UDPChksumValid (1<<31)
217 struct tx_desc_3com {
218 u32 next; /* Last entry points to 0 */
219 u32 status; /* bits 0:12 length, others see below */
224 /* Values for the Tx status entry. */
226 #define CRCDisable 0x2000
227 #define TxDComplete 0x8000
228 #define AddIPChksum 0x02000000
229 #define AddTCPChksum 0x04000000
230 #define AddUDPChksum 0x08000000
231 #define TxIntrUploaded 0x80000000 /* IRQ when in FIFO, but maybe not sent. */
235 #define XCVR_10baseT 0
237 #define XCVR_10baseTOnly 2
238 #define XCVR_10base2 3
239 #define XCVR_100baseTx 4
240 #define XCVR_100baseFx 5
243 #define XCVR_ExtMII 9
244 #define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */
246 struct descriptor { /* A generic descriptor. */
247 u32 next; /* Last entry points to 0 */
248 u32 status; /* FSH -> Frame Start Header */
249 u32 addr; /* Up to 63 addr/len pairs possible */
250 u32 length; /* Set LAST_FRAG to indicate last pair */
253 /* Misc. definitions */
255 #define NUM_RX_DESC PKTBUFSRX * 10
256 #define NUM_TX_DESC 1 /* Number of TX descriptors */
258 #define TOUT_LOOP 1000000
262 #define EL3WINDOW(dev, win_num) ETH_OUTW(dev, SelectWindow + (win_num), EL3_CMD)
264 #define EL3_STATUS 0x0e
270 #define PRINTF(fmt,args...) printf (fmt ,##args)
272 #define PRINTF(fmt,args...)
276 static struct rx_desc_3com *rx_ring; /* RX descriptor ring */
277 static struct tx_desc_3com *tx_ring; /* TX descriptor ring */
278 static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN];/* storage for the incoming messages */
279 static int rx_next = 0; /* RX descriptor ring pointer */
280 static int tx_next = 0; /* TX descriptor ring pointer */
281 static int tx_threshold;
283 static void init_rx_ring(struct eth_device* dev);
284 static void purge_tx_ring(struct eth_device* dev);
286 static void read_hw_addr(struct eth_device* dev, bd_t * bis);
288 static int eth_3com_init(struct eth_device* dev, bd_t *bis);
289 static int eth_3com_send(struct eth_device* dev, volatile void *packet, int length);
290 static int eth_3com_recv(struct eth_device* dev);
291 static void eth_3com_halt(struct eth_device* dev);
293 #define io_to_phys(a) pci_io_to_phys((pci_dev_t)dev->priv, a)
294 #define phys_to_io(a) pci_phys_to_io((pci_dev_t)dev->priv, a)
295 #define mem_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
296 #define phys_to_mem(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
298 static inline int ETH_INL(struct eth_device* dev, u_long addr)
300 __asm__ volatile ("eieio");
301 return le32_to_cpu(*(volatile u32 *)io_to_phys(addr + dev->iobase));
304 static inline int ETH_INW(struct eth_device* dev, u_long addr)
306 __asm__ volatile ("eieio");
307 return le16_to_cpu(*(volatile u16 *)io_to_phys(addr + dev->iobase));
310 static inline int ETH_INB(struct eth_device* dev, u_long addr)
312 __asm__ volatile ("eieio");
313 return *(volatile u8 *)io_to_phys(addr + dev->iobase);
316 static inline void ETH_OUTB(struct eth_device* dev, int command, u_long addr)
318 *(volatile u8 *)io_to_phys(addr + dev->iobase) = command;
319 __asm__ volatile ("eieio");
322 static inline void ETH_OUTW(struct eth_device* dev, int command, u_long addr)
324 *(volatile u16 *)io_to_phys(addr + dev->iobase) = cpu_to_le16(command);
325 __asm__ volatile ("eieio");
328 static inline void ETH_OUTL(struct eth_device* dev, int command, u_long addr)
330 *(volatile u32 *)io_to_phys(addr + dev->iobase) = cpu_to_le32(command);
331 __asm__ volatile ("eieio");
334 static inline int ETH_STATUS(struct eth_device* dev)
336 __asm__ volatile ("eieio");
337 return le16_to_cpu(*(volatile u16 *)io_to_phys(EL3_STATUS + dev->iobase));
340 static inline void ETH_CMD(struct eth_device* dev, int command)
342 *(volatile u16 *)io_to_phys(EL3_CMD + dev->iobase) = cpu_to_le16(command);
343 __asm__ volatile ("eieio");
346 /* Command register is always in the same spot in all the register windows */
347 /* This function issues a command and waits for it so complete by checking the CmdInProgress bit */
349 static int issue_and_wait(struct eth_device* dev, int command)
354 ETH_CMD(dev, command);
355 for (i = 0; i < 2000; i++) {
356 status = ETH_STATUS(dev);
357 /*printf ("Issue: status 0x%4x.\n", status); */
358 if (!(status & CmdInProgress))
362 /* OK, that didn't work. Do it the slow way. One second */
363 for (i = 0; i < 100000; i++) {
364 status = ETH_STATUS(dev);
365 /*printf ("Issue: status 0x%4x.\n", status); */
369 PRINTF("Ethernet command: 0x%4x did not complete! Status: 0x%4x\n", command, ETH_STATUS(dev) );
373 /* Determine network media type and set up 3com accordingly */
374 /* I think I'm going to start with something known first like 10baseT */
376 static int auto_negotiate (struct eth_device *dev)
382 /* Wait for Auto negotiation to complete */
383 for (i = 0; i <= 1000; i++) {
384 if (ETH_INW (dev, 2) & 0x04)
389 PRINTF ("Error: Auto negotiation failed\n");
398 void eth_interrupt (struct eth_device *dev)
400 u16 status = ETH_STATUS (dev);
402 printf ("eth0: status = 0x%04x\n", status);
404 if (!(status & IntLatch))
407 if (status & (1 << 6)) {
408 ETH_CMD (dev, AckIntr | (1 << 6));
409 printf ("Acknowledged Interrupt command\n");
412 if (status & DownComplete) {
413 ETH_CMD (dev, AckIntr | DownComplete);
414 printf ("Acknowledged DownComplete\n");
417 if (status & UpComplete) {
418 ETH_CMD (dev, AckIntr | UpComplete);
419 printf ("Acknowledged UpComplete\n");
422 ETH_CMD (dev, AckIntr | IntLatch);
423 printf ("Acknowledged IntLatch\n");
426 int eth_3com_initialize (bd_t * bis)
428 u32 eth_iobase = 0, status;
429 int card_number = 0, ret;
430 struct eth_device *dev;
434 s = getenv ("3com_base");
436 /* Find ethernet controller on the PCI bus */
439 pci_find_device (PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C,
441 PRINTF ("Error: Cannot find the ethernet device on the PCI bus\n");
446 unsigned long base = atoi (s);
448 pci_write_config_dword (devno, PCI_BASE_ADDRESS_0,
452 ret = pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, ð_iobase);
455 PRINTF ("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
457 pci_write_config_dword (devno, PCI_COMMAND,
458 PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
461 /* Check if I/O accesses and Bus Mastering are enabled */
463 ret = pci_read_config_dword (devno, PCI_COMMAND, &status);
465 if (!(status & PCI_COMMAND_IO)) {
466 printf ("Error: Cannot enable IO access.\n");
470 if (!(status & PCI_COMMAND_MEMORY)) {
471 printf ("Error: Cannot enable MEMORY access.\n");
475 if (!(status & PCI_COMMAND_MASTER)) {
476 printf ("Error: Cannot enable Bus Mastering.\n");
480 dev = (struct eth_device *) malloc (sizeof (*dev)); /*struct eth_device)); */
482 sprintf (dev->name, "3Com 3c920c#%d", card_number);
483 dev->iobase = eth_iobase;
484 dev->priv = (void *) devno;
485 dev->init = eth_3com_init;
486 dev->halt = eth_3com_halt;
487 dev->send = eth_3com_send;
488 dev->recv = eth_3com_recv;
493 /* char interrupt; */
494 /* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */
495 /* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */
497 /* printf("Installing eth0 interrupt handler to %d\n", interrupt); */
498 /* irq_install_handler(interrupt, eth_interrupt, dev); */
503 /* Set the latency timer for value */
504 s = getenv ("3com_latency");
506 ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER,
507 (unsigned char) atoi (s));
509 ret = pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x0a);
511 read_hw_addr (dev, bis); /* get the MAC address from Window 2 */
513 /* Reset the ethernet controller */
515 PRINTF ("Issuing reset command....\n");
516 if (!issue_and_wait (dev, TotalReset)) {
517 printf ("Error: Cannot reset ethernet controller.\n");
520 PRINTF ("Ethernet controller reset.\n");
522 /* allocate memory for rx and tx rings */
524 if (!(rx_ring = memalign (sizeof (struct rx_desc_3com) * NUM_RX_DESC, 16))) {
525 PRINTF ("Cannot allocate memory for RX_RING.....\n");
529 if (!(tx_ring = memalign (sizeof (struct tx_desc_3com) * NUM_TX_DESC, 16))) {
530 PRINTF ("Cannot allocate memory for TX_RING.....\n");
539 static int eth_3com_init (struct eth_device *dev, bd_t * bis)
543 u16 status_enable, intr_enable;
544 struct descriptor *ias_cmd;
546 /* Determine what type of network the machine is connected to */
547 /* presently drops the connect to 10Mbps */
549 if (!auto_negotiate (dev)) {
550 printf ("Error: Cannot determine network media.\n");
554 issue_and_wait (dev, TxReset);
555 issue_and_wait (dev, RxReset | 0x04);
557 /* Switch to register set 7 for normal use. */
560 /* Initialize Rx and Tx rings */
565 ETH_CMD (dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
567 issue_and_wait (dev, SetTxStart | 0x07ff);
569 /* Below sets which indication bits to be seen. */
572 SetStatusEnb | HostError | DownComplete | UpComplete | (1 <<
574 ETH_CMD (dev, status_enable);
576 /* Below sets no bits are to cause an interrupt since this is just polling */
578 intr_enable = SetIntrEnb;
579 /* intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */
580 ETH_CMD (dev, intr_enable);
581 ETH_OUTB (dev, 127, UpPoll);
583 /* Ack all pending events, and set active indicator mask */
585 ETH_CMD (dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
586 ETH_CMD (dev, intr_enable);
588 /* Tell the adapter where the RX ring is located */
590 issue_and_wait (dev, UpStall); /* Stall and set the UplistPtr */
591 ETH_OUTL (dev, (u32) & rx_ring[rx_next], UpListPtr);
592 ETH_CMD (dev, RxEnable); /* Enable the receiver. */
593 issue_and_wait (dev, UpUnstall);
595 /* Send the Individual Address Setup frame */
598 tx_next = ((tx_next + 1) % NUM_TX_DESC);
600 ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
601 ias_cmd->status = cpu_to_le32 (1 << 31); /* set DnIndicate bit. */
603 ias_cmd->addr = cpu_to_le32 ((u32) dev->enetaddr);
604 ias_cmd->length = cpu_to_le32 (6 | LAST_FRAG);
606 /* Tell the adapter where the TX ring is located */
608 ETH_CMD (dev, TxEnable); /* Enable transmitter. */
609 issue_and_wait (dev, DownStall); /* Stall and set the DownListPtr. */
610 ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr);
611 issue_and_wait (dev, DownUnstall);
612 for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) {
613 if (i >= TOUT_LOOP) {
614 PRINTF ("TX Ring status (Init): 0x%4x\n",
615 le32_to_cpu (tx_ring[tx_cur].status));
616 PRINTF ("ETH_STATUS: 0x%x\n", ETH_STATUS (dev));
620 if (ETH_STATUS (dev) & DownComplete) { /* If DownLoad Complete ACK the bit */
621 ETH_CMD (dev, AckIntr | DownComplete); /* acknowledge the indication bit */
622 issue_and_wait (dev, DownStall); /* stall and clear DownListPtr */
623 ETH_OUTL (dev, 0, DownListPtr);
624 issue_and_wait (dev, DownUnstall);
631 int eth_3com_send (struct eth_device *dev, volatile void *packet, int length)
637 PRINTF ("eth: bad packet size: %d\n", length);
642 tx_next = (tx_next + 1) % NUM_TX_DESC;
644 tx_ring[tx_cur].status = cpu_to_le32 (1 << 31); /* set DnIndicate bit */
645 tx_ring[tx_cur].next = 0;
646 tx_ring[tx_cur].addr = cpu_to_le32 (((u32) packet));
647 tx_ring[tx_cur].length = cpu_to_le32 (length | LAST_FRAG);
649 /* Send the packet */
651 issue_and_wait (dev, DownStall); /* stall and set the DownListPtr */
652 ETH_OUTL (dev, (u32) & tx_ring[tx_cur], DownListPtr);
653 issue_and_wait (dev, DownUnstall);
655 for (i = 0; !(ETH_STATUS (dev) & DownComplete); i++) {
656 if (i >= TOUT_LOOP) {
657 PRINTF ("TX Ring status (send): 0x%4x\n",
658 le32_to_cpu (tx_ring[tx_cur].status));
662 if (ETH_STATUS (dev) & DownComplete) { /* If DownLoad Complete ACK the bit */
663 ETH_CMD (dev, AckIntr | DownComplete); /* acknowledge the indication bit */
664 issue_and_wait (dev, DownStall); /* stall and clear DownListPtr */
665 ETH_OUTL (dev, 0, DownListPtr);
666 issue_and_wait (dev, DownUnstall);
673 void PrintPacket (uchar * packet, int length)
678 printf ("Printing packet of length %x.\n\n", length);
680 for (loop = 1; loop <= length; loop++) {
681 printf ("%2x ", *ptr++);
682 if ((loop % 40) == 0)
687 int eth_3com_recv (struct eth_device *dev)
691 int rx_prev, length = 0;
693 while (!(ETH_STATUS (dev) & UpComplete)) /* wait on receipt of packet */
696 status = le32_to_cpu (rx_ring[rx_next].status); /* packet status */
698 while (status & (1 << 15)) {
699 /* A packet has been received */
701 if (status & (1 << 15)) {
702 /* A valid frame received */
704 length = le32_to_cpu (rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */
706 /* Pass the packet up to the protocol layers */
708 NetReceive ((uchar *)
709 le32_to_cpu (rx_ring[rx_next].addr),
711 rx_ring[rx_next].status = 0; /* clear the status word */
712 ETH_CMD (dev, AckIntr | UpComplete);
713 issue_and_wait (dev, UpUnstall);
714 } else if (stat & HostError) {
715 /* There was an error */
717 printf ("Rx error status: 0x%4x\n", stat);
723 rx_next = (rx_next + 1) % NUM_RX_DESC;
724 stat = ETH_STATUS (dev); /* register status */
725 status = le32_to_cpu (rx_ring[rx_next].status); /* packet status */
731 void eth_3com_halt (struct eth_device *dev)
733 if (!(dev->iobase)) {
737 issue_and_wait (dev, DownStall); /* shut down transmit and receive */
738 issue_and_wait (dev, UpStall);
739 issue_and_wait (dev, RxDisable);
740 issue_and_wait (dev, TxDisable);
742 /* free(tx_ring); /###* release memory allocated to the DPD and UPD rings */
749 static void init_rx_ring (struct eth_device *dev)
753 PRINTF ("Initializing rx_ring. rx_buffer = %p\n", rx_buffer);
754 issue_and_wait (dev, UpStall);
756 for (i = 0; i < NUM_RX_DESC; i++) {
758 cpu_to_le32 (((u32) &
759 rx_ring[(i + 1) % NUM_RX_DESC]));
760 rx_ring[i].status = 0;
761 rx_ring[i].addr = cpu_to_le32 (((u32) & rx_buffer[i][0]));
762 rx_ring[i].length = cpu_to_le32 (PKTSIZE_ALIGN | LAST_FRAG);
767 static void purge_tx_ring (struct eth_device *dev)
771 PRINTF ("Purging tx_ring.\n");
775 for (i = 0; i < NUM_TX_DESC; i++) {
777 tx_ring[i].status = 0;
779 tx_ring[i].length = 0;
783 static void read_hw_addr (struct eth_device *dev, bd_t * bis)
785 u8 hw_addr[ETH_ALEN];
786 unsigned int eeprom[0x40];
787 unsigned int checksum = 0;
790 /* First, try the env ... if that works, we're all done! */
791 if (eth_getenv_enetaddr("ethaddr", hw_addr))
794 /* Read the station address from the EEPROM. */
797 for (i = 0; i < 0x40; i++) {
798 ETH_OUTW (dev, EEPROM_Read + i, Wn0EepromCmd);
799 /* Pause for at least 162 us. for the read to take place. */
800 for (timer = 10; timer >= 0; timer--) {
802 if ((ETH_INW (dev, Wn0EepromCmd) & 0x8000) == 0)
805 eeprom[i] = ETH_INW (dev, Wn0EepromData);
808 /* Checksum calculation. I'm not sure about this part and there seems to be a bug on the 3com side of things */
810 for (i = 0; i < 0x21; i++)
811 checksum ^= eeprom[i];
812 checksum = (checksum ^ (checksum >> 8)) & 0xff;
814 if (checksum != 0xbb)
815 printf (" *** INVALID EEPROM CHECKSUM %4.4x *** \n",
818 for (i = 0, j = 0; i < 3; i++) {
819 hw_addr[j++] = (u8) ((eeprom[i + 10] >> 8) & 0xff);
820 hw_addr[j++] = (u8) (eeprom[i + 10] & 0xff);
823 /* MAC Address is in window 2, write value from EEPROM to window 2 */
826 for (i = 0; i < 6; i++)
827 ETH_OUTB (dev, hw_addr[i], i);
829 for (j = 0; j < ETH_ALEN; j += 2) {
830 hw_addr[j] = (u8) (ETH_INW (dev, j) & 0xff);
831 hw_addr[j + 1] = (u8) ((ETH_INW (dev, j) >> 8) & 0xff);
834 /* Save the result in the environment */
835 eth_setenv_enetaddr("ethaddr", hw_addr);
838 memcpy(dev->enetaddr, hw_addr, 6);