3 * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 DECLARE_GLOBAL_DATA_PTR;
36 #define PRINTF(fmt,args...) printf (fmt ,##args)
38 #define PRINTF(fmt,args...)
42 /* Setup the ISA-to-PCI host bridge */
43 void via_isa_init(pci_dev_t dev, struct pci_config_table *table)
46 if (PCI_FUNC(dev) == 0)
48 PRINTF("... PCI-to-ISA bridge, dev=0x%X\n", dev);
50 /* Enable I/O Recovery time */
51 pci_write_config_byte(dev, 0x40, 0x08);
53 /* Enable ISA refresh */
54 pci_write_config_byte(dev, 0x41, 0x41); /* was 01 */
56 /* Enable ISA line buffer */
57 pci_write_config_byte(dev, 0x45, 0x80);
59 /* Gate INTR, and flush line buffer */
60 pci_write_config_byte(dev, 0x46, 0x60);
62 /* Enable EISA ports 4D0/4D1. Do we need this ? */
63 pci_write_config_byte(dev, 0x47, 0xe6); /* was 20 */
65 /* 512 K PCI Decode */
66 pci_write_config_byte(dev, 0x48, 0x01);
68 /* Wait for PGNT before grant to ISA Master/DMA */
69 /* ports 0-FF to SDBus */
70 /* IRQ 14 and 15 for ide 0/1 */
71 pci_write_config_byte(dev, 0x4a, 0x04); /* Was c4 */
74 /* Parallel DRQ 3, Floppy DRQ 2 (default) */
75 pci_write_config_byte(dev, 0x50, 0x0e);
77 /* IRQ Routing for Floppy and Parallel port */
78 /* IRQ 6 for floppy, IRQ 7 for parallel port */
79 pci_write_config_byte(dev, 0x51, 0x76);
81 /* IRQ Routing for serial ports (take IRQ 3 and 4) */
82 pci_write_config_byte(dev, 0x52, 0x34);
84 /* All IRQ's level triggered. */
85 pci_write_config_byte(dev, 0x54, 0x00);
87 /* PCI IRQ's all at IRQ 9 */
88 pci_write_config_byte(dev, 0x55, 0x90);
89 pci_write_config_byte(dev, 0x56, 0x99);
90 pci_write_config_byte(dev, 0x57, 0x90);
93 pci_read_config_byte(dev, 0x5A, ®val);
95 pci_write_config_byte(dev, 0x5A, regval);
97 pci_write_config_byte(dev, 0x80, 0);
98 pci_write_config_byte(dev, 0x85, 0x01);
100 /* pci_write_config_byte(dev, 0x77, 0x00); */
105 * Initialize PNP irq routing
108 void via_init_irq_routing(uint8 irq_map[])
111 uint8 level_edge_bits = 0xf;
113 /* Set irq routings */
114 pci_write_cfg_byte(0, 7<<3, 0x55, irq_map[0]<<4);
115 pci_write_cfg_byte(0, 7<<3, 0x56, irq_map[1] | irq_map[2]<<4);
116 pci_write_cfg_byte(0, 7<<3, 0x57, irq_map[3]<<4);
119 * Gather level/edge bits
120 * Default is to assume level triggered
123 s = getenv("pci_irqa_select");
124 if (s && strcmp(s, "level") == 0)
125 level_edge_bits &= ~0x01;
127 s = getenv("pci_irqb_select");
128 if (s && strcmp(s, "level") == 0)
129 level_edge_bits &= ~0x02;
131 s = getenv("pci_irqc_select");
132 if (s && strcmp(s, "level") == 0)
133 level_edge_bits &= ~0x04;
135 s = getenv("pci_irqd_select");
136 if (s && strcmp(s, "level") == 0)
137 level_edge_bits &= ~0x08;
140 PRINTF("%d: %s\n", irq_map[0], level_edge_bits&0x1 ? "edge" : "level");
141 PRINTF("%d: %s\n", irq_map[1], level_edge_bits&0x2 ? "edge" : "level");
142 PRINTF("%d: %s\n", irq_map[2], level_edge_bits&0x4 ? "edge" : "level");
143 PRINTF("%d: %s\n", irq_map[3], level_edge_bits&0x8 ? "edge" : "level");
144 pci_write_cfg_byte(0, 7<<3, 0x54, level_edge_bits);
146 PRINTF("%02x %02x %02x %02x\n", pci_read_cfg_byte(0, 7<<3, 0x54),
147 pci_read_cfg_byte(0, 7<<3, 0x55), pci_read_cfg_byte(0, 7<<3, 0x56),
148 pci_read_cfg_byte(0, 7<<3, 0x57));
152 /* Setup the IDE controller. This doesn't seem to work yet. I/O to an IDE controller port */
153 /* always return the last character output on the serial port (!) */
154 /* This function is called by the pnp-library when it encounters 0:7:1 */
155 void via_cfgfunc_ide_init(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table)
157 PRINTF("... IDE controller, dev=0x%X\n", dev);
159 /* Enable both IDE channels. */
160 pci_write_config_byte(dev, 0x40, 0x03);
164 /* Enable IO Space */
165 pci_write_config_word(dev, 0x04, 0x03);
167 /* Set to compatibility mode */
168 pci_write_config_byte(dev, 0x09, 0x8A); /* WAS: 0x8f); */
170 /* Set to legacy interrupt mode */
171 pci_write_config_byte(dev, 0x3d, 0x00); /* WAS: 0x01); */
176 /* Set the base address of the floppy controller to 0x3F0 */
177 void via_fdc_init(pci_dev_t dev)
180 /* Enable Configuration mode */
181 pci_read_config_byte(dev, 0x85, &c);
183 pci_write_config_byte(dev, 0x85, c);
185 /* Set floppy controller port to 0x3F0. */
186 SIO_WRITE_CONFIG(0xE3, (0x3F<<2));
188 /* Enable floppy controller */
189 SIO_READ_CONFIG(0xE2, c);
191 SIO_WRITE_CONFIG(0xE2, c);
193 /* Switch of configuration mode */
194 pci_read_config_byte(dev, 0x85, &c);
196 pci_write_config_byte(dev, 0x85, c);
199 /* Init function 0 of the via southbridge. Called by the pnp-library */
200 void via_cfgfunc_via686(struct pci_controller *host, pci_dev_t dev, struct pci_config_table *table)
202 if (PCI_FUNC(dev) == 0)
204 /* FIXME: Try to generate a PCI reset */
205 /* unsigned char c; */
206 /* pci_read_config_byte(dev, 0x47, &c); */
207 /* pci_write_config_byte(dev, 0x47, c | 0x01); */
209 via_isa_init(dev, table);
214 __asm (" .globl via_calibrate_time_base \n"
215 "via_calibrate_time_base: \n"
223 " andi. 0, 0, 0x20 \n"
229 extern unsigned long via_calibrate_time_base(void);
231 void via_calibrate_bus_freq (void)
235 /* This is 20 microseconds */
236 #define CALIBRATE_TIME 28636
238 /* Enable the timer (and disable speaker) */
242 out_byte (0x61, ((c & ~0x02) | 0x01));
244 /* Set timer 2 to low/high writing */
245 out_byte (0x43, 0xb0);
246 out_byte (0x42, CALIBRATE_TIME & 0xff);
247 out_byte (0x42, CALIBRATE_TIME >> 8);
249 /* Read the time base */
250 tb = via_calibrate_time_base ();
253 gd->bus_clk = 133333333;
255 gd->bus_clk = 100000000;
260 void ide_led(uchar led, uchar status)
262 /* unsigned char c = in_byte(0x92); */
265 /* out_byte(0x92, c | 0xC0); */
267 /* out_byte(0x92, c & ~0xC0); */
271 void via_init_afterscan(void)
273 /* Modify IDE controller setup */
274 pci_write_cfg_byte(0, 7<<3|1, PCI_LATENCY_TIMER, 0x20);
275 pci_write_cfg_byte(0, 7<<3|1, PCI_COMMAND, PCI_COMMAND_IO|PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER);
276 pci_write_cfg_byte(0, 7<<3|1, PCI_INTERRUPT_LINE, 0xff);
277 pci_write_cfg_byte(0, 7<<3|1, 0x40, 0x0b); /* FIXME: Might depend on drives connected */
278 pci_write_cfg_byte(0, 7<<3|1, 0x41, 0x42); /* FIXME: Might depend on drives connected */
279 pci_write_cfg_byte(0, 7<<3|1, 0x43, 0x05);
280 pci_write_cfg_byte(0, 7<<3|1, 0x44, 0x18);
281 pci_write_cfg_byte(0, 7<<3|1, 0x45, 0x10);
282 pci_write_cfg_byte(0, 7<<3|1, 0x4e, 0x22); /* FIXME: Not documented, but set in PC bios */
283 pci_write_cfg_byte(0, 7<<3|1, 0x4f, 0x20); /* FIXME: Not documented */
285 /* Modify some values in the USB controller */
286 pci_write_cfg_byte(0, 7<<3|2, 0x05, 0x17);
287 pci_write_cfg_byte(0, 7<<3|2, 0x06, 0x01);
288 pci_write_cfg_byte(0, 7<<3|2, 0x41, 0x12);
289 pci_write_cfg_byte(0, 7<<3|2, 0x42, 0x03);
290 pci_write_cfg_byte(0, 7<<3|2, PCI_LATENCY_TIMER, 0x40);
292 pci_write_cfg_byte(0, 7<<3|3, 0x05, 0x17);
293 pci_write_cfg_byte(0, 7<<3|3, 0x06, 0x01);
294 pci_write_cfg_byte(0, 7<<3|3, 0x41, 0x12);
295 pci_write_cfg_byte(0, 7<<3|3, 0x42, 0x03);
296 pci_write_cfg_byte(0, 7<<3|3, PCI_LATENCY_TIMER, 0x40);