2 * Copyright - Galileo technology.
4 * SPDX-License-Identifier: GPL-2.0+
9 * written or collected and sometimes rewritten by
10 * Ingo Assmus <ingo.assmus@keymile.com>
16 #include "../include/core.h"
17 #include "../include/memory.h"
19 /*******************************************************************************
20 * memoryGetBankBaseAddress - Returns the base address of a memory bank.
22 * This function returns the base address of one of the SDRAM's memory
23 * banks. There are 4 memory banks and each one represents one DIMM side.
25 * MEMORY_BANK bank - Selects one of the four banks as defined in Memory.h.
29 * 32 bit Memory bank base address.
30 *******************************************************************************/
31 static unsigned long memoryGetBankRegOffset (MEMORY_BANK bank)
35 return SCS_0_LOW_DECODE_ADDRESS;
37 return SCS_1_LOW_DECODE_ADDRESS;
39 return SCS_2_LOW_DECODE_ADDRESS;
41 return SCS_3_LOW_DECODE_ADDRESS;
44 return SCS_0_LOW_DECODE_ADDRESS; /* default value */
47 unsigned int memoryGetBankBaseAddress (MEMORY_BANK bank)
50 unsigned int regOffset = memoryGetBankRegOffset (bank);
52 GT_REG_READ (regOffset, &base);
53 base = base << 16; /* MV6436x */
57 /*******************************************************************************
58 * memoryGetDeviceBaseAddress - Returns the base address of a device.
60 * This function returns the base address of a device on the system. There
61 * are 5 possible devices (0 - 4 and one boot device) as defined in
62 * gtMemory.h. Each of the device parameters is maped to one of the CS
63 * (Devices chip selects) base address register.
65 * device - Selects one of the five devices as defined in Memory.h.
69 * 32 bit Device base address.
71 *******************************************************************************/
72 static unsigned int memoryGetDeviceRegOffset (DEVICE device)
76 return CS_0_LOW_DECODE_ADDRESS;
78 return CS_1_LOW_DECODE_ADDRESS;
80 return CS_2_LOW_DECODE_ADDRESS;
82 return CS_3_LOW_DECODE_ADDRESS;
84 return BOOTCS_LOW_DECODE_ADDRESS;
86 return CS_0_LOW_DECODE_ADDRESS; /* default value */
89 unsigned int memoryGetDeviceBaseAddress (DEVICE device)
92 unsigned int regOffset = memoryGetDeviceRegOffset (device);
94 GT_REG_READ (regOffset, ®Base);
96 regBase = regBase << 16; /* MV6436x */
100 /*******************************************************************************
101 * MemoryGetPciBaseAddr - Returns the base address of a PCI window.
103 * This function returns the base address of a PCI window. There are 5
104 * possible PCI windows (memory 0 - 3 and one for I/O) for each PCI
105 * interface as defined in gtMemory.h, used by the CPU's address decoding
109 * pciWindow - Selects one of the PCI windows as defined in Memory.h.
113 * 32 bit PCI window base address.
114 *******************************************************************************/
115 unsigned int MemoryGetPciBaseAddr (PCI_MEM_WINDOW pciWindow)
117 unsigned int baseAddrReg, base;
121 baseAddrReg = PCI_0I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */
124 baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */
127 baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */
130 baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */
133 baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */
137 baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */
140 baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */
143 baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */
146 baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */
149 baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */
151 #endif /* INCLUDE_PCI_1 */
155 GT_REG_READ (baseAddrReg, &base);
159 /*******************************************************************************
160 * memoryGetBankSize - Returns the size of a memory bank.
162 * This function returns the size of memory bank as described in
163 * 'gtMemoryGetBankBaseAddress' function.
165 * bank - Selects one of the four banks as defined in Memory.h.
169 * 32 bit size memory bank size or 0 for a closed or non populated bank.
171 *******************************************************************************/
172 unsigned int memoryGetBankSize (MEMORY_BANK bank)
174 unsigned int sizeReg, size;
175 MEMORY_WINDOW window;
179 sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /* CS_0_SIZE; */
180 window = CS_0_WINDOW;
183 sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /* CS_1_SIZE; */
184 window = CS_1_WINDOW;
187 sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /* CS_2_SIZE; */
188 window = CS_2_WINDOW;
191 sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /* CS_3_SIZE; */
192 window = CS_3_WINDOW;
198 /* If the window is closed, a size of 0 is returned */
199 if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
201 GT_REG_READ (sizeReg, &size);
202 size = ((size << 16) | 0xffff) + 1;
206 /*******************************************************************************
207 * memoryGetDeviceSize - Returns the size of a device memory space.
209 * This function returns the memory space size of a given device.
211 * device - Selects one of the five devices as defined in Memory.h.
215 * 32 bit size of a device memory space.
216 *******************************************************************************/
217 unsigned int memoryGetDeviceSize (DEVICE device)
219 unsigned int sizeReg, size;
220 MEMORY_WINDOW window;
224 sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */
225 window = DEVCS_0_WINDOW;
228 sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */
229 window = DEVCS_1_WINDOW;
232 sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */
233 window = DEVCS_2_WINDOW;
236 sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */
237 window = DEVCS_3_WINDOW;
240 sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */
241 window = BOOT_CS_WINDOW;
247 /* If the window is closed, a size of 0 is returned */
248 if (MemoryGetMemWindowStatus (window) != MEM_WINDOW_ENABLED)
250 GT_REG_READ (sizeReg, &size);
251 size = ((size << 16) | 0xffff) + 1;
255 /*******************************************************************************
256 * MemoryGetPciWindowSize - Returns the size of a PCI memory window.
258 * This function returns the size of a PCI window.
260 * pciWindow - Selects one of the PCI memory windows as defined in
265 * 32 bit size of a PCI memory window.
266 *******************************************************************************/
267 unsigned int MemoryGetPciWindowSize (PCI_MEM_WINDOW pciWindow)
269 unsigned int sizeReg, size;
273 sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */
276 sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */
279 sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */
282 sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */
285 sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */
289 sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */
292 sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */
295 sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */
298 sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */
301 sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */
303 #endif /* INCLUDE_PCI_1 */
307 /* If the memory window is disabled, retrun size = 0 */
308 if (MemoryGetMemWindowStatus (PCI_0_IO_WINDOW << pciWindow)
309 == MEM_WINDOW_DISABLED)
311 GT_REG_READ (sizeReg, &size);
312 size = ((size << 16) | 0xffff) + 1;
316 /*******************************************************************************
317 * memoryGetDeviceWidth - Returns the width of a given device.
319 * The MV's device interface supports up to 32 Bit wide devices. A device
320 * can have a 1, 2, 4 or 8 Bytes data width. This function returns the
321 * width of a device as defined by the user or the operating system.
323 * device - Selects one of the five devices as defined in Memory.h.
327 * Device width in Bytes (1,2,4 or 8), 0 if error had occurred.
328 *******************************************************************************/
329 unsigned int memoryGetDeviceWidth (DEVICE device)
332 unsigned int regValue;
334 GT_REG_READ (DEVICE_BANK0PARAMETERS + device * 4, ®Value);
335 width = (regValue & (BIT20 | BIT21)) >> 20;
336 return (BIT0 << width);
339 /*******************************************************************************
340 * memoryMapBank - Set new base address and size for one of the memory
344 * The CPU interface address decoding map consists of 21 address windows
345 * for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
346 * window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
347 * space. Each address window is defined by two registers - base and size.
348 * The CPU address is compared with the values in the various CPU windows
349 * until a match is found and the address is than targeted to that window.
350 * This function sets new base and size for one the memory banks
351 * (CS0 - CS3). It is the programmer`s responsibility to make sure that
352 * there are no conflicts with other memory spaces. When two memory spaces
353 * overlap, the MV's behavior is not defined .If a bank needs to be closed,
354 * set the 'bankLength' parameter size to 0x0.
357 * bank - One of the memory banks (CS0-CS3) as defined in gtMemory.h.
358 * bankBase - The memory bank base address.
359 * bankLength - The memory bank size. This function will decrement the
360 * 'bankLength' parameter by one and then check if the size is
361 * valid. A valid size must be programed from LSB to MSB as
362 * sequence of '1's followed by sequence of '0's.
363 * To close a memory window simply set the size to 0.
365 * The size must be in 64Kbyte granularity.
366 * The base address must be aligned to the size.
370 * false for invalid size, true otherwise.
372 * CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
374 *******************************************************************************/
376 bool memoryMapBank (MEMORY_BANK bank, unsigned int bankBase,
377 unsigned int bankLength)
379 unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
381 /* PCI_INTERNAL_BAR pciBAR; */
385 baseReg = SCS_0_LOW_DECODE_ADDRESS; /*CS_0_BASE_ADDR; */
386 sizeReg = SCS_0_HIGH_DECODE_ADDRESS; /*CS_0_SIZE; */
387 /* pciBAR = PCI_CS0_BAR; */
390 baseReg = SCS_1_LOW_DECODE_ADDRESS; /*CS_1_BASE_ADDR; */
391 sizeReg = SCS_1_HIGH_DECODE_ADDRESS; /*CS_1_SIZE; */
392 /* pciBAR = SCS_0_HIGH_DECODE_ADDRESS; */ /*PCI_CS1_BAR; */
395 baseReg = SCS_2_LOW_DECODE_ADDRESS; /*CS_2_BASE_ADDR; */
396 sizeReg = SCS_2_HIGH_DECODE_ADDRESS; /*CS_2_SIZE; */
397 /* pciBAR = PCI_CS2_BAR;*/
400 baseReg = SCS_3_LOW_DECODE_ADDRESS; /*CS_3_BASE_ADDR; */
401 sizeReg = SCS_3_HIGH_DECODE_ADDRESS; /*CS_3_SIZE; */
402 /* pciBAR = PCI_CS3_BAR; */
407 /* If the size is 0, the window will be disabled */
408 if (bankLength == 0) {
409 MemoryDisableWindow (CS_0_WINDOW << bank);
410 /* Disable the BAR from the PCI slave side */
411 /* gtPci0DisableInternalBAR(pciBAR); */
412 /* gtPci1DisableInternalBAR(pciBAR); */
415 /* The base address must be aligned to the size */
416 if ((bankBase % bankLength) != 0) {
419 if (bankLength >= MINIMUM_MEM_BANK_SIZE) {
420 newBase = bankBase >> 16;
421 newSize = bankLength >> 16;
422 /* Checking that the size is a sequence of '1' followed by a
423 sequence of '0' starting from LSB to MSB. */
425 for (rShift = 0; rShift < 16; rShift++) {
426 temp = temp >> rShift;
427 if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
428 /* or the size is not valid */
437 unsigned int oldBase, oldSize;
439 GT_REG_READ (baseReg, &oldBase);
440 GT_REG_READ (sizeReg + 8, &oldSize);
442 printf ("b%d Base:%x Size:%x -> Base:%x Size:%x\n",
443 bank, oldBase, oldSize, newBase, newSize);
446 /* writing the new values */
447 GT_REG_WRITE (baseReg, newBase);
448 GT_REG_WRITE (sizeReg, newSize - 1);
449 /* Enable back the window */
450 MemoryEnableWindow (CS_0_WINDOW << bank);
451 /* Enable the BAR from the PCI slave side */
452 /* gtPci0EnableInternalBAR(pciBAR); */
453 /* gtPci1EnableInternalBAR(pciBAR); */
460 /*******************************************************************************
461 * memoryMapDeviceSpace - Set new base address and size for one of the device
465 * The CPU interface address decoding map consists of 21 address windows
466 * for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
467 * window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
468 * space. Each address window is defined by two registers - base and size.
469 * The CPU address is compared with the values in the various CPU windows
470 * until a match is found and the address is than targeted to that window.
471 * This function sets new base and size for one the device windows
472 * (DEV_CS0 - DEV_CS3). It is the programmer`s responsibility to make sure
473 * that there are no conflicts with other memory spaces. When two memory
474 * spaces overlap, the MV's behavior is not defined .If a device window
475 * needs to be closed, set the 'deviceLength' parameter size to 0x0.
478 * device - One of the device windows (DEV_CS0-DEV_CS3) as
479 * defined in gtMemory.h.
480 * deviceBase - The device window base address.
481 * deviceLength - The device window size. This function will decrement
482 * the 'deviceLength' parameter by one and then
483 * check if the size is valid. A valid size must be
484 * programed from LSB to MSB as sequence of '1's
485 * followed by sequence of '0's.
486 * To close a memory window simply set the size to 0.
489 * The size must be in 64Kbyte granularity.
490 * The base address must be aligned to the size.
496 * false for invalid size, true otherwise.
498 * CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!!
500 *******************************************************************************/
502 bool memoryMapDeviceSpace (DEVICE device, unsigned int deviceBase,
503 unsigned int deviceLength)
505 unsigned int newBase, newSize, baseReg, sizeReg, temp, rShift;
507 /* PCI_INTERNAL_BAR pciBAR;*/
511 baseReg = CS_0_LOW_DECODE_ADDRESS; /*DEV_CS0_BASE_ADDR; */
512 sizeReg = CS_0_HIGH_DECODE_ADDRESS; /*DEV_CS0_SIZE; */
513 /* pciBAR = PCI_DEV_CS0_BAR; */
516 baseReg = CS_1_LOW_DECODE_ADDRESS; /*DEV_CS1_BASE_ADDR; */
517 sizeReg = CS_1_HIGH_DECODE_ADDRESS; /*DEV_CS1_SIZE; */
518 /* pciBAR = PCI_DEV_CS1_BAR; */
521 baseReg = CS_2_LOW_DECODE_ADDRESS; /*DEV_CS2_BASE_ADDR; */
522 sizeReg = CS_2_HIGH_DECODE_ADDRESS; /*DEV_CS2_SIZE; */
523 /* pciBAR = PCI_DEV_CS2_BAR; */
526 baseReg = CS_3_LOW_DECODE_ADDRESS; /*DEV_CS3_BASE_ADDR; */
527 sizeReg = CS_3_HIGH_DECODE_ADDRESS; /*DEV_CS3_SIZE; */
528 /* pciBAR = PCI_DEV_CS3_BAR; */
531 baseReg = BOOTCS_LOW_DECODE_ADDRESS; /*BOOTCS_BASE_ADDR; */
532 sizeReg = BOOTCS_HIGH_DECODE_ADDRESS; /*BOOTCS_SIZE; */
533 /* pciBAR = PCI_BOOT_CS_BAR; */
538 if (deviceLength == 0) {
539 MemoryDisableWindow (DEVCS_0_WINDOW << device);
540 /* Disable the BAR from the PCI slave side */
541 /* gtPci0DisableInternalBAR(pciBAR); */
542 /* gtPci1DisableInternalBAR(pciBAR); */
545 /* The base address must be aligned to the size */
546 if ((deviceBase % deviceLength) != 0) {
549 if (deviceLength >= MINIMUM_DEVICE_WINDOW_SIZE) {
550 newBase = deviceBase >> 16;
551 newSize = deviceLength >> 16;
552 /* Checking that the size is a sequence of '1' followed by a
553 sequence of '0' starting from LSB to MSB. */
555 for (rShift = 0; rShift < 16; rShift++) {
556 temp = temp >> rShift;
557 if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
558 /* or the size is not valid */
565 /* writing the new values */
566 GT_REG_WRITE (baseReg, newBase);
567 GT_REG_WRITE (sizeReg, newSize - 1);
568 MemoryEnableWindow (DEVCS_0_WINDOW << device);
569 /* Enable the BAR from the PCI slave side */
570 /* gtPci0EnableInternalBAR(pciBAR); */
571 /* gtPci1EnableInternalBAR(pciBAR); */
577 /*******************************************************************************
578 * MemorySetPciWindow - Set new base address and size for one of the PCI
582 * The CPU interface address decoding map consists of 21 address windows
583 * for the different devices (e.g. CS[3:0] ,PCI0 Mem 0/1/2/3...). Each
584 * window can have a minimum of 1Mbytes of address space, and up to 4Gbyte
585 * space. Each address window is defined by two registers - base and size.
586 * The CPU address is compared with the values in the various CPU windows
587 * until a match is found and the address is than targeted to that window.
588 * This function sets new base and size for one the PCI windows
589 * (PCI memory0/1/2..). It is the programmer`s responsibility to make sure
590 * that there are no conflicts with other memory spaces. When two memory
591 * spaces overlap, the MV's behavior is not defined. If a PCI window
592 * needs to be closed, set the 'pciWindowSize' parameter size to 0x0.
595 * pciWindow - One of the PCI windows as defined in gtMemory.h.
596 * pciWindowBase - The PCI window base address.
597 * pciWindowSize - The PCI window size. This function will decrement the
598 * 'pciWindowSize' parameter by one and then check if the
599 * size is valid. A valid size must be programed from LSB
600 * to MSB as sequence of '1's followed by sequence of '0's.
601 * To close a memory window simply set the size to 0.
604 * The size must be in 64Kbyte granularity.
605 * The base address must be aligned to the size.
611 * false for invalid size, true otherwise.
613 *******************************************************************************/
614 bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase,
615 unsigned int pciWindowSize)
617 unsigned int currentLow, baseAddrReg, sizeReg, temp, rShift;
621 baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_0_IO_BASE_ADDR; */
622 sizeReg = PCI_0I_O_HIGH_DECODE_ADDRESS; /*PCI_0_IO_SIZE; */
625 baseAddrReg = PCI_0MEMORY0_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY0_BASE_ADDR; */
626 sizeReg = PCI_0MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY0_SIZE; */
629 baseAddrReg = PCI_0MEMORY1_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY1_BASE_ADDR; */
630 sizeReg = PCI_0MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY1_SIZE; */
633 baseAddrReg = PCI_0MEMORY2_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY2_BASE_ADDR; */
634 sizeReg = PCI_0MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY2_SIZE; */
637 baseAddrReg = PCI_0MEMORY3_LOW_DECODE_ADDRESS; /*PCI_0_MEMORY3_BASE_ADDR; */
638 sizeReg = PCI_0MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_0_MEMORY3_SIZE; */
642 baseAddrReg = PCI_1I_O_LOW_DECODE_ADDRESS; /*PCI_1_IO_BASE_ADDR; */
643 sizeReg = PCI_1I_O_HIGH_DECODE_ADDRESS; /*PCI_1_IO_SIZE; */
646 baseAddrReg = PCI_1MEMORY0_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY0_BASE_ADDR; */
647 sizeReg = PCI_1MEMORY0_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY0_SIZE; */
650 baseAddrReg = PCI_1MEMORY1_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY1_BASE_ADDR; */
651 sizeReg = PCI_1MEMORY1_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY1_SIZE; */
654 baseAddrReg = PCI_1MEMORY2_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY2_BASE_ADDR; */
655 sizeReg = PCI_1MEMORY2_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY2_SIZE; */
658 baseAddrReg = PCI_1MEMORY3_LOW_DECODE_ADDRESS; /*PCI_1_MEMORY3_BASE_ADDR; */
659 sizeReg = PCI_1MEMORY3_HIGH_DECODE_ADDRESS; /*PCI_1_MEMORY3_SIZE; */
661 #endif /* INCLUDE_PCI_1 */
665 if (pciWindowSize == 0) {
666 MemoryDisableWindow (PCI_0_IO_WINDOW << pciWindow);
669 /* The base address must be aligned to the size */
670 if ((pciWindowBase % pciWindowSize) != 0) {
673 if (pciWindowSize >= MINIMUM_PCI_WINDOW_SIZE) {
674 pciWindowBase >>= 16;
675 pciWindowSize >>= 16;
676 /* Checking that the size is a sequence of '1' followed by a
677 sequence of '0' starting from LSB to MSB. */
678 temp = pciWindowSize - 1;
679 for (rShift = 0; rShift < 16; rShift++) {
680 temp = temp >> rShift;
681 if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
682 /* or the size is not valid */
689 GT_REG_WRITE (sizeReg, pciWindowSize - 1);
690 GT_REG_READ (baseAddrReg, ¤tLow);
692 (pciWindowBase & 0xfffff) | (currentLow & 0xfff00000);
693 GT_REG_WRITE (baseAddrReg, pciWindowBase);
694 MemoryEnableWindow (PCI_0_IO_WINDOW << pciWindow);
700 /*******************************************************************************
701 * memoryMapInternalRegistersSpace - Sets new base address for the internal
702 * registers memory space.
705 * This function set new base address for the internal registers memory
706 * space (the size is fixed and cannot be modified). The function does not
707 * handle overlapping with other memory spaces, it is the programer's
708 * responsibility to ensure that overlapping does not occur.
709 * When two memory spaces overlap, the MV's behavior is not defined.
712 * internalRegBase - new base address for the internal registers memory
719 * true on success, false on failure
721 *******************************************************************************/
722 /********************************************************************
723 * memoryMapInternalRegistersSpace - Sets new base address for the internals
726 * INPUTS: unsigned int internalRegBase - The new base address.
727 * RETURNS: true on success, false on failure
728 *********************************************************************/
729 bool memoryMapInternalRegistersSpace (unsigned int internalRegBase)
731 unsigned int currentValue;
732 unsigned int internalValue = internalRegBase;
734 internalRegBase = (internalRegBase >> 16);
735 GT_REG_READ (INTERNAL_SPACE_DECODE, ¤tValue);
736 internalRegBase = (currentValue & 0xff000000) | internalRegBase;
737 GT_REG_WRITE (INTERNAL_SPACE_DECODE, internalRegBase);
738 /* initializing also the global variable 'internalRegBaseAddr' */
739 /* gtInternalRegBaseAddr = internalValue; */
740 INTERNAL_REG_BASE_ADDR = internalValue;
744 /*******************************************************************************
745 * memoryGetInternalRegistersSpace - Returns the internal registers Base
749 * This function returns the base address of the internal registers
759 * 32 bit base address of the internal registers memory space.
761 *******************************************************************************/
762 unsigned int memoryGetInternalRegistersSpace (void)
764 unsigned int currentValue = 0;
766 GT_REG_READ (INTERNAL_SPACE_DECODE, ¤tValue);
767 return ((currentValue & 0x000fffff) << 16);
770 /*******************************************************************************
771 * gtMemoryGetInternalSramBaseAddr - Returns the integrated SRAM base address.
774 * The Atlantis incorporate integrated 2Mbit SRAM for general use. This
775 * funcnion return the SRAM's base address.
781 * 32 bit SRAM's base address.
783 *******************************************************************************/
784 unsigned int memoryGetInternalSramBaseAddr (void)
786 return ((GTREGREAD (INTEGRATED_SRAM_BASE_ADDR) & 0xfffff) << 16);
789 /*******************************************************************************
790 * gtMemorySetInternalSramBaseAddr - Set the integrated SRAM base address.
793 * The Atlantis incorporate integrated 2Mbit SRAM for general use. This
794 * function sets a new base address to the SRAM .
796 * sramBaseAddress - The SRAM's base address.
802 *******************************************************************************/
803 void gtMemorySetInternalSramBaseAddr (unsigned int sramBaseAddress)
805 GT_REG_WRITE (INTEGRATED_SRAM_BASE_ADDR, sramBaseAddress >> 16);
808 /*******************************************************************************
809 * memorySetProtectRegion - Set protection mode for one of the 8 regions.
812 * The CPU interface supports configurable access protection. This includes
813 * up to eight address ranges defined to a different protection type :
814 * whether the address range is cacheable or not, whether it is writable or
815 * not , and whether it is accessible or not. A Low and High registers
816 * define each window while the minimum address range of each window is
817 * 1Mbyte. An address driven by the CPU, in addition to the address
818 * decoding and remapping process, is compared against the eight Access
819 * Protection Low/High registers , if an address matches one of the windows
820 * , the MV device checks the transaction type against the protection bits
821 * defined in CPU Access Protection register, to determine if the access is
822 * allowed. This function set a protection mode to one of the 8 possible
825 * The CPU address windows are restricted to a size of 2 power n and the
826 * start address must be aligned to the window size. For example, if using
827 * a 16 MB window, the start address bits [23:0] must be 0.The MV's
828 * internal registers space is not protected, even if the access protection
829 * windows contain this space.
832 * region - selects which region to be configured. The values defined in
839 * memAccess - Allows or forbids access (read or write ) to the region. The
840 * values defined in gtMemory.h:
842 * - MEM_ACCESS_ALLOWED
843 * - MEM_ACCESS_FORBIDEN
845 * memWrite - CPU write protection to the region. The values defined in
848 * - MEM_WRITE_ALLOWED
849 * - MEM_WRITE_FORBIDEN
851 * cacheProtection - Defines whether caching the region is allowed or not.
852 * The values defined in gtMemory.h:
854 * - MEM_CACHE_ALLOWED
855 * - MEM_CACHE_FORBIDEN
857 * baseAddress - the region's base Address.
858 * regionSize - The region's size. This function will decrement the
859 * 'regionSize' parameter by one and then check if the size
860 * is valid. A valid size must be programed from LSB to MSB
861 * as sequence of '1's followed by sequence of '0's.
862 * To close a memory window simply set the size to 0.
865 * The size must be in 64Kbyte granularity.
866 * The base address must be aligned to the size.
872 * false for invalid size, true otherwise.
874 *******************************************************************************/
875 bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window,
876 MEMORY_ACCESS memAccess,
877 MEMORY_ACCESS_WRITE memWrite,
878 MEMORY_CACHE_PROTECT cacheProtection,
879 unsigned int baseAddress, unsigned int size)
881 unsigned int dataForReg, temp, rShift;
884 GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
888 /* The base address must be aligned to the size. */
889 if (baseAddress % size != 0) {
892 if (size >= MINIMUM_ACCESS_WIN_SIZE) {
893 baseAddress = ((baseAddress >> 16) & 0xfffff);
894 dataForReg = baseAddress | ((memAccess << 20) & BIT20) |
895 ((memWrite << 21) & BIT21) | ((cacheProtection << 22)
897 GT_REG_WRITE (CPU_PROTECT_WINDOW_0_BASE_ADDR + 0x10 * window,
900 /* Checking that the size is a sequence of '1' followed by a
901 sequence of '0' starting from LSB to MSB. */
903 for (rShift = 0; rShift < 16; rShift++) {
904 temp = temp >> rShift;
905 if ((temp & 0x1) == 0) { /* Either we got to the last '1' */
906 /* or the size is not valid */
913 GT_REG_WRITE ((CPU_PROTECT_WINDOW_0_SIZE + 0x10 * window),
920 /*******************************************************************************
921 * gtMemoryDisableProtectRegion - Disable a protected window.
924 * This function disable a protected window set by
925 * 'gtMemorySetProtectRegion' function.
928 * window - one of the 4 windows ( defined in gtMemory.h ).
936 *******************************************************************************/
937 void memoryDisableProtectRegion (MEMORY_PROTECT_WINDOW window)
939 RESET_REG_BITS (((CPU_PROTECT_WINDOW_0_BASE_ADDR) + (0x10 * window)),
943 /*******************************************************************************
944 * memorySetPciRemapValue - Set a remap value to a PCI memory space target.
947 * In addition to the address decoding mechanism, the CPU has an address
948 * remapping mechanism to be used by every PCI decoding window. Each PCI
949 * window can be remaped to a desired address target according to the remap
950 * value within the remap register. The address remapping is useful when a
951 * CPU address range must be reallocated to a different location on the
952 * PCI bus. Also, it enables CPU access to a PCI agent located above the
953 * 4Gbyte space. On system boot, each of the PCI memory spaces is maped to
954 * a defualt value (see CPU interface section in the MV spec for the
955 * default values). The remap mechanism does not always produce the desired
956 * address on the PCI bus because of the remap mechanism way of working
957 * (to fully understand why, please see the 'Address Remapping' section in
958 * the MV's spec). Therefor, this function sets a desired remap value to
959 * one of the PCI memory windows and return the effective address that
960 * should be used when exiting the PCI memory window. You should ALWAYS use
961 * the returned value by this function when remapping a PCI window and
962 * exiting it. If for example the base address of PCI0 memory 0 is
963 * 0x90000000, the size is 0x03ffffff and the remap value is 0x11000000,
964 * the function will return the value of 0x91000000 that MUST
965 * be used to exit this memory window in order to achive the deisred
969 * memoryWindow - One of the PCI memory windows as defined in Memory.h
970 * remapValueLow - The low remap value.
971 * remapValueHigh - The high remap value.
976 * The effective base address to exit the PCI, or 0xffffffff if one of the
977 * parameters is erroneous or the effective base address is higher the top
980 *******************************************************************************/
981 unsigned int memorySetPciRemapValue (PCI_MEM_WINDOW memoryWindow,
982 unsigned int remapValueHigh,
983 unsigned int remapValueLow)
985 unsigned int pciMemWindowBaseAddrReg = 0, baseAddrValue = 0;
986 unsigned int pciMemWindowSizeReg = 0, windowSizeValue = 0;
987 unsigned int effectiveBaseAddress, remapRegLow, remapRegHigh;
989 /* Initializing the base and size variables of the PCI
991 switch (memoryWindow) {
993 pciMemWindowBaseAddrReg = PCI_0_IO_BASE_ADDR;
994 pciMemWindowSizeReg = PCI_0_IO_SIZE;
995 remapRegLow = PCI_0_IO_ADDR_REMAP;
996 remapRegHigh = PCI_0_IO_ADDR_REMAP;
999 pciMemWindowBaseAddrReg = PCI_0_MEMORY0_BASE_ADDR;
1000 pciMemWindowSizeReg = PCI_0_MEMORY0_SIZE;
1001 remapRegLow = PCI_0_MEMORY0_LOW_ADDR_REMAP;
1002 remapRegHigh = PCI_0_MEMORY0_HIGH_ADDR_REMAP;
1005 pciMemWindowBaseAddrReg = PCI_0_MEMORY1_BASE_ADDR;
1006 pciMemWindowSizeReg = PCI_0_MEMORY1_SIZE;
1007 remapRegLow = PCI_0_MEMORY1_LOW_ADDR_REMAP;
1008 remapRegHigh = PCI_0_MEMORY1_HIGH_ADDR_REMAP;
1011 pciMemWindowBaseAddrReg = PCI_0_MEMORY2_BASE_ADDR;
1012 pciMemWindowSizeReg = PCI_0_MEMORY2_SIZE;
1013 remapRegLow = PCI_0_MEMORY2_LOW_ADDR_REMAP;
1014 remapRegHigh = PCI_0_MEMORY2_HIGH_ADDR_REMAP;
1017 pciMemWindowBaseAddrReg = PCI_0_MEMORY3_BASE_ADDR;
1018 pciMemWindowSizeReg = PCI_0_MEMORY3_SIZE;
1019 remapRegLow = PCI_0_MEMORY3_LOW_ADDR_REMAP;
1020 remapRegHigh = PCI_0_MEMORY3_HIGH_ADDR_REMAP;
1022 #ifdef INCLUDE_PCI_1
1024 pciMemWindowBaseAddrReg = PCI_1_IO_BASE_ADDR;
1025 pciMemWindowSizeReg = PCI_1_IO_SIZE;
1026 remapRegLow = PCI_1_IO_ADDR_REMAP;
1027 remapRegHigh = PCI_1_IO_ADDR_REMAP;
1030 pciMemWindowBaseAddrReg = PCI_1_MEMORY0_BASE_ADDR;
1031 pciMemWindowSizeReg = PCI_1_MEMORY0_SIZE;
1032 remapRegLow = PCI_1_MEMORY0_LOW_ADDR_REMAP;
1033 remapRegHigh = PCI_1_MEMORY0_HIGH_ADDR_REMAP;
1036 pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
1037 pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
1038 remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
1039 remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
1042 pciMemWindowBaseAddrReg = PCI_1_MEMORY1_BASE_ADDR;
1043 pciMemWindowSizeReg = PCI_1_MEMORY1_SIZE;
1044 remapRegLow = PCI_1_MEMORY1_LOW_ADDR_REMAP;
1045 remapRegHigh = PCI_1_MEMORY1_HIGH_ADDR_REMAP;
1048 pciMemWindowBaseAddrReg = PCI_1_MEMORY3_BASE_ADDR;
1049 pciMemWindowSizeReg = PCI_1_MEMORY3_SIZE;
1050 remapRegLow = PCI_1_MEMORY3_LOW_ADDR_REMAP;
1051 remapRegHigh = PCI_1_MEMORY3_HIGH_ADDR_REMAP;
1053 #endif /* INCLUDE_PCI_1 */
1055 /* Retrun an invalid effective base address */
1058 /* Writing the remap value to the remap regisers */
1059 GT_REG_WRITE (remapRegHigh, remapValueHigh);
1060 GT_REG_WRITE (remapRegLow, remapValueLow >> 16);
1061 /* Reading the values from the base address and size registers */
1062 baseAddrValue = GTREGREAD (pciMemWindowBaseAddrReg) & 0xfffff;
1063 windowSizeValue = GTREGREAD (pciMemWindowSizeReg) & 0xffff;
1064 /* Start calculating the effective Base Address */
1065 effectiveBaseAddress = baseAddrValue << 16;
1066 /* The effective base address will be combined from the chopped (if any)
1067 remap value (according to the size value and remap mechanism) and the
1068 window's base address */
1069 effectiveBaseAddress |=
1070 (((windowSizeValue << 16) | 0xffff) & remapValueLow);
1071 /* If the effectiveBaseAddress exceed the window boundaries return an
1073 if (effectiveBaseAddress >
1074 ((baseAddrValue << 16) + ((windowSizeValue << 16) | 0xffff)))
1076 return effectiveBaseAddress;
1079 /********************************************************************
1080 * memorySetRegionSnoopMode - This function modifys one of the 4 regions which
1081 * supports Cache Coherency.
1084 * Inputs: SNOOP_REGION region - One of the four regions.
1085 * SNOOP_TYPE snoopType - There is four optional Types:
1087 * 2. Snoop to WT region.
1088 * 3. Snoop to WB region.
1089 * 4. Snoop & Invalidate to WB region.
1090 * unsigned int baseAddress - Base Address of this region.
1091 * unsigned int topAddress - Top Address of this region.
1092 * Returns: false if one of the parameters is wrong and true else
1093 *********************************************************************/
1096 bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
1097 MEMORY_SNOOP_TYPE snoopType,
1098 unsigned int baseAddress,
1099 unsigned int regionLength)
1101 unsigned int snoopXbaseAddress;
1102 unsigned int snoopXtopAddress;
1104 unsigned int snoopHigh = baseAddress + regionLength;
1106 if( (region > MEM_SNOOP_REGION3) || (snoopType > MEM_SNOOP_WB) )
1108 snoopXbaseAddress = SNOOP_BASE_ADDRESS_0 + 0x10 * region;
1109 snoopXtopAddress = SNOOP_TOP_ADDRESS_0 + 0x10 * region;
1110 if(regionLength == 0) /* closing the region */
1112 GT_REG_WRITE(snoopXbaseAddress,0x0000ffff);
1113 GT_REG_WRITE(snoopXtopAddress,0);
1116 baseAddress = baseAddress & 0xffff0000;
1117 data = (baseAddress >> 16) | snoopType << 16;
1118 GT_REG_WRITE(snoopXbaseAddress,data);
1119 snoopHigh = (snoopHigh & 0xfff00000) >> 20;
1120 GT_REG_WRITE(snoopXtopAddress,snoopHigh - 1);
1125 /********************************************************************
1126 * memoryRemapAddress - This fubction used for address remapping.
1129 * Inputs: regOffset: remap register
1131 * Returns: false if one of the parameters is erroneous,true otherwise.
1133 * Not needed function To_do !!!!
1134 *********************************************************************/
1135 bool memoryRemapAddress (unsigned int remapReg, unsigned int remapValue)
1137 unsigned int valueForReg;
1139 valueForReg = (remapValue & 0xfff00000) >> 20;
1140 GT_REG_WRITE (remapReg, valueForReg);
1144 /*******************************************************************************
1145 * memoryGetDeviceParam - Extract the device parameters from the device bank
1146 * parameters register.
1149 * To allow interfacing with very slow devices and fast synchronous SRAMs,
1150 * each device can be programed to different timing parameters. Each bank
1151 * has its own parameters register. Bank width can be programmed to 8, 16,
1152 * or 32-bits. Bank timing parameters can be programmed to support
1153 * different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
1154 * Controllers). The MV allows you to set timing parameters and width for
1155 * each device through parameters register .
1156 * This function extracts the parameters described from the Device Bank
1157 * parameters register and fills the given 'deviceParam' (defined in
1158 * gtMemory.h) structure with the read data.
1161 * deviceParam - pointer to a structure DEVICE_PARAM (defined in
1162 * Memory.h).For details about each structure field please
1163 * see the device timing parameter section in the MV
1165 * deviceNum - Select on of the five device banks (defined in
1177 * false if one of the parameters is erroneous,true otherwise.
1179 *******************************************************************************/
1180 /********************************************************************
1181 * memoryGetDeviceParam - This function used for getting device parameters from
1182 * DEVICE BANK PARAMETERS REGISTER
1185 * Inputs: - deviceParam: STRUCT with paramiters for DEVICE BANK
1186 * PARAMETERS REGISTER
1187 * - deviceNum : number of device
1188 * Returns: false if one of the parameters is erroneous,true otherwise.
1189 *********************************************************************/
1191 bool memoryGetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
1193 unsigned int valueOfReg;
1194 unsigned int calcData;
1198 GT_REG_READ (DEVICE_BANK0PARAMETERS + 4 * deviceNum, &valueOfReg);
1199 calcData = (0x7 & valueOfReg) + ((BIT22 & valueOfReg) >> 19);
1200 deviceParam->turnOff = calcData; /* Turn Off */
1202 calcData = ((0x78 & valueOfReg) >> 3) + ((BIT23 & valueOfReg) >> 19);
1203 deviceParam->acc2First = calcData; /* Access To First */
1205 calcData = ((0x780 & valueOfReg) >> 7) + ((BIT24 & valueOfReg) >> 20);
1206 deviceParam->acc2Next = calcData; /* Access To Next */
1209 ((0x3800 & valueOfReg) >> 11) + ((BIT25 & valueOfReg) >> 22);
1210 deviceParam->ale2Wr = calcData; /* Ale To Write */
1212 calcData = ((0x1c000 & valueOfReg) >> 14) +
1213 ((BIT26 & valueOfReg) >> 23);
1214 deviceParam->wrLow = calcData; /* Write Active */
1216 calcData = ((0xe0000 & valueOfReg) >> 17) +
1217 ((BIT27 & valueOfReg) >> 24);
1218 deviceParam->wrHigh = calcData; /* Write High */
1220 calcData = ((0x300000 & valueOfReg) >> 20);
1221 deviceParam->deviceWidth = (BIT0 << calcData); /* In bytes */
1222 calcData = ((0x30000000 & valueOfReg) >> 28);
1223 deviceParam->badrSkew = calcData; /* Cycles gap between BAdr
1224 toggle to read data sample. */
1225 calcData = ((0x40000000 & valueOfReg) >> 30);
1226 deviceParam->DPEn = calcData; /* Data Parity enable */
1230 /*******************************************************************************
1231 * memorySetDeviceParam - Set new parameters for a device.
1235 * To allow interfacing with very slow devices and fast synchronous SRAMs,
1236 * each device can be programed to different timing parameters. Each bank
1237 * has its own parameters register. Bank width can be programmed to 8, 16,
1238 * or 32-bits. Bank timing parameters can be programmed to support
1239 * different device types (e.g. Sync Burst SRAM, Flash , ROM, I/O
1240 * Controllers). The MV allows you to set timing parameters and width for
1241 * each device through parameters register. This function set new
1242 * parameters to a device Bank from the delivered structure 'deviceParam'
1243 * (defined in gtMemory.h). The structure must be initialized with data
1244 * prior to the use of these function.
1247 * deviceParam - pointer to a structure DEVICE_PARAM (defined in
1248 * Memory.h).For details about each structure field please
1249 * see the device timing parameter section in the MV
1251 * deviceNum - Select on of the five device banks (defined in
1263 * false if one of the parameters is erroneous,true otherwise.
1265 *******************************************************************************/
1266 /********************************************************************
1267 * memorySetDeviceParam - This function used for setting device parameters to
1268 * DEVICE BANK PARAMETERS REGISTER
1271 * Inputs: - deviceParam: STRUCT for store paramiters from DEVICE BANK
1272 * PARAMETERS REGISTER
1273 * - deviceNum : number of device
1274 * Returns: false if one of the parameters is erroneous,true otherwise.
1275 *********************************************************************/
1276 bool memorySetDeviceParam (DEVICE_PARAM * deviceParam, DEVICE deviceNum)
1278 unsigned int valueForReg;
1280 if ((deviceParam->turnOff > 0x7) || (deviceParam->acc2First > 0xf) ||
1281 (deviceParam->acc2Next > 0xf) || (deviceParam->ale2Wr > 0x7) ||
1282 (deviceParam->wrLow > 0x7) || (deviceParam->wrHigh > 0x7) ||
1283 (deviceParam->badrSkew > 0x2) || (deviceParam->DPEn > 0x1)) {
1286 valueForReg = (((deviceParam->turnOff) & 0x7) |
1287 (((deviceParam->turnOff) & 0x8) << 19) |
1288 (((deviceParam->acc2First) & 0xf) << 3) |
1289 (((deviceParam->acc2First) & 0x10) << 19) |
1290 (((deviceParam->acc2Next) & 0xf) << 7) |
1291 (((deviceParam->acc2Next) & 0x10) << 20) |
1292 (((deviceParam->ale2Wr) & 0x7) << 11) |
1293 (((deviceParam->ale2Wr) & 0xf) << 22) |
1294 (((deviceParam->wrLow) & 0x7) << 14) |
1295 (((deviceParam->wrLow) & 0xf) << 23) |
1296 (((deviceParam->wrHigh) & 0x7) << 17) |
1297 (((deviceParam->wrHigh) & 0xf) << 24) |
1298 (((deviceParam->badrSkew) & 0x3) << 28) |
1299 (((deviceParam->DPEn) & 0x1) << 30));
1301 /* insert the device width: */
1302 switch (deviceParam->deviceWidth) {
1304 valueForReg = valueForReg | _8BIT;
1307 valueForReg = valueForReg | _16BIT;
1310 valueForReg = valueForReg | _32BIT;
1313 valueForReg = valueForReg | _8BIT;
1316 GT_REG_WRITE (DEVICE_BANK0PARAMETERS + 4 * deviceNum, valueForReg);
1320 /*******************************************************************************
1321 * MemoryDisableWindow - Disable a memory space by the disable bit.
1323 * This function disables one of the 21 availiable windows dedicated for
1324 * the CPU decoding mechanism. Its possible to combine several windows with
1327 * window - One or more of the memory windows (defined in gtMemory.h).
1332 *******************************************************************************/
1333 void MemoryDisableWindow (MEMORY_WINDOW window)
1335 SET_REG_BITS (BASE_ADDR_ENABLE, window);
1338 /*******************************************************************************
1339 * MemoryEnableWindow - Enable a memory space that was disabled by
1340 * 'MemoryDisableWindow'.
1342 * This function enables one of the 21 availiable windows dedicated for the
1343 * CPU decoding mechanism. Its possible to combine several windows with the
1346 * window - One or more of the memory windows (defined in gtMemory.h).
1351 *******************************************************************************/
1352 void MemoryEnableWindow (MEMORY_WINDOW window)
1354 RESET_REG_BITS (BASE_ADDR_ENABLE, window);
1357 /*******************************************************************************
1358 * MemoryGetMemWindowStatus - This function check whether the memory window is
1361 * This function checks if the given memory window is closed .
1363 * window - One or more of the memory windows (defined in gtMemory.h).
1367 * true for a closed window, false otherwise .
1368 *******************************************************************************/
1369 MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window)
1371 if (GTREGREAD (BASE_ADDR_ENABLE) & window)
1372 return MEM_WINDOW_DISABLED;
1373 return MEM_WINDOW_ENABLED;