2 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
15 #include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
17 DECLARE_GLOBAL_DATA_PTR;
19 #define ETH_PHY_CTRL_REG 0
20 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11
21 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
24 * Those values and defines are taken from the Marvell U-Boot version
25 * "u-boot-2013.01-2014_T3.0"
27 #define DB_GP_88F68XX_GPP_OUT_ENA_LOW \
28 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
29 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
30 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
31 #define DB_GP_88F68XX_GPP_OUT_ENA_MID \
32 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
33 BIT(16) | BIT(17) | BIT(18)))
35 #define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
36 #define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0
37 #define DB_GP_88F68XX_GPP_POL_LOW 0x0
38 #define DB_GP_88F68XX_GPP_POL_MID 0x0
40 /* IO expander on Marvell GP board includes e.g. fan enabling */
41 struct marvell_io_exp {
47 static struct marvell_io_exp io_exp[] = {
48 { 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
49 { 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
50 { 0x20, 2, 0x1D }, /* Output Data, register#0 */
51 { 0x20, 3, 0x18 }, /* Output Data, register#1 */
52 { 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
53 { 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */
54 { 0x21, 2, 0x08 }, /* Output Data, register#0 */
55 { 0x21, 3, 0xC0 } /* Output Data, register#1 */
59 * Define the DDR layout / topology here in the board file. This will
60 * be used by the DDR3 init code in the SPL U-Boot version to configure
61 * the DDR3 controller.
63 static struct hws_topology_map board_topology_map = {
64 0x1, /* active interfaces */
65 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
71 SPEED_BIN_DDR_1866L, /* speed_bin */
72 BUS_WIDTH_8, /* memory_width */
73 MEM_4G, /* mem_size */
74 DDR_FREQ_800, /* frequency */
75 0, 0, /* cas_l cas_wl */
76 HWS_TEMP_LOW} }, /* temperature */
77 5, /* Num Of Bus Per Interface*/
78 BUS_MASK_32BIT /* Busses mask */
81 struct hws_topology_map *ddr3_get_topology_map(void)
83 /* Return the board topology as defined in the board code */
84 return &board_topology_map;
87 int board_early_init_f(void)
90 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
91 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
92 writel(0x11244011, MVEBU_MPP_BASE + 0x08);
93 writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
94 writel(0x22200002, MVEBU_MPP_BASE + 0x10);
95 writel(0x30042022, MVEBU_MPP_BASE + 0x14);
96 writel(0x55550555, MVEBU_MPP_BASE + 0x18);
97 writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
99 /* Set GPP Out value */
100 writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
101 writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
103 /* Set GPP Polarity */
104 writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
105 writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
107 /* Set GPP Out Enable */
108 writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
109 writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
118 /* adress of boot parameters */
119 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
121 /* Init I2C IO expanders */
122 for (i = 0; i < ARRAY_SIZE(io_exp); i++)
123 i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
130 puts("Board: Marvell DB-88F6820-GP\n");
135 int board_eth_init(bd_t *bis)
137 cpu_eth_init(bis); /* Built in controller(s) come first */
138 return pci_eth_init(bis);