3 * Ingo Assmus <ingo.assmus@keymile.com>
5 * based on - Driver for MV64360X ethernet ports
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * mv_eth.c - header file for the polled mode GT ethernet driver
36 /* enable Debug outputs */
47 #undef MV64360_CHECKSUM_OFFLOAD
48 /*************************************************************************
49 **************************************************************************
50 **************************************************************************
51 * The first part is the high level driver of the gigE ethernet ports. *
52 **************************************************************************
53 **************************************************************************
54 *************************************************************************/
56 /* Definition for configuring driver */
57 /* #define UPDATE_STATS_BY_SOFTWARE */
58 #undef MV64360_RX_QUEUE_FILL_ON_TASK
62 #define MAGIC_ETH_RUNNING 8031971
63 #define MV64360_INTERNAL_SRAM_SIZE _256K
64 #define EXTRA_BYTES 32
65 #define WRAP ETH_HLEN + 2 + 4 + 16
66 #define BUFFER_MTU dev->mtu + WRAP
67 #define INT_CAUSE_UNMASK_ALL 0x0007ffff
68 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
69 #ifdef MV64360_RX_FILL_ON_TASK
70 #define INT_CAUSE_MASK_ALL 0x00000000
71 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
72 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
75 /* Read/Write to/from MV64360 internal registers */
76 #define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset))
77 #define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data)
78 #define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits)))
79 #define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits)))
81 /* Static function declarations */
82 static int mv64360_eth_real_open (struct eth_device *eth);
83 static int mv64360_eth_real_stop (struct eth_device *eth);
84 static struct net_device_stats *mv64360_eth_get_stats (struct eth_device
86 static void eth_port_init_mac_tables (ETH_PORT eth_port_num);
87 static void mv64360_eth_update_stat (struct eth_device *dev);
88 bool db64360_eth_start (struct eth_device *eth);
89 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
90 unsigned int mib_offset);
91 int mv64360_eth_receive (struct eth_device *dev);
93 int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length);
95 #ifndef UPDATE_STATS_BY_SOFTWARE
96 static void mv64360_eth_print_stat (struct eth_device *dev);
99 extern unsigned int INTERNAL_REG_BASE_ADDR;
101 /*************************************************
102 *Helper functions - used inside the driver only *
103 *************************************************/
105 void print_globals (struct eth_device *dev)
107 printf ("Ethernet PRINT_Globals-Debug function\n");
108 printf ("Base Address for ETH_PORT_INFO: %08x\n",
109 (unsigned int) dev->priv);
110 printf ("Base Address for mv64360_eth_priv: %08x\n",
111 (unsigned int) &(((ETH_PORT_INFO *) dev->priv)->
114 printf ("GT Internal Base Address: %08x\n",
115 INTERNAL_REG_BASE_ADDR);
116 printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE);
117 printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE);
118 printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n",
119 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
121 (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32);
122 printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n",
123 (unsigned int) ((ETH_PORT_INFO *) dev->priv)->
125 (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32);
129 #define my_cpu_to_le32(x) my_le32_to_cpu((x))
131 unsigned long my_le32_to_cpu (unsigned long x)
133 return (((x & 0x000000ffU) << 24) |
134 ((x & 0x0000ff00U) << 8) |
135 ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24));
139 /**********************************************************************
140 * mv64360_eth_print_phy_status
142 * Prints gigabit ethenret phy status
144 * Input : pointer to ethernet interface network device structure
146 **********************************************************************/
148 static void mv64360_eth_print_phy_status (struct eth_device *dev)
150 struct mv64360_eth_priv *port_private;
151 unsigned int port_num;
152 ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv;
153 unsigned int port_status, phy_reg_data;
156 (struct mv64360_eth_priv *) ethernet_private->port_private;
157 port_num = port_private->port_num;
159 /* Check Link status on phy */
160 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
161 if (!(phy_reg_data & 0x20)) {
162 printf ("Ethernet port changed link status to DOWN\n");
165 MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
166 printf ("Ethernet status port %d: Link up", port_num);
168 (port_status & BIT2) ? "Full Duplex" : "Half Duplex");
169 if (port_status & BIT4)
170 printf (", Speed 1 Gbps");
173 (port_status & BIT5) ? "Speed 100 Mbps" :
179 /**********************************************************************
180 * u-boot entry functions for mv64360_eth
182 **********************************************************************/
183 int db64360_eth_probe (struct eth_device *dev)
185 return ((int) db64360_eth_start (dev));
188 int db64360_eth_poll (struct eth_device *dev)
190 return mv64360_eth_receive (dev);
193 int db64360_eth_transmit(struct eth_device *dev, void *packet, int length)
195 mv64360_eth_xmit (dev, packet, length);
199 void db64360_eth_disable (struct eth_device *dev)
201 mv64360_eth_stop (dev);
205 void mv6436x_eth_initialize (bd_t * bis)
207 struct eth_device *dev;
208 ETH_PORT_INFO *ethernet_private;
209 struct mv64360_eth_priv *port_private;
211 char *s, *e, buf[64];
213 for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) {
214 dev = calloc (sizeof (*dev), 1);
216 printf ("%s: mv_enet%d allocation failure, %s\n",
217 __FUNCTION__, devnum, "eth_device structure");
221 /* must be less than sizeof(dev->name) */
222 sprintf (dev->name, "mv_enet%d", devnum);
225 printf ("Initializing %s\n", dev->name);
228 /* Extract the MAC address from the environment */
242 default: /* this should never happen */
243 printf ("%s: Invalid device number %d\n",
244 __FUNCTION__, devnum);
248 temp = getenv_f(s, buf, sizeof (buf));
249 s = (temp > 0) ? buf : NULL;
252 printf ("Setting MAC %d to %s\n", devnum, s);
254 for (x = 0; x < 6; ++x) {
255 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
257 s = (*e) ? e + 1 : e;
259 /* ronen - set the MAC addr in the HW */
260 eth_port_uc_addr_set (devnum, dev->enetaddr, 0);
262 dev->init = (void *) db64360_eth_probe;
263 dev->halt = (void *) ethernet_phy_reset;
264 dev->send = (void *) db64360_eth_transmit;
265 dev->recv = (void *) db64360_eth_poll;
267 ethernet_private = calloc (sizeof (*ethernet_private), 1);
268 dev->priv = (void *) ethernet_private;
270 if (!ethernet_private) {
271 printf ("%s: %s allocation failure, %s\n",
272 __FUNCTION__, dev->name,
273 "Private Device Structure");
277 /* start with an zeroed ETH_PORT_INFO */
278 memset (ethernet_private, 0, sizeof (ETH_PORT_INFO));
279 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
281 /* set pointer to memory for stats data structure etc... */
282 port_private = calloc (sizeof (*ethernet_private), 1);
283 ethernet_private->port_private = (void *)port_private;
285 printf ("%s: %s allocation failure, %s\n",
286 __FUNCTION__, dev->name,
287 "Port Private Device Structure");
289 free (ethernet_private);
294 port_private->stats =
295 calloc (sizeof (struct net_device_stats), 1);
296 if (!port_private->stats) {
297 printf ("%s: %s allocation failure, %s\n",
298 __FUNCTION__, dev->name,
299 "Net stat Structure");
302 free (ethernet_private);
306 memset (ethernet_private->port_private, 0,
307 sizeof (struct mv64360_eth_priv));
310 ethernet_private->port_num = ETH_0;
313 ethernet_private->port_num = ETH_1;
316 ethernet_private->port_num = ETH_2;
319 printf ("Invalid device number %d\n", devnum);
323 port_private->port_num = devnum;
325 * Read MIB counter on the GT in order to reset them,
326 * then zero all the stats fields in memory
328 mv64360_eth_update_stat (dev);
329 memset (port_private->stats, 0,
330 sizeof (struct net_device_stats));
331 /* Extract the MAC address from the environment */
345 default: /* this should never happen */
346 printf ("%s: Invalid device number %d\n",
347 __FUNCTION__, devnum);
351 temp = getenv_f(s, buf, sizeof (buf));
352 s = (temp > 0) ? buf : NULL;
355 printf ("Setting MAC %d to %s\n", devnum, s);
357 for (x = 0; x < 6; ++x) {
358 dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0;
360 s = (*e) ? e + 1 : e;
363 DP (printf ("Allocating descriptor and buffer rings\n"));
365 ethernet_private->p_rx_desc_area_base[0] =
366 (ETH_RX_DESC *) memalign (16,
367 RX_DESC_ALIGNED_SIZE *
368 MV64360_RX_QUEUE_SIZE + 1);
369 ethernet_private->p_tx_desc_area_base[0] =
370 (ETH_TX_DESC *) memalign (16,
371 TX_DESC_ALIGNED_SIZE *
372 MV64360_TX_QUEUE_SIZE + 1);
374 ethernet_private->p_rx_buffer_base[0] =
375 (char *) memalign (16,
376 MV64360_RX_QUEUE_SIZE *
377 MV64360_TX_BUFFER_SIZE + 1);
378 ethernet_private->p_tx_buffer_base[0] =
379 (char *) memalign (16,
380 MV64360_RX_QUEUE_SIZE *
381 MV64360_TX_BUFFER_SIZE + 1);
384 /* DEBUG OUTPUT prints adresses of globals */
390 DP (printf ("%s: exit\n", __FUNCTION__));
394 /**********************************************************************
397 * This function is called when openning the network device. The function
398 * should initialize all the hardware, initialize cyclic Rx/Tx
399 * descriptors chain and buffers and allocate an IRQ to the network
402 * Input : a pointer to the network device structure
403 * / / ronen - changed the output to match net/eth.c needs
404 * Output : nonzero of success , zero if fails.
406 **********************************************************************/
408 int mv64360_eth_open (struct eth_device *dev)
410 return (mv64360_eth_real_open (dev));
413 /* Helper function for mv64360_eth_open */
414 static int mv64360_eth_real_open (struct eth_device *dev)
418 ETH_PORT_INFO *ethernet_private;
419 struct mv64360_eth_priv *port_private;
420 unsigned int port_num;
423 ethernet_private = (ETH_PORT_INFO *) dev->priv;
424 /* ronen - when we update the MAC env params we only update dev->enetaddr
425 see ./net/eth.c eth_set_enetaddr() */
426 memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6);
429 (struct mv64360_eth_priv *) ethernet_private->port_private;
430 port_num = port_private->port_num;
433 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
436 /* Clear the ethernet port interrupts */
437 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
438 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
440 /* Unmask RX buffer and TX end interrupt */
441 MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num),
442 INT_CAUSE_UNMASK_ALL);
444 /* Unmask phy and link status changes interrupts */
445 MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num),
446 INT_CAUSE_UNMASK_ALL_EXT);
448 /* Set phy address of the port */
449 ethernet_private->port_phy_addr = 0x8 + port_num;
451 /* Activate the DMA channels etc */
452 eth_port_init (ethernet_private);
455 /* "Allocate" setup TX rings */
457 for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
460 port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE;
461 size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */
462 ethernet_private->tx_desc_area_size[queue] = size;
464 /* first clear desc area completely */
465 memset ((void *) ethernet_private->p_tx_desc_area_base[queue],
466 0, ethernet_private->tx_desc_area_size[queue]);
468 /* initialize tx desc ring with low level driver */
469 if (ether_init_tx_desc_ring
470 (ethernet_private, ETH_Q0,
471 port_private->tx_ring_size[queue],
472 MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
473 (unsigned int) ethernet_private->
474 p_tx_desc_area_base[queue],
475 (unsigned int) ethernet_private->
476 p_tx_buffer_base[queue]) == false)
477 printf ("### Error initializing TX Ring\n");
480 /* "Allocate" setup RX rings */
481 for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
484 /* Meantime RX Ring are fixed - but must be configurable by user */
485 port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE;
486 size = (port_private->rx_ring_size[queue] *
487 RX_DESC_ALIGNED_SIZE);
488 ethernet_private->rx_desc_area_size[queue] = size;
490 /* first clear desc area completely */
491 memset ((void *) ethernet_private->p_rx_desc_area_base[queue],
492 0, ethernet_private->rx_desc_area_size[queue]);
493 if ((ether_init_rx_desc_ring
494 (ethernet_private, ETH_Q0,
495 port_private->rx_ring_size[queue],
496 MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ ,
497 (unsigned int) ethernet_private->
498 p_rx_desc_area_base[queue],
499 (unsigned int) ethernet_private->
500 p_rx_buffer_base[queue])) == false)
501 printf ("### Error initializing RX Ring\n");
504 eth_port_start (ethernet_private);
506 /* Set maximum receive buffer to 9700 bytes */
507 MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num),
510 (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num))
514 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
515 * disable the leaky bucket mechanism .
518 MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0);
519 MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num));
521 /* Check Link status on phy */
522 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
523 if (!(phy_reg_data & 0x20)) {
525 if ((ethernet_phy_reset (port_num)) != true) {
526 printf ("$$ Warnning: No link on port %d \n",
530 eth_port_read_smi_reg (port_num, 1, &phy_reg_data);
531 if (!(phy_reg_data & 0x20)) {
532 printf ("### Error: Phy is not active\n");
537 mv64360_eth_print_phy_status (dev);
539 port_private->eth_running = MAGIC_ETH_RUNNING;
544 static int mv64360_eth_free_tx_rings (struct eth_device *dev)
547 ETH_PORT_INFO *ethernet_private;
548 struct mv64360_eth_priv *port_private;
549 unsigned int port_num;
550 volatile ETH_TX_DESC *p_tx_curr_desc;
552 ethernet_private = (ETH_PORT_INFO *) dev->priv;
554 (struct mv64360_eth_priv *) ethernet_private->port_private;
555 port_num = port_private->port_num;
558 MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num),
562 DP (printf ("Clearing previously allocated TX queues... "));
563 for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) {
564 /* Free on TX rings */
565 for (p_tx_curr_desc =
566 ethernet_private->p_tx_desc_area_base[queue];
567 ((unsigned int) p_tx_curr_desc <= (unsigned int)
568 ethernet_private->p_tx_desc_area_base[queue] +
569 ethernet_private->tx_desc_area_size[queue]);
571 (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc +
572 TX_DESC_ALIGNED_SIZE)) {
573 /* this is inside for loop */
574 if (p_tx_curr_desc->return_info != 0) {
575 p_tx_curr_desc->return_info = 0;
576 DP (printf ("freed\n"));
579 DP (printf ("Done\n"));
584 static int mv64360_eth_free_rx_rings (struct eth_device *dev)
587 ETH_PORT_INFO *ethernet_private;
588 struct mv64360_eth_priv *port_private;
589 unsigned int port_num;
590 volatile ETH_RX_DESC *p_rx_curr_desc;
592 ethernet_private = (ETH_PORT_INFO *) dev->priv;
594 (struct mv64360_eth_priv *) ethernet_private->port_private;
595 port_num = port_private->port_num;
599 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num),
603 DP (printf ("Clearing previously allocated RX queues... "));
604 for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) {
605 /* Free preallocated skb's on RX rings */
606 for (p_rx_curr_desc =
607 ethernet_private->p_rx_desc_area_base[queue];
608 (((unsigned int) p_rx_curr_desc <
609 ((unsigned int) ethernet_private->
610 p_rx_desc_area_base[queue] +
611 ethernet_private->rx_desc_area_size[queue])));
613 (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc +
614 RX_DESC_ALIGNED_SIZE)) {
615 if (p_rx_curr_desc->return_info != 0) {
616 p_rx_curr_desc->return_info = 0;
617 DP (printf ("freed\n"));
620 DP (printf ("Done\n"));
625 /**********************************************************************
628 * This function is used when closing the network device.
629 * It updates the hardware,
630 * release all memory that holds buffers and descriptors and release the IRQ.
631 * Input : a pointer to the device structure
632 * Output : zero if success , nonzero if fails
633 *********************************************************************/
635 int mv64360_eth_stop (struct eth_device *dev)
637 /* Disable all gigE address decoder */
638 MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f);
639 DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__));
640 mv64360_eth_real_stop (dev);
645 /* Helper function for mv64360_eth_stop */
647 static int mv64360_eth_real_stop (struct eth_device *dev)
649 ETH_PORT_INFO *ethernet_private;
650 struct mv64360_eth_priv *port_private;
651 unsigned int port_num;
653 ethernet_private = (ETH_PORT_INFO *) dev->priv;
655 (struct mv64360_eth_priv *) ethernet_private->port_private;
656 port_num = port_private->port_num;
659 mv64360_eth_free_tx_rings (dev);
660 mv64360_eth_free_rx_rings (dev);
662 eth_port_reset (ethernet_private->port_num);
663 /* Disable ethernet port interrupts */
664 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0);
665 MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0);
666 /* Mask RX buffer and TX end interrupt */
667 MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0);
668 /* Mask phy and link status changes interrupts */
669 MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0);
670 MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH,
672 /* Print Network statistics */
673 #ifndef UPDATE_STATS_BY_SOFTWARE
675 * Print statistics (only if ethernet is running),
676 * then zero all the stats fields in memory
678 if (port_private->eth_running == MAGIC_ETH_RUNNING) {
679 port_private->eth_running = 0;
680 mv64360_eth_print_stat (dev);
682 memset (port_private->stats, 0, sizeof (struct net_device_stats));
684 DP (printf ("\nEthernet stopped ... \n"));
689 /**********************************************************************
690 * mv64360_eth_start_xmit
692 * This function is queues a packet in the Tx descriptor for
695 * Input : skb - a pointer to socket buffer
696 * dev - a pointer to the required port
698 * Output : zero upon success
699 **********************************************************************/
701 int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr,
704 ETH_PORT_INFO *ethernet_private;
705 struct mv64360_eth_priv *port_private;
707 ETH_FUNC_RET_STATUS status;
708 struct net_device_stats *stats;
709 ETH_FUNC_RET_STATUS release_result;
711 ethernet_private = (ETH_PORT_INFO *) dev->priv;
713 (struct mv64360_eth_priv *) ethernet_private->port_private;
715 stats = port_private->stats;
717 /* Update packet info data structure */
718 pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */
719 pkt_info.byte_cnt = dataSize;
720 pkt_info.buf_ptr = (unsigned int) dataPtr;
721 pkt_info.return_info = 0;
723 status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info);
724 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) {
725 printf ("Error on transmitting packet ..");
726 if (status == ETH_QUEUE_FULL)
727 printf ("ETH Queue is full. \n");
728 if (status == ETH_QUEUE_LAST_RESOURCE)
729 printf ("ETH Queue: using last available resource. \n");
733 /* Update statistics and start of transmittion time */
734 stats->tx_bytes += dataSize;
737 /* Check if packet(s) is(are) transmitted correctly (release everything) */
740 eth_tx_return_desc (ethernet_private, ETH_Q0,
742 switch (release_result) {
744 DP (printf ("descriptor released\n"));
745 if (pkt_info.cmd_sts & BIT0) {
746 printf ("Error in TX\n");
752 DP (printf ("transmission still in process\n"));
756 printf ("routine can not access Tx desc ring\n");
760 DP (printf ("the routine has nothing to release\n"));
762 default: /* should not happen */
765 } while (release_result == ETH_OK);
768 return 0; /* success */
770 return 1; /* Failed - higher layers will free the skb */
773 /**********************************************************************
774 * mv64360_eth_receive
776 * This function is forward packets that are received from the port's
777 * queues toward kernel core or FastRoute them to another interface.
779 * Input : dev - a pointer to the required interface
780 * max - maximum number to receive (0 means unlimted)
782 * Output : number of served packets
783 **********************************************************************/
785 int mv64360_eth_receive (struct eth_device *dev)
787 ETH_PORT_INFO *ethernet_private;
788 struct mv64360_eth_priv *port_private;
790 struct net_device_stats *stats;
792 ethernet_private = (ETH_PORT_INFO *) dev->priv;
794 (struct mv64360_eth_priv *) ethernet_private->port_private;
795 stats = port_private->stats;
797 while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) ==
801 if (pkt_info.byte_cnt != 0) {
802 printf ("%s: Received %d byte Packet @ 0x%x\n",
803 __FUNCTION__, pkt_info.byte_cnt,
807 /* Update statistics. Note byte count includes 4 byte CRC count */
809 stats->rx_bytes += pkt_info.byte_cnt;
812 * In case received a packet without first / last bits on OR the error
813 * summary bit is on, the packets needs to be dropeed.
816 cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
817 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
818 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
821 printf ("Received packet spread on multiple descriptors\n");
823 /* Is this caused by an error ? */
824 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) {
828 /* free these descriptors again without forwarding them to the higher layers */
829 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
830 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
832 if (eth_rx_return_buff
833 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
834 printf ("Error while returning the RX Desc to Ring\n");
836 DP (printf ("RX Desc returned to Ring\n"));
838 /* /free these descriptors again */
841 /* !!! call higher layer processing */
843 printf ("\nNow send it to upper layer protocols (NetReceive) ...\n");
845 /* let the upper layer handle the packet */
846 NetReceive ((uchar *) pkt_info.buf_ptr,
847 (int) pkt_info.byte_cnt);
849 /* **************************************************************** */
850 /* free descriptor */
851 pkt_info.buf_ptr &= ~0x7; /* realign buffer again */
852 pkt_info.byte_cnt = 0x0000; /* Reset Byte count */
854 ("RX: pkt_info.buf_ptr = %x\n",
856 if (eth_rx_return_buff
857 (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) {
858 printf ("Error while returning the RX Desc to Ring\n");
860 DP (printf ("RX Desc returned to Ring\n"));
863 /* **************************************************************** */
867 mv64360_eth_get_stats (dev); /* update statistics */
871 /**********************************************************************
872 * mv64360_eth_get_stats
874 * Returns a pointer to the interface statistics.
876 * Input : dev - a pointer to the required interface
878 * Output : a pointer to the interface's statistics
879 **********************************************************************/
881 static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev)
883 ETH_PORT_INFO *ethernet_private;
884 struct mv64360_eth_priv *port_private;
886 ethernet_private = (ETH_PORT_INFO *) dev->priv;
888 (struct mv64360_eth_priv *) ethernet_private->port_private;
890 mv64360_eth_update_stat (dev);
892 return port_private->stats;
896 /**********************************************************************
897 * mv64360_eth_update_stat
899 * Update the statistics structure in the private data structure
901 * Input : pointer to ethernet interface network device structure
903 **********************************************************************/
905 static void mv64360_eth_update_stat (struct eth_device *dev)
907 ETH_PORT_INFO *ethernet_private;
908 struct mv64360_eth_priv *port_private;
909 struct net_device_stats *stats;
911 ethernet_private = (ETH_PORT_INFO *) dev->priv;
913 (struct mv64360_eth_priv *) ethernet_private->port_private;
914 stats = port_private->stats;
916 /* These are false updates */
917 stats->rx_packets += (unsigned long)
918 eth_read_mib_counter (ethernet_private->port_num,
919 ETH_MIB_GOOD_FRAMES_RECEIVED);
920 stats->tx_packets += (unsigned long)
921 eth_read_mib_counter (ethernet_private->port_num,
922 ETH_MIB_GOOD_FRAMES_SENT);
923 stats->rx_bytes += (unsigned long)
924 eth_read_mib_counter (ethernet_private->port_num,
925 ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
927 * Ideally this should be as follows -
929 * stats->rx_bytes += stats->rx_bytes +
930 * ((unsigned long) ethReadMibCounter (ethernet_private->port_num ,
931 * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32);
933 * But the unsigned long in PowerPC and MIPS are 32bit. So the next read
934 * is just a dummy read for proper work of the GigE port
936 eth_read_mib_counter (ethernet_private->port_num,
937 ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH);
938 stats->tx_bytes += (unsigned long)
939 eth_read_mib_counter (ethernet_private->port_num,
940 ETH_MIB_GOOD_OCTETS_SENT_LOW);
941 eth_read_mib_counter (ethernet_private->port_num,
942 ETH_MIB_GOOD_OCTETS_SENT_HIGH);
943 stats->rx_errors += (unsigned long)
944 eth_read_mib_counter (ethernet_private->port_num,
945 ETH_MIB_MAC_RECEIVE_ERROR);
947 /* Rx dropped is for received packet with CRC error */
949 (unsigned long) eth_read_mib_counter (ethernet_private->
951 ETH_MIB_BAD_CRC_EVENT);
952 stats->multicast += (unsigned long)
953 eth_read_mib_counter (ethernet_private->port_num,
954 ETH_MIB_MULTICAST_FRAMES_RECEIVED);
956 (unsigned long) eth_read_mib_counter (ethernet_private->
959 (unsigned long) eth_read_mib_counter (ethernet_private->
961 ETH_MIB_LATE_COLLISION);
962 /* detailed rx errors */
963 stats->rx_length_errors +=
964 (unsigned long) eth_read_mib_counter (ethernet_private->
966 ETH_MIB_UNDERSIZE_RECEIVED)
968 (unsigned long) eth_read_mib_counter (ethernet_private->
970 ETH_MIB_OVERSIZE_RECEIVED);
971 /* detailed tx errors */
974 #ifndef UPDATE_STATS_BY_SOFTWARE
975 /**********************************************************************
976 * mv64360_eth_print_stat
978 * Update the statistics structure in the private data structure
980 * Input : pointer to ethernet interface network device structure
982 **********************************************************************/
984 static void mv64360_eth_print_stat (struct eth_device *dev)
986 ETH_PORT_INFO *ethernet_private;
987 struct mv64360_eth_priv *port_private;
988 struct net_device_stats *stats;
990 ethernet_private = (ETH_PORT_INFO *) dev->priv;
992 (struct mv64360_eth_priv *) ethernet_private->port_private;
993 stats = port_private->stats;
995 /* These are false updates */
996 printf ("\n### Network statistics: ###\n");
997 printf ("--------------------------\n");
998 printf (" Packets received: %ld\n", stats->rx_packets);
999 printf (" Packets send: %ld\n", stats->tx_packets);
1000 printf (" Received bytes: %ld\n", stats->rx_bytes);
1001 printf (" Send bytes: %ld\n", stats->tx_bytes);
1002 if (stats->rx_errors != 0)
1003 printf (" Rx Errors: %ld\n",
1005 if (stats->rx_dropped != 0)
1006 printf (" Rx dropped (CRC Errors): %ld\n",
1008 if (stats->multicast != 0)
1009 printf (" Rx mulicast frames: %ld\n",
1011 if (stats->collisions != 0)
1012 printf (" No. of collisions: %ld\n",
1014 if (stats->rx_length_errors != 0)
1015 printf (" Rx length errors: %ld\n",
1016 stats->rx_length_errors);
1020 /**************************************************************************
1021 *network_start - Network Kick Off Routine UBoot
1024 **************************************************************************/
1026 bool db64360_eth_start (struct eth_device *dev)
1028 return (mv64360_eth_open (dev)); /* calls real open */
1031 /*************************************************************************
1032 **************************************************************************
1033 **************************************************************************
1034 * The second part is the low level driver of the gigE ethernet ports. *
1035 **************************************************************************
1036 **************************************************************************
1037 *************************************************************************/
1039 * based on Linux code
1040 * arch/powerpc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports
1041 * Copyright (C) 2002 rabeeh@galileo.co.il
1043 * This program is free software; you can redistribute it and/or
1044 * modify it under the terms of the GNU General Public License
1045 * as published by the Free Software Foundation; either version 2
1046 * of the License, or (at your option) any later version.
1048 * This program is distributed in the hope that it will be useful,
1049 * but WITHOUT ANY WARRANTY; without even the implied warranty of
1050 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1051 * GNU General Public License for more details.
1053 * You should have received a copy of the GNU General Public License
1054 * along with this program; if not, write to the Free Software
1055 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
1059 /********************************************************************************
1060 * Marvell's Gigabit Ethernet controller low level driver
1063 * This file introduce low level API to Marvell's Gigabit Ethernet
1064 * controller. This Gigabit Ethernet Controller driver API controls
1065 * 1) Operations (i.e. port init, start, reset etc').
1066 * 2) Data flow (i.e. port send, receive etc').
1067 * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO
1069 * This struct includes user configuration information as well as
1070 * driver internal data needed for its operations.
1072 * Supported Features:
1073 * - This low level driver is OS independent. Allocating memory for
1074 * the descriptor rings and buffers are not within the scope of
1076 * - The user is free from Rx/Tx queue managing.
1077 * - This low level driver introduce functionality API that enable
1078 * the to operate Marvell's Gigabit Ethernet Controller in a
1080 * - Simple Gigabit Ethernet port operation API.
1081 * - Simple Gigabit Ethernet port data flow API.
1082 * - Data flow and operation API support per queue functionality.
1083 * - Support cached descriptors for better performance.
1084 * - Enable access to all four DRAM banks and internal SRAM memory
1086 * - PHY access and control API.
1087 * - Port control register configuration API.
1088 * - Full control over Unicast and Multicast MAC configurations.
1092 * Initialization phase
1093 * This phase complete the initialization of the ETH_PORT_INFO
1095 * User information regarding port configuration has to be set
1096 * prior to calling the port initialization routine. For example,
1097 * the user has to assign the port_phy_addr field which is board
1098 * depended parameter.
1099 * In this phase any port Tx/Rx activity is halted, MIB counters
1100 * are cleared, PHY address is set according to user parameter and
1101 * access to DRAM and internal SRAM memory spaces.
1103 * Driver ring initialization
1104 * Allocating memory for the descriptor rings and buffers is not
1105 * within the scope of this driver. Thus, the user is required to
1106 * allocate memory for the descriptors ring and buffers. Those
1107 * memory parameters are used by the Rx and Tx ring initialization
1108 * routines in order to curve the descriptor linked list in a form
1110 * Note: Pay special attention to alignment issues when using
1111 * cached descriptors/buffers. In this phase the driver store
1112 * information in the ETH_PORT_INFO struct regarding each queue
1116 * This phase prepares the Ethernet port for Rx and Tx activity.
1117 * It uses the information stored in the ETH_PORT_INFO struct to
1118 * initialize the various port registers.
1121 * All packet references to/from the driver are done using PKT_INFO
1123 * This struct is a unified struct used with Rx and Tx operations.
1124 * This way the user is not required to be familiar with neither
1125 * Tx nor Rx descriptors structures.
1126 * The driver's descriptors rings are management by indexes.
1127 * Those indexes controls the ring resources and used to indicate
1128 * a SW resource error:
1130 * This index points to the current available resource for use. For
1131 * example in Rx process this index will point to the descriptor
1132 * that will be passed to the user upon calling the receive routine.
1133 * In Tx process, this index will point to the descriptor
1134 * that will be assigned with the user packet info and transmitted.
1136 * This index points to the descriptor that need to restore its
1137 * resources. For example in Rx process, using the Rx buffer return
1138 * API will attach the buffer returned in packet info to the
1139 * descriptor pointed by 'used'. In Tx process, using the Tx
1140 * descriptor return will merely return the user packet info with
1141 * the command status of the transmitted buffer pointed by the
1142 * 'used' index. Nevertheless, it is essential to use this routine
1143 * to update the 'used' index.
1145 * This index supports Tx Scatter-Gather. It points to the first
1146 * descriptor of a packet assembled of multiple buffers. For example
1147 * when in middle of Such packet we have a Tx resource error the
1148 * 'curr' index get the value of 'first' to indicate that the ring
1149 * returned to its state before trying to transmit this packet.
1151 * Receive operation:
1152 * The eth_port_receive API set the packet information struct,
1153 * passed by the caller, with received information from the
1154 * 'current' SDMA descriptor.
1155 * It is the user responsibility to return this resource back
1156 * to the Rx descriptor ring to enable the reuse of this source.
1157 * Return Rx resource is done using the eth_rx_return_buff API.
1159 * Transmit operation:
1160 * The eth_port_send API supports Scatter-Gather which enables to
1161 * send a packet spanned over multiple buffers. This means that
1162 * for each packet info structure given by the user and put into
1163 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1164 * bit will be set in the packet info command status field. This
1165 * API also consider restriction regarding buffer alignments and
1167 * The user must return a Tx resource after ensuring the buffer
1168 * has been transmitted to enable the Tx ring indexes to update.
1171 * This device is on-board. No jumper diagram is necessary.
1173 * EXTERNAL INTERFACE
1175 * Prior to calling the initialization routine eth_port_init() the user
1176 * must set the following fields under ETH_PORT_INFO struct:
1177 * port_num User Ethernet port number.
1178 * port_phy_addr User PHY address of Ethernet port.
1179 * port_mac_addr[6] User defined port MAC address.
1180 * port_config User port configuration value.
1181 * port_config_extend User port config extend value.
1182 * port_sdma_config User port SDMA config value.
1183 * port_serial_control User port serial control value.
1184 * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr.
1185 * *port_private User scratch pad for user specific data structures.
1187 * This driver introduce a set of default values:
1188 * PORT_CONFIG_VALUE Default port configuration value
1189 * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value
1190 * PORT_SDMA_CONFIG_VALUE Default sdma control value
1191 * PORT_SERIAL_CONTROL_VALUE Default port serial control value
1193 * This driver data flow is done using the PKT_INFO struct which is
1194 * a unified struct for Rx and Tx operations:
1195 * byte_cnt Tx/Rx descriptor buffer byte count.
1196 * l4i_chk CPU provided TCP Checksum. For Tx operation only.
1197 * cmd_sts Tx/Rx descriptor command status.
1198 * buf_ptr Tx/Rx descriptor buffer pointer.
1199 * return_info Tx/Rx user resource return information.
1202 * EXTERNAL SUPPORT REQUIREMENTS
1204 * This driver requires the following external support:
1206 * D_CACHE_FLUSH_LINE (address, address offset)
1208 * This macro applies assembly code to flush and invalidate cache
1210 * address - address base.
1211 * address offset - address offset
1216 * This macro applies assembly code to flush the CPU pipeline.
1218 *******************************************************************************/
1222 /* SDMA command macros */
1223 #define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \
1224 MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue))
1226 #define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \
1227 MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\
1228 (1 << (8 + tx_queue)))
1230 #define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \
1231 MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue))
1233 #define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \
1234 MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue)))
1236 #define CURR_RFD_GET(p_curr_desc, queue) \
1237 ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue])
1239 #define CURR_RFD_SET(p_curr_desc, queue) \
1240 (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc))
1242 #define USED_RFD_GET(p_used_desc, queue) \
1243 ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue])
1245 #define USED_RFD_SET(p_used_desc, queue)\
1246 (p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc))
1249 #define CURR_TFD_GET(p_curr_desc, queue) \
1250 ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue])
1252 #define CURR_TFD_SET(p_curr_desc, queue) \
1253 (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc))
1255 #define USED_TFD_GET(p_used_desc, queue) \
1256 ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue])
1258 #define USED_TFD_SET(p_used_desc, queue) \
1259 (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc))
1261 #define FIRST_TFD_GET(p_first_desc, queue) \
1262 ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue])
1264 #define FIRST_TFD_SET(p_first_desc, queue) \
1265 (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc))
1268 /* Macros that save access to desc in order to find next desc pointer */
1269 #define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue])
1271 #define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue])
1273 #define LINK_UP_TIMEOUT 100000
1274 #define PHY_BUSY_TIMEOUT 10000000
1279 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr);
1280 static int ethernet_phy_get (ETH_PORT eth_port_num);
1282 /* Ethernet Port routines */
1283 static void eth_set_access_control (ETH_PORT eth_port_num,
1284 ETH_WIN_PARAM * param);
1285 static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble,
1286 ETH_QUEUE queue, int option);
1288 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
1289 unsigned char mc_byte,
1290 ETH_QUEUE queue, int option);
1291 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
1293 ETH_QUEUE queue, int option);
1296 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
1299 void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl);
1302 typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
1303 u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank)
1306 u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
1308 if (enable & (1 << bank))
1311 result = MV_REG_READ (MV64360_CS_0_BASE_ADDR);
1313 result = MV_REG_READ (MV64360_CS_1_BASE_ADDR);
1315 result = MV_REG_READ (MV64360_CS_2_BASE_ADDR);
1317 result = MV_REG_READ (MV64360_CS_3_BASE_ADDR);
1318 result &= 0x0000ffff;
1319 result = result << 16;
1323 u32 mv_get_dram_bank_size (MEMORY_BANK bank)
1326 u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE);
1328 if (enable & (1 << bank))
1331 result = MV_REG_READ (MV64360_CS_0_SIZE);
1333 result = MV_REG_READ (MV64360_CS_1_SIZE);
1335 result = MV_REG_READ (MV64360_CS_2_SIZE);
1337 result = MV_REG_READ (MV64360_CS_3_SIZE);
1339 result &= 0x0000ffff;
1340 result = result << 16;
1344 u32 mv_get_internal_sram_base (void)
1348 result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR);
1349 result &= 0x0000ffff;
1350 result = result << 16;
1354 /*******************************************************************************
1355 * eth_port_init - Initialize the Ethernet port driver
1358 * This function prepares the ethernet port to start its activity:
1359 * 1) Completes the ethernet port driver struct initialization toward port
1361 * 2) Resets the device to a quiescent state in case of warm reboot.
1362 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1363 * 4) Clean MAC tables. The reset status of those tables is unknown.
1364 * 5) Set PHY address.
1365 * Note: Call this routine prior to eth_port_start routine and after setting
1366 * user values in the user fields of Ethernet port control struct (i.e.
1370 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1378 *******************************************************************************/
1379 static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl)
1382 ETH_WIN_PARAM win_param;
1384 p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE;
1385 p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE;
1386 p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE;
1387 p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE;
1389 p_eth_port_ctrl->port_rx_queue_command = 0;
1390 p_eth_port_ctrl->port_tx_queue_command = 0;
1392 /* Zero out SW structs */
1393 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1394 CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1395 USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue);
1396 p_eth_port_ctrl->rx_resource_err[queue] = false;
1399 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1400 CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1401 USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1402 FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue);
1403 p_eth_port_ctrl->tx_resource_err[queue] = false;
1406 eth_port_reset (p_eth_port_ctrl->port_num);
1408 /* Set access parameters for DRAM bank 0 */
1409 win_param.win = ETH_WIN0; /* Use Ethernet window 0 */
1410 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1411 win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */
1412 #ifndef CONFIG_NOT_COHERENT_CACHE
1413 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1415 win_param.high_addr = 0;
1417 win_param.base_addr = mv_get_dram_bank_base_addr (BANK0);
1418 win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */
1419 if (win_param.size == 0)
1420 win_param.enable = 0;
1422 win_param.enable = 1; /* Enable the access */
1423 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1425 /* Set the access control for address window (EPAPR) READ & WRITE */
1426 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1428 /* Set access parameters for DRAM bank 1 */
1429 win_param.win = ETH_WIN1; /* Use Ethernet window 1 */
1430 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1431 win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */
1432 #ifndef CONFIG_NOT_COHERENT_CACHE
1433 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1435 win_param.high_addr = 0;
1437 win_param.base_addr = mv_get_dram_bank_base_addr (BANK1);
1438 win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */
1439 if (win_param.size == 0)
1440 win_param.enable = 0;
1442 win_param.enable = 1; /* Enable the access */
1443 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1445 /* Set the access control for address window (EPAPR) READ & WRITE */
1446 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1448 /* Set access parameters for DRAM bank 2 */
1449 win_param.win = ETH_WIN2; /* Use Ethernet window 2 */
1450 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1451 win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */
1452 #ifndef CONFIG_NOT_COHERENT_CACHE
1453 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1455 win_param.high_addr = 0;
1457 win_param.base_addr = mv_get_dram_bank_base_addr (BANK2);
1458 win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */
1459 if (win_param.size == 0)
1460 win_param.enable = 0;
1462 win_param.enable = 1; /* Enable the access */
1463 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1465 /* Set the access control for address window (EPAPR) READ & WRITE */
1466 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1468 /* Set access parameters for DRAM bank 3 */
1469 win_param.win = ETH_WIN3; /* Use Ethernet window 3 */
1470 win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */
1471 win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */
1472 #ifndef CONFIG_NOT_COHERENT_CACHE
1473 win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB;
1475 win_param.high_addr = 0;
1477 win_param.base_addr = mv_get_dram_bank_base_addr (BANK3);
1478 win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */
1479 if (win_param.size == 0)
1480 win_param.enable = 0;
1482 win_param.enable = 1; /* Enable the access */
1483 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1485 /* Set the access control for address window (EPAPR) READ & WRITE */
1486 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1488 /* Set access parameters for Internal SRAM */
1489 win_param.win = ETH_WIN4; /* Use Ethernet window 0 */
1490 win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */
1491 win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0;
1492 win_param.high_addr = 0;
1493 win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */
1494 win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */
1495 win_param.enable = 1; /* Enable the access */
1496 win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */
1498 /* Set the access control for address window (EPAPR) READ & WRITE */
1499 eth_set_access_control (p_eth_port_ctrl->port_num, &win_param);
1501 eth_port_init_mac_tables (p_eth_port_ctrl->port_num);
1503 ethernet_phy_set (p_eth_port_ctrl->port_num,
1504 p_eth_port_ctrl->port_phy_addr);
1510 /*******************************************************************************
1511 * eth_port_start - Start the Ethernet port activity.
1514 * This routine prepares the Ethernet port for Rx and Tx activity:
1515 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1516 * has been initialized a descriptor's ring (using ether_init_tx_desc_ring
1517 * for Tx and ether_init_rx_desc_ring for Rx)
1518 * 2. Initialize and enable the Ethernet configuration port by writing to
1519 * the port's configuration and command registers.
1520 * 3. Initialize and enable the SDMA by writing to the SDMA's
1521 * configuration and command registers.
1522 * After completing these steps, the ethernet port SDMA can starts to
1523 * perform Rx and Tx activities.
1525 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1526 * to calling this function (use ether_init_tx_desc_ring for Tx queues and
1527 * ether_init_rx_desc_ring for Rx queues).
1530 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct
1533 * Ethernet port is ready to receive and transmit.
1536 * false if the port PHY is not up.
1539 *******************************************************************************/
1540 static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl)
1543 volatile ETH_TX_DESC *p_tx_curr_desc;
1544 volatile ETH_RX_DESC *p_rx_curr_desc;
1545 unsigned int phy_reg_data;
1546 ETH_PORT eth_port_num = p_eth_port_ctrl->port_num;
1549 /* Assignment of Tx CTRP of given queue */
1550 for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) {
1551 CURR_TFD_GET (p_tx_curr_desc, queue);
1552 MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0
1555 ((unsigned int) p_tx_curr_desc));
1559 /* Assignment of Rx CRDP of given queue */
1560 for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) {
1561 CURR_RFD_GET (p_rx_curr_desc, queue);
1562 MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0
1565 ((unsigned int) p_rx_curr_desc));
1567 if (p_rx_curr_desc != NULL)
1568 /* Add the assigned Ethernet address to the port's address table */
1569 eth_port_uc_addr_set (p_eth_port_ctrl->port_num,
1570 p_eth_port_ctrl->port_mac_addr,
1574 /* Assign port configuration and command. */
1575 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
1576 p_eth_port_ctrl->port_config);
1578 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
1579 p_eth_port_ctrl->port_config_extend);
1581 MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1582 p_eth_port_ctrl->port_serial_control);
1584 MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
1585 ETH_SERIAL_PORT_ENABLE);
1587 /* Assign port SDMA configuration */
1588 MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
1589 p_eth_port_ctrl->port_sdma_config);
1591 MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT
1592 (eth_port_num), 0x3fffffff);
1593 MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG
1594 (eth_port_num), 0x03fffcff);
1595 /* Turn off the port/queue bandwidth limitation */
1596 MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0);
1598 /* Enable port Rx. */
1599 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num),
1600 p_eth_port_ctrl->port_rx_queue_command);
1602 /* Check if link is up */
1603 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
1605 if (!(phy_reg_data & 0x20))
1611 /*******************************************************************************
1612 * eth_port_uc_addr_set - This function Set the port Unicast address.
1615 * This function Set the port Ethernet MAC address.
1618 * ETH_PORT eth_port_num Port number.
1619 * char * p_addr Address to be set
1620 * ETH_QUEUE queue Rx queue number for this MAC address.
1623 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1624 * To set the unicast table with the proper information.
1629 *******************************************************************************/
1630 static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
1631 unsigned char *p_addr, ETH_QUEUE queue)
1636 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1637 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) |
1638 (p_addr[2] << 8) | (p_addr[3] << 0);
1640 MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l);
1641 MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h);
1643 /* Accept frames of this address */
1644 eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR);
1649 /*******************************************************************************
1650 * eth_port_uc_addr - This function Set the port unicast address table
1653 * This function locates the proper entry in the Unicast table for the
1654 * specified MAC nibble and sets its properties according to function
1658 * ETH_PORT eth_port_num Port number.
1659 * unsigned char uc_nibble Unicast MAC Address last nibble.
1660 * ETH_QUEUE queue Rx queue number for this MAC address.
1661 * int option 0 = Add, 1 = remove address.
1664 * This function add/removes MAC addresses from the port unicast address
1668 * true is output succeeded.
1669 * false if option parameter is invalid.
1671 *******************************************************************************/
1672 static bool eth_port_uc_addr (ETH_PORT eth_port_num,
1673 unsigned char uc_nibble,
1674 ETH_QUEUE queue, int option)
1676 unsigned int unicast_reg;
1677 unsigned int tbl_offset;
1678 unsigned int reg_offset;
1680 /* Locate the Unicast table entry */
1681 uc_nibble = (0xf & uc_nibble);
1682 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
1683 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
1686 case REJECT_MAC_ADDR:
1687 /* Clear accepts frame bit at specified unicast DA table entry */
1689 MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1693 unicast_reg &= (0x0E << (8 * reg_offset));
1695 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1697 + tbl_offset), unicast_reg);
1700 case ACCEPT_MAC_ADDR:
1701 /* Set accepts frame bit at unicast DA filter table entry */
1703 MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1707 unicast_reg |= ((0x01 | queue) << (8 * reg_offset));
1709 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
1711 + tbl_offset), unicast_reg);
1722 /*******************************************************************************
1723 * eth_port_mc_addr - Multicast address settings.
1726 * This API controls the MV device MAC multicast support.
1727 * The MV device supports multicast using two tables:
1728 * 1) Special Multicast Table for MAC addresses of the form
1729 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
1730 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1731 * Table entries in the DA-Filter table.
1732 * In this case, the function calls eth_port_smc_addr() routine to set the
1733 * Special Multicast Table.
1734 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1735 * is used as an index to the Other Multicast Table entries in the
1737 * In this case, the function calculates the CRC-8bit value and calls
1738 * eth_port_omc_addr() routine to set the Other Multicast Table.
1740 * ETH_PORT eth_port_num Port number.
1741 * unsigned char *p_addr Unicast MAC Address.
1742 * ETH_QUEUE queue Rx queue number for this MAC address.
1743 * int option 0 = Add, 1 = remove address.
1749 * true is output succeeded.
1750 * false if add_address_table_entry( ) failed.
1752 *******************************************************************************/
1753 static void eth_port_mc_addr (ETH_PORT eth_port_num,
1754 unsigned char *p_addr,
1755 ETH_QUEUE queue, int option)
1759 unsigned char crc_result = 0;
1765 if ((p_addr[0] == 0x01) &&
1766 (p_addr[1] == 0x00) &&
1767 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00))
1769 eth_port_smc_addr (eth_port_num, p_addr[5], queue, option);
1771 /* Calculate CRC-8 out of the given address */
1772 mac_h = (p_addr[0] << 8) | (p_addr[1]);
1773 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
1774 (p_addr[4] << 8) | (p_addr[5] << 0);
1776 for (i = 0; i < 32; i++)
1777 mac_array[i] = (mac_l >> i) & 0x1;
1778 for (i = 32; i < 48; i++)
1779 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1782 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^
1783 mac_array[39] ^ mac_array[35] ^ mac_array[34] ^
1784 mac_array[31] ^ mac_array[30] ^ mac_array[28] ^
1785 mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1786 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1787 mac_array[12] ^ mac_array[8] ^ mac_array[7] ^
1788 mac_array[6] ^ mac_array[0];
1790 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1791 mac_array[43] ^ mac_array[41] ^ mac_array[39] ^
1792 mac_array[36] ^ mac_array[34] ^ mac_array[32] ^
1793 mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1794 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^
1795 mac_array[21] ^ mac_array[20] ^ mac_array[18] ^
1796 mac_array[17] ^ mac_array[16] ^ mac_array[15] ^
1797 mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1798 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^
1801 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^
1802 mac_array[43] ^ mac_array[42] ^ mac_array[39] ^
1803 mac_array[37] ^ mac_array[34] ^ mac_array[33] ^
1804 mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1805 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^
1806 mac_array[15] ^ mac_array[13] ^ mac_array[12] ^
1807 mac_array[10] ^ mac_array[8] ^ mac_array[6] ^
1808 mac_array[2] ^ mac_array[1] ^ mac_array[0];
1810 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^
1811 mac_array[43] ^ mac_array[40] ^ mac_array[38] ^
1812 mac_array[35] ^ mac_array[34] ^ mac_array[30] ^
1813 mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1814 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^
1815 mac_array[14] ^ mac_array[13] ^ mac_array[11] ^
1816 mac_array[9] ^ mac_array[7] ^ mac_array[3] ^
1817 mac_array[2] ^ mac_array[1];
1819 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^
1820 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^
1821 mac_array[35] ^ mac_array[31] ^ mac_array[30] ^
1822 mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1823 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^
1824 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
1825 mac_array[8] ^ mac_array[4] ^ mac_array[3] ^
1828 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^
1829 mac_array[42] ^ mac_array[40] ^ mac_array[37] ^
1830 mac_array[36] ^ mac_array[32] ^ mac_array[31] ^
1831 mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1832 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^
1833 mac_array[15] ^ mac_array[13] ^ mac_array[11] ^
1834 mac_array[9] ^ mac_array[5] ^ mac_array[4] ^
1837 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^
1838 mac_array[41] ^ mac_array[38] ^ mac_array[37] ^
1839 mac_array[33] ^ mac_array[32] ^ mac_array[29] ^
1840 mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1841 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^
1842 mac_array[14] ^ mac_array[12] ^ mac_array[10] ^
1843 mac_array[6] ^ mac_array[5] ^ mac_array[4];
1845 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^
1846 mac_array[39] ^ mac_array[38] ^ mac_array[34] ^
1847 mac_array[33] ^ mac_array[30] ^ mac_array[29] ^
1848 mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1849 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^
1850 mac_array[13] ^ mac_array[11] ^ mac_array[7] ^
1851 mac_array[6] ^ mac_array[5];
1853 for (i = 0; i < 8; i++)
1854 crc_result = crc_result | (crc[i] << i);
1856 eth_port_omc_addr (eth_port_num, crc_result, queue, option);
1861 /*******************************************************************************
1862 * eth_port_smc_addr - Special Multicast address settings.
1865 * This routine controls the MV device special MAC multicast support.
1866 * The Special Multicast Table for MAC addresses supports MAC of the form
1867 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF).
1868 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1869 * Table entries in the DA-Filter table.
1870 * This function set the Special Multicast Table appropriate entry
1871 * according to the argument given.
1874 * ETH_PORT eth_port_num Port number.
1875 * unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits).
1876 * ETH_QUEUE queue Rx queue number for this MAC address.
1877 * int option 0 = Add, 1 = remove address.
1883 * true is output succeeded.
1884 * false if option parameter is invalid.
1886 *******************************************************************************/
1887 static bool eth_port_smc_addr (ETH_PORT eth_port_num,
1888 unsigned char mc_byte,
1889 ETH_QUEUE queue, int option)
1891 unsigned int smc_table_reg;
1892 unsigned int tbl_offset;
1893 unsigned int reg_offset;
1895 /* Locate the SMC table entry */
1896 tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */
1897 reg_offset = mc_byte % 4; /* Entry offset within the above register */
1901 case REJECT_MAC_ADDR:
1902 /* Clear accepts frame bit at specified Special DA table entry */
1904 MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1905 smc_table_reg &= (0x0E << (8 * reg_offset));
1907 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
1910 case ACCEPT_MAC_ADDR:
1911 /* Set accepts frame bit at specified Special DA table entry */
1913 MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1914 smc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
1916 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg);
1925 /*******************************************************************************
1926 * eth_port_omc_addr - Multicast address settings.
1929 * This routine controls the MV device Other MAC multicast support.
1930 * The Other Multicast Table is used for multicast of another type.
1931 * A CRC-8bit is used as an index to the Other Multicast Table entries
1932 * in the DA-Filter table.
1933 * The function gets the CRC-8bit value from the calling routine and
1934 * set the Other Multicast Table appropriate entry according to the
1935 * CRC-8 argument given.
1938 * ETH_PORT eth_port_num Port number.
1939 * unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1).
1940 * ETH_QUEUE queue Rx queue number for this MAC address.
1941 * int option 0 = Add, 1 = remove address.
1947 * true is output succeeded.
1948 * false if option parameter is invalid.
1950 *******************************************************************************/
1951 static bool eth_port_omc_addr (ETH_PORT eth_port_num,
1953 ETH_QUEUE queue, int option)
1955 unsigned int omc_table_reg;
1956 unsigned int tbl_offset;
1957 unsigned int reg_offset;
1959 /* Locate the OMC table entry */
1960 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1961 reg_offset = crc8 % 4; /* Entry offset within the above register */
1965 case REJECT_MAC_ADDR:
1966 /* Clear accepts frame bit at specified Other DA table entry */
1968 MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1969 omc_table_reg &= (0x0E << (8 * reg_offset));
1971 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
1974 case ACCEPT_MAC_ADDR:
1975 /* Set accepts frame bit at specified Other DA table entry */
1977 MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset));
1978 omc_table_reg |= ((0x01 | queue) << (8 * reg_offset));
1980 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg);
1990 /*******************************************************************************
1991 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
1994 * Go through all the DA filter tables (Unicast, Special Multicast & Other
1995 * Multicast) and set each entry to 0.
1998 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2001 * Multicast and Unicast packets are rejected.
2006 *******************************************************************************/
2007 static void eth_port_init_mac_tables (ETH_PORT eth_port_num)
2011 /* Clear DA filter unicast table (Ex_dFUT) */
2012 for (table_index = 0; table_index <= 0xC; table_index += 4)
2013 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE
2014 (eth_port_num) + table_index), 0);
2016 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2017 /* Clear DA filter special multicast table (Ex_dFSMT) */
2018 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
2019 /* Clear DA filter other multicast table (Ex_dFOMT) */
2020 MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0);
2024 /*******************************************************************************
2025 * eth_clear_mib_counters - Clear all MIB counters
2028 * This function clears all MIB counters of a specific ethernet port.
2029 * A read from the MIB counter will reset the counter.
2032 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2035 * After reading all MIB counters, the counters resets.
2038 * MIB counter value.
2040 *******************************************************************************/
2041 static void eth_clear_mib_counters (ETH_PORT eth_port_num)
2045 /* Perform dummy reads from MIB counters */
2046 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2048 MV_REG_READ((MV64360_ETH_MIB_COUNTERS_BASE(eth_port_num) + i));
2053 /*******************************************************************************
2054 * eth_read_mib_counter - Read a MIB counter
2057 * This function reads a MIB counter of a specific ethernet port.
2058 * NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the
2059 * following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
2060 * register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and
2061 * ETH_MIB_GOOD_OCTETS_SENT_HIGH
2064 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2065 * unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros).
2068 * After reading the MIB counter, the counter resets.
2071 * MIB counter value.
2073 *******************************************************************************/
2074 unsigned int eth_read_mib_counter (ETH_PORT eth_port_num,
2075 unsigned int mib_offset)
2077 return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num)
2081 /*******************************************************************************
2082 * ethernet_phy_set - Set the ethernet port PHY address.
2085 * This routine set the ethernet port PHY address according to given
2089 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2092 * Set PHY Address Register with given PHY address parameter.
2097 *******************************************************************************/
2098 static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr)
2100 unsigned int reg_data;
2102 reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
2104 reg_data &= ~(0x1F << (5 * eth_port_num));
2105 reg_data |= (phy_addr << (5 * eth_port_num));
2107 MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data);
2112 /*******************************************************************************
2113 * ethernet_phy_get - Get the ethernet port PHY address.
2116 * This routine returns the given ethernet port PHY address.
2119 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2127 *******************************************************************************/
2128 static int ethernet_phy_get (ETH_PORT eth_port_num)
2130 unsigned int reg_data;
2132 reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG);
2134 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2137 /*******************************************************************************
2138 * ethernet_phy_reset - Reset Ethernet port PHY.
2141 * This routine utilize the SMI interface to reset the ethernet port PHY.
2142 * The routine waits until the link is up again or link up is timeout.
2145 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2148 * The ethernet port PHY renew its link.
2153 *******************************************************************************/
2154 static bool ethernet_phy_reset (ETH_PORT eth_port_num)
2156 unsigned int time_out = 50;
2157 unsigned int phy_reg_data;
2160 eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data);
2161 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2162 eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data);
2164 /* Poll on the PHY LINK */
2166 eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data);
2168 if (time_out-- == 0)
2171 while (!(phy_reg_data & 0x20));
2176 /*******************************************************************************
2177 * eth_port_reset - Reset Ethernet port
2180 * This routine resets the chip by aborting any SDMA engine activity and
2181 * clearing the MIB counters. The Receiver and the Transmit unit are in
2182 * idle state after this command is performed and the port is disabled.
2185 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2188 * Channel activity is halted.
2193 *******************************************************************************/
2194 static void eth_port_reset (ETH_PORT eth_port_num)
2196 unsigned int reg_data;
2198 /* Stop Tx port activity. Check port Tx activity. */
2200 MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
2203 if (reg_data & 0xFF) {
2204 /* Issue stop command for active channels only */
2205 MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
2206 (eth_port_num), (reg_data << 8));
2208 /* Wait for all Tx activity to terminate. */
2210 /* Check port cause register that all Tx queues are stopped */
2213 (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG
2216 while (reg_data & 0xFF);
2219 /* Stop Rx port activity. Check port Rx activity. */
2221 MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
2224 if (reg_data & 0xFF) {
2225 /* Issue stop command for active channels only */
2226 MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
2227 (eth_port_num), (reg_data << 8));
2229 /* Wait for all Rx activity to terminate. */
2231 /* Check port cause register that all Rx queues are stopped */
2234 (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG
2237 while (reg_data & 0xFF);
2241 /* Clear all MIB counters */
2242 eth_clear_mib_counters (eth_port_num);
2244 /* Reset the Enable bit in the Configuration Register */
2246 MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG
2248 reg_data &= ~ETH_SERIAL_PORT_ENABLE;
2249 MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num),
2255 #if 0 /* Not needed here */
2256 /*******************************************************************************
2257 * ethernet_set_config_reg - Set specified bits in configuration register.
2260 * This function sets specified bits in the given ethernet
2261 * configuration register.
2264 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2265 * unsigned int value 32 bit value.
2268 * The set bits in the value parameter are set in the configuration
2274 *******************************************************************************/
2275 static void ethernet_set_config_reg (ETH_PORT eth_port_num,
2278 unsigned int eth_config_reg;
2281 MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num));
2282 eth_config_reg |= value;
2283 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num),
2291 /*******************************************************************************
2292 * ethernet_reset_config_reg - Reset specified bits in configuration register.
2295 * This function resets specified bits in the given Ethernet
2296 * configuration register.
2299 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2300 * unsigned int value 32 bit value.
2303 * The set bits in the value parameter are reset in the configuration
2309 *******************************************************************************/
2310 static void ethernet_reset_config_reg (ETH_PORT eth_port_num,
2313 unsigned int eth_config_reg;
2315 eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
2317 eth_config_reg &= ~value;
2318 MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num),
2325 #if 0 /* Not needed here */
2326 /*******************************************************************************
2327 * ethernet_get_config_reg - Get the port configuration register
2330 * This function returns the configuration register value of the given
2334 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2340 * Port configuration register value.
2342 *******************************************************************************/
2343 static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num)
2345 unsigned int eth_config_reg;
2347 eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG
2349 return eth_config_reg;
2354 /*******************************************************************************
2355 * eth_port_read_smi_reg - Read PHY registers
2358 * This routine utilize the SMI interface to interact with the PHY in
2359 * order to perform PHY register read.
2362 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2363 * unsigned int phy_reg PHY register address offset.
2364 * unsigned int *value Register value buffer.
2367 * Write the value of a specified PHY register into given buffer.
2370 * false if the PHY is busy or read data is not in valid state.
2373 *******************************************************************************/
2374 static bool eth_port_read_smi_reg (ETH_PORT eth_port_num,
2375 unsigned int phy_reg, unsigned int *value)
2377 unsigned int reg_value;
2378 unsigned int time_out = PHY_BUSY_TIMEOUT;
2381 phy_addr = ethernet_phy_get (eth_port_num);
2382 /* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/
2384 /* first check that it is not busy */
2386 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2387 if (time_out-- == 0) {
2391 while (reg_value & ETH_SMI_BUSY);
2395 MV_REG_WRITE (MV64360_ETH_SMI_REG,
2396 (phy_addr << 16) | (phy_reg << 21) |
2397 ETH_SMI_OPCODE_READ);
2399 time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */
2402 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2403 if (time_out-- == 0) {
2407 while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */
2409 /* Wait for the data to update in the SMI register */
2410 #define PHY_UPDATE_TIMEOUT 10000
2411 for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++);
2413 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2415 *value = reg_value & 0xffff;
2420 /*******************************************************************************
2421 * eth_port_write_smi_reg - Write to PHY registers
2424 * This routine utilize the SMI interface to interact with the PHY in
2425 * order to perform writes to PHY registers.
2428 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2429 * unsigned int phy_reg PHY register address offset.
2430 * unsigned int value Register value.
2433 * Write the given value to the specified PHY register.
2436 * false if the PHY is busy.
2439 *******************************************************************************/
2440 static bool eth_port_write_smi_reg (ETH_PORT eth_port_num,
2441 unsigned int phy_reg, unsigned int value)
2443 unsigned int reg_value;
2444 unsigned int time_out = PHY_BUSY_TIMEOUT;
2447 phy_addr = ethernet_phy_get (eth_port_num);
2449 /* first check that it is not busy */
2451 reg_value = MV_REG_READ (MV64360_ETH_SMI_REG);
2452 if (time_out-- == 0) {
2456 while (reg_value & ETH_SMI_BUSY);
2459 MV_REG_WRITE (MV64360_ETH_SMI_REG,
2460 (phy_addr << 16) | (phy_reg << 21) |
2461 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2465 /*******************************************************************************
2466 * eth_set_access_control - Config address decode parameters for Ethernet unit
2469 * This function configures the address decode parameters for the Gigabit
2470 * Ethernet Controller according the given parameters struct.
2473 * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum.
2474 * ETH_WIN_PARAM *param Address decode parameter struct.
2477 * An access window is opened using the given access parameters.
2482 *******************************************************************************/
2483 static void eth_set_access_control (ETH_PORT eth_port_num,
2484 ETH_WIN_PARAM * param)
2486 unsigned int access_prot_reg;
2488 /* Set access control register */
2489 access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG
2491 access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */
2492 access_prot_reg |= (param->access_ctrl << (param->win * 2));
2493 MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num),
2496 /* Set window Size reg (SR) */
2497 MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 +
2498 (ETH_SIZE_REG_GAP * param->win)),
2499 (((param->size / 0x10000) - 1) << 16));
2501 /* Set window Base address reg (BA) */
2502 MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)),
2503 (param->target | param->attributes | param->base_addr));
2504 /* High address remap reg (HARR) */
2506 MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 +
2507 (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)),
2510 /* Base address enable reg (BARER) */
2511 if (param->enable == 1)
2512 MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
2515 MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG,
2519 /*******************************************************************************
2520 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
2523 * This function prepares a Rx chained list of descriptors and packet
2524 * buffers in a form of a ring. The routine must be called after port
2525 * initialization routine and before port start routine.
2526 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2527 * devices in the system (i.e. DRAM). This function uses the ethernet
2528 * struct 'virtual to physical' routine (set by the user) to set the ring
2529 * with physical addresses.
2532 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2533 * ETH_QUEUE rx_queue Number of Rx queue.
2534 * int rx_desc_num Number of Rx descriptors
2535 * int rx_buff_size Size of Rx buffer
2536 * unsigned int rx_desc_base_addr Rx descriptors memory area base addr.
2537 * unsigned int rx_buff_base_addr Rx buffer memory area base addr.
2540 * The routine updates the Ethernet port control struct with information
2541 * regarding the Rx descriptors and buffers.
2544 * false if the given descriptors memory area is not aligned according to
2545 * Ethernet SDMA specifications.
2548 *******************************************************************************/
2549 static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2553 unsigned int rx_desc_base_addr,
2554 unsigned int rx_buff_base_addr)
2556 ETH_RX_DESC *p_rx_desc;
2557 ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */
2558 unsigned int buffer_addr;
2559 int ix; /* a counter */
2562 p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr;
2563 p_rx_prev_desc = p_rx_desc;
2564 buffer_addr = rx_buff_base_addr;
2566 /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2567 if (rx_buff_base_addr & 0xF)
2570 /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2571 if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE))
2574 /* Rx buffers must be 64-bit aligned. */
2575 if ((rx_buff_base_addr + rx_buff_size) & 0x7)
2578 /* initialize the Rx descriptors ring */
2579 for (ix = 0; ix < rx_desc_num; ix++) {
2580 p_rx_desc->buf_size = rx_buff_size;
2581 p_rx_desc->byte_cnt = 0x0000;
2582 p_rx_desc->cmd_sts =
2583 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2584 p_rx_desc->next_desc_ptr =
2585 ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE;
2586 p_rx_desc->buf_ptr = buffer_addr;
2587 p_rx_desc->return_info = 0x00000000;
2588 D_CACHE_FLUSH_LINE (p_rx_desc, 0);
2589 buffer_addr += rx_buff_size;
2590 p_rx_prev_desc = p_rx_desc;
2591 p_rx_desc = (ETH_RX_DESC *)
2592 ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE);
2595 /* Closing Rx descriptors ring */
2596 p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr);
2597 D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0);
2599 /* Save Rx desc pointer to driver struct. */
2600 CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2601 USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue);
2603 p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] =
2604 (ETH_RX_DESC *) rx_desc_base_addr;
2605 p_eth_port_ctrl->rx_desc_area_size[rx_queue] =
2606 rx_desc_num * RX_DESC_ALIGNED_SIZE;
2608 p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue);
2613 /*******************************************************************************
2614 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
2617 * This function prepares a Tx chained list of descriptors and packet
2618 * buffers in a form of a ring. The routine must be called after port
2619 * initialization routine and before port start routine.
2620 * The Ethernet SDMA engine uses CPU bus addresses to access the various
2621 * devices in the system (i.e. DRAM). This function uses the ethernet
2622 * struct 'virtual to physical' routine (set by the user) to set the ring
2623 * with physical addresses.
2626 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2627 * ETH_QUEUE tx_queue Number of Tx queue.
2628 * int tx_desc_num Number of Tx descriptors
2629 * int tx_buff_size Size of Tx buffer
2630 * unsigned int tx_desc_base_addr Tx descriptors memory area base addr.
2631 * unsigned int tx_buff_base_addr Tx buffer memory area base addr.
2634 * The routine updates the Ethernet port control struct with information
2635 * regarding the Tx descriptors and buffers.
2638 * false if the given descriptors memory area is not aligned according to
2639 * Ethernet SDMA specifications.
2642 *******************************************************************************/
2643 static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl,
2647 unsigned int tx_desc_base_addr,
2648 unsigned int tx_buff_base_addr)
2651 ETH_TX_DESC *p_tx_desc;
2652 ETH_TX_DESC *p_tx_prev_desc;
2653 unsigned int buffer_addr;
2654 int ix; /* a counter */
2657 /* save the first desc pointer to link with the last descriptor */
2658 p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr;
2659 p_tx_prev_desc = p_tx_desc;
2660 buffer_addr = tx_buff_base_addr;
2662 /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */
2663 if (tx_buff_base_addr & 0xF)
2666 /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */
2667 if ((tx_buff_size > TX_BUFFER_MAX_SIZE)
2668 || (tx_buff_size < TX_BUFFER_MIN_SIZE))
2671 /* Initialize the Tx descriptors ring */
2672 for (ix = 0; ix < tx_desc_num; ix++) {
2673 p_tx_desc->byte_cnt = 0x0000;
2674 p_tx_desc->l4i_chk = 0x0000;
2675 p_tx_desc->cmd_sts = 0x00000000;
2676 p_tx_desc->next_desc_ptr =
2677 ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE;
2679 p_tx_desc->buf_ptr = buffer_addr;
2680 p_tx_desc->return_info = 0x00000000;
2681 D_CACHE_FLUSH_LINE (p_tx_desc, 0);
2682 buffer_addr += tx_buff_size;
2683 p_tx_prev_desc = p_tx_desc;
2684 p_tx_desc = (ETH_TX_DESC *)
2685 ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE);
2688 /* Closing Tx descriptors ring */
2689 p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr;
2690 D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0);
2691 /* Set Tx desc pointer in driver struct. */
2692 CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2693 USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue);
2695 /* Init Tx ring base and size parameters */
2696 p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] =
2697 (ETH_TX_DESC *) tx_desc_base_addr;
2698 p_eth_port_ctrl->tx_desc_area_size[tx_queue] =
2699 (tx_desc_num * TX_DESC_ALIGNED_SIZE);
2701 /* Add the queue to the list of Tx queues of this port */
2702 p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue);
2707 /*******************************************************************************
2708 * eth_port_send - Send an Ethernet packet
2711 * This routine send a given packet described by p_pktinfo parameter. It
2712 * supports transmitting of a packet spaned over multiple buffers. The
2713 * routine updates 'curr' and 'first' indexes according to the packet
2714 * segment passed to the routine. In case the packet segment is first,
2715 * the 'first' index is update. In any case, the 'curr' index is updated.
2716 * If the routine get into Tx resource error it assigns 'curr' index as
2717 * 'first'. This way the function can abort Tx process of multiple
2718 * descriptors per packet.
2721 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2722 * ETH_QUEUE tx_queue Number of Tx queue.
2723 * PKT_INFO *p_pkt_info User packet buffer.
2726 * Tx ring 'curr' and 'first' indexes are updated.
2729 * ETH_QUEUE_FULL in case of Tx resource error.
2730 * ETH_ERROR in case the routine can not access Tx desc ring.
2731 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2734 *******************************************************************************/
2735 static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl,
2737 PKT_INFO * p_pkt_info)
2739 volatile ETH_TX_DESC *p_tx_desc_first;
2740 volatile ETH_TX_DESC *p_tx_desc_curr;
2741 volatile ETH_TX_DESC *p_tx_next_desc_curr;
2742 volatile ETH_TX_DESC *p_tx_desc_used;
2743 unsigned int command_status;
2745 /* Do not process Tx ring in case of Tx ring resource error */
2746 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
2747 return ETH_QUEUE_FULL;
2749 /* Get the Tx Desc ring indexes */
2750 CURR_TFD_GET (p_tx_desc_curr, tx_queue);
2751 USED_TFD_GET (p_tx_desc_used, tx_queue);
2753 if (p_tx_desc_curr == NULL)
2756 /* The following parameters are used to save readings from memory */
2757 p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue);
2758 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2760 if (command_status & (ETH_TX_FIRST_DESC)) {
2761 /* Update first desc */
2762 FIRST_TFD_SET (p_tx_desc_curr, tx_queue);
2763 p_tx_desc_first = p_tx_desc_curr;
2765 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
2766 command_status |= ETH_BUFFER_OWNED_BY_DMA;
2769 /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */
2770 /* boundary. We use the memory allocated for Tx descriptor. This memory */
2771 /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */
2772 if (p_pkt_info->byte_cnt <= 8) {
2773 printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */
2776 p_tx_desc_curr->buf_ptr =
2777 (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC;
2778 eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr,
2779 p_pkt_info->byte_cnt);
2781 p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr;
2783 p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt;
2784 p_tx_desc_curr->return_info = p_pkt_info->return_info;
2786 if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) {
2787 /* Set last desc with DMA ownership and interrupt enable. */
2788 p_tx_desc_curr->cmd_sts = command_status |
2789 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2791 if (p_tx_desc_curr != p_tx_desc_first)
2792 p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA;
2794 /* Flush CPU pipe */
2796 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
2797 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0);
2800 /* Apply send command */
2801 ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num);
2803 /* Finish Tx packet. Update first desc in case of Tx resource error */
2804 p_tx_desc_first = p_tx_next_desc_curr;
2805 FIRST_TFD_SET (p_tx_desc_first, tx_queue);
2808 p_tx_desc_curr->cmd_sts = command_status;
2809 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0);
2812 /* Check for ring index overlap in the Tx desc ring */
2813 if (p_tx_next_desc_curr == p_tx_desc_used) {
2814 /* Update the current descriptor */
2815 CURR_TFD_SET (p_tx_desc_first, tx_queue);
2817 p_eth_port_ctrl->tx_resource_err[tx_queue] = true;
2818 return ETH_QUEUE_LAST_RESOURCE;
2820 /* Update the current descriptor */
2821 CURR_TFD_SET (p_tx_next_desc_curr, tx_queue);
2826 /*******************************************************************************
2827 * eth_tx_return_desc - Free all used Tx descriptors
2830 * This routine returns the transmitted packet information to the caller.
2831 * It uses the 'first' index to support Tx desc return in case a transmit
2832 * of a packet spanned over multiple buffer still in process.
2833 * In case the Tx queue was in "resource error" condition, where there are
2834 * no available Tx resources, the function resets the resource error flag.
2837 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2838 * ETH_QUEUE tx_queue Number of Tx queue.
2839 * PKT_INFO *p_pkt_info User packet buffer.
2842 * Tx ring 'first' and 'used' indexes are updated.
2845 * ETH_ERROR in case the routine can not access Tx desc ring.
2846 * ETH_RETRY in case there is transmission in process.
2847 * ETH_END_OF_JOB if the routine has nothing to release.
2850 *******************************************************************************/
2851 static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO *
2854 PKT_INFO * p_pkt_info)
2856 volatile ETH_TX_DESC *p_tx_desc_used = NULL;
2857 volatile ETH_TX_DESC *p_tx_desc_first = NULL;
2858 unsigned int command_status;
2861 /* Get the Tx Desc ring indexes */
2862 USED_TFD_GET (p_tx_desc_used, tx_queue);
2863 FIRST_TFD_GET (p_tx_desc_first, tx_queue);
2867 if (p_tx_desc_used == NULL)
2870 command_status = p_tx_desc_used->cmd_sts;
2872 /* Still transmitting... */
2873 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2874 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2878 /* Stop release. About to overlap the current available Tx descriptor */
2879 if ((p_tx_desc_used == p_tx_desc_first) &&
2880 (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) {
2881 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2882 return ETH_END_OF_JOB;
2885 /* Pass the packet information to the caller */
2886 p_pkt_info->cmd_sts = command_status;
2887 p_pkt_info->return_info = p_tx_desc_used->return_info;
2888 p_tx_desc_used->return_info = 0;
2890 /* Update the next descriptor to release. */
2891 USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue);
2893 /* Any Tx return cancels the Tx resource error status */
2894 if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true)
2895 p_eth_port_ctrl->tx_resource_err[tx_queue] = false;
2897 D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0);
2903 /*******************************************************************************
2904 * eth_port_receive - Get received information from Rx ring.
2907 * This routine returns the received data to the caller. There is no
2908 * data copying during routine operation. All information is returned
2909 * using pointer to packet information struct passed from the caller.
2910 * If the routine exhausts Rx ring resources then the resource error flag
2914 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2915 * ETH_QUEUE rx_queue Number of Rx queue.
2916 * PKT_INFO *p_pkt_info User packet buffer.
2919 * Rx ring current and used indexes are updated.
2922 * ETH_ERROR in case the routine can not access Rx desc ring.
2923 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2924 * ETH_END_OF_JOB if there is no received data.
2927 *******************************************************************************/
2928 static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl,
2930 PKT_INFO * p_pkt_info)
2932 volatile ETH_RX_DESC *p_rx_curr_desc;
2933 volatile ETH_RX_DESC *p_rx_next_curr_desc;
2934 volatile ETH_RX_DESC *p_rx_used_desc;
2935 unsigned int command_status;
2937 /* Do not process Rx ring in case of Rx ring resource error */
2938 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) {
2939 printf ("\nRx Queue is full ...\n");
2940 return ETH_QUEUE_FULL;
2943 /* Get the Rx Desc ring 'curr and 'used' indexes */
2944 CURR_RFD_GET (p_rx_curr_desc, rx_queue);
2945 USED_RFD_GET (p_rx_used_desc, rx_queue);
2948 if (p_rx_curr_desc == NULL)
2951 /* The following parameters are used to save readings from memory */
2952 p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue);
2953 command_status = p_rx_curr_desc->cmd_sts;
2955 /* Nothing to receive... */
2956 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
2957 /* DP(printf("Rx: command_status: %08x\n", command_status)); */
2958 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
2959 /* DP(printf("\nETH_END_OF_JOB ...\n"));*/
2960 return ETH_END_OF_JOB;
2963 p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET;
2964 p_pkt_info->cmd_sts = command_status;
2965 p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET;
2966 p_pkt_info->return_info = p_rx_curr_desc->return_info;
2967 p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */
2969 /* Clean the return info field to indicate that the packet has been */
2970 /* moved to the upper layers */
2971 p_rx_curr_desc->return_info = 0;
2973 /* Update 'curr' in data structure */
2974 CURR_RFD_SET (p_rx_next_curr_desc, rx_queue);
2976 /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */
2977 if (p_rx_next_curr_desc == p_rx_used_desc)
2978 p_eth_port_ctrl->rx_resource_err[rx_queue] = true;
2980 D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0);
2985 /*******************************************************************************
2986 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2989 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2990 * next 'used' descriptor and attached the returned buffer to it.
2991 * In case the Rx ring was in "resource error" condition, where there are
2992 * no available Rx resources, the function resets the resource error flag.
2995 * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct.
2996 * ETH_QUEUE rx_queue Number of Rx queue.
2997 * PKT_INFO *p_pkt_info Information on the returned buffer.
3000 * New available Rx resource in Rx descriptor ring.
3003 * ETH_ERROR in case the routine can not access Rx desc ring.
3006 *******************************************************************************/
3007 static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO *
3010 PKT_INFO * p_pkt_info)
3012 volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */
3014 /* Get 'used' Rx descriptor */
3015 USED_RFD_GET (p_used_rx_desc, rx_queue);
3018 if (p_used_rx_desc == NULL)
3021 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
3022 p_used_rx_desc->return_info = p_pkt_info->return_info;
3023 p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt;
3024 p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */
3026 /* Flush the write pipe */
3029 /* Return the descriptor to DMA ownership */
3030 p_used_rx_desc->cmd_sts =
3031 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
3033 /* Flush descriptor and CPU pipe */
3034 D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0);
3037 /* Move the used descriptor pointer to the next descriptor */
3038 USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue);
3040 /* Any Rx return cancels the Rx resource error status */
3041 if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true)
3042 p_eth_port_ctrl->rx_resource_err[rx_queue] = false;
3047 /*******************************************************************************
3048 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
3051 * This routine sets the RX coalescing interrupt mechanism parameter.
3052 * This parameter is a timeout counter, that counts in 64 t_clk
3053 * chunks ; that when timeout event occurs a maskable interrupt
3055 * The parameter is calculated using the tClk of the MV-643xx chip
3056 * , and the required delay of the interrupt in usec.
3059 * ETH_PORT eth_port_num Ethernet port number
3060 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3061 * unsigned int delay Delay in usec
3064 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3067 * The interrupt coalescing value set in the gigE port.
3069 *******************************************************************************/
3071 static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num,
3077 coal = ((t_clk / 1000000) * delay) / 64;
3078 /* Set RX Coalescing mechanism */
3079 MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num),
3080 ((coal & 0x3fff) << 8) |
3082 (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num))
3088 /*******************************************************************************
3089 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
3092 * This routine sets the TX coalescing interrupt mechanism parameter.
3093 * This parameter is a timeout counter, that counts in 64 t_clk
3094 * chunks ; that when timeout event occurs a maskable interrupt
3096 * The parameter is calculated using the t_cLK frequency of the
3097 * MV-643xx chip and the required delay in the interrupt in uSec
3100 * ETH_PORT eth_port_num Ethernet port number
3101 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
3102 * unsigned int delay Delay in uSeconds
3105 * Interrupt coalescing mechanism value is set in MV-643xx chip.
3108 * The interrupt coalescing value set in the gigE port.
3110 *******************************************************************************/
3112 static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num,
3118 coal = ((t_clk / 1000000) * delay) / 64;
3119 /* Set TX Coalescing mechanism */
3120 MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num),
3126 /*******************************************************************************
3127 * eth_b_copy - Copy bytes from source to destination
3130 * This function supports the eight bytes limitation on Tx buffer size.
3131 * The routine will zero eight bytes starting from the destination address
3132 * followed by copying bytes from the source address to the destination.
3135 * unsigned int src_addr 32 bit source address.
3136 * unsigned int dst_addr 32 bit destination address.
3137 * int byte_count Number of bytes to copy.
3145 *******************************************************************************/
3146 static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr,
3149 /* Zero the dst_addr area */
3150 *(unsigned int *) dst_addr = 0x0;
3152 while (byte_count != 0) {
3153 *(char *) dst_addr = *(char *) src_addr;