3 * Ingo Assmus <ingo.assmus@keymile.com>
5 * based on - Driver for MV64360X ethernet ports
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * mv_eth.h - header file for the polled mode GT ethernet driver
31 #ifndef __DB64360_ETH_H__
32 #define __DB64360_ETH_H__
34 #include <asm/types.h>
36 #include <asm/byteorder.h>
40 #include <asm/errno.h>
42 /*************************************************************************
43 **************************************************************************
44 **************************************************************************
45 * The first part is the high level driver of the gigE ethernet ports. *
46 **************************************************************************
47 **************************************************************************
48 *************************************************************************/
56 /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
58 #define MAX_SKB_FRAGS 0
62 /*#define MAX_RX_QUEUE_NUM 8*/
63 /*#define MAX_TX_QUEUE_NUM 8*/
64 #define MAX_RX_QUEUE_NUM 1
65 #define MAX_TX_QUEUE_NUM 1
68 /* Use one TX queue and one RX queue */
69 #define MV64360_TX_QUEUE_NUM 1
70 #define MV64360_RX_QUEUE_NUM 1
73 * Number of RX / TX descriptors on RX / TX rings.
74 * Note that allocating RX descriptors is done by allocating the RX
75 * ring AND a preallocated RX buffers (skb's) for each descriptor.
76 * The TX descriptors only allocates the TX descriptors ring,
77 * with no pre allocated TX buffers (skb's are allocated by higher layers.
80 /* Default TX ring size is 10 descriptors */
81 #ifdef CONFIG_MV64360_ETH_TXQUEUE_SIZE
82 #define MV64360_TX_QUEUE_SIZE CONFIG_MV64360_ETH_TXQUEUE_SIZE
84 #define MV64360_TX_QUEUE_SIZE 4
87 /* Default RX ring size is 4 descriptors */
88 #ifdef CONFIG_MV64360_ETH_RXQUEUE_SIZE
89 #define MV64360_RX_QUEUE_SIZE CONFIG_MV64360_ETH_RXQUEUE_SIZE
91 #define MV64360_RX_QUEUE_SIZE 4
94 #ifdef CONFIG_RX_BUFFER_SIZE
95 #define MV64360_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
97 #define MV64360_RX_BUFFER_SIZE 1600
100 #ifdef CONFIG_TX_BUFFER_SIZE
101 #define MV64360_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
103 #define MV64360_TX_BUFFER_SIZE 1600
108 * Network device statistics. Akin to the 2.0 ether stats but
109 * with byte counters.
112 struct net_device_stats
114 unsigned long rx_packets; /* total packets received */
115 unsigned long tx_packets; /* total packets transmitted */
116 unsigned long rx_bytes; /* total bytes received */
117 unsigned long tx_bytes; /* total bytes transmitted */
118 unsigned long rx_errors; /* bad packets received */
119 unsigned long tx_errors; /* packet transmit problems */
120 unsigned long rx_dropped; /* no space in linux buffers */
121 unsigned long tx_dropped; /* no space available in linux */
122 unsigned long multicast; /* multicast packets received */
123 unsigned long collisions;
125 /* detailed rx_errors: */
126 unsigned long rx_length_errors;
127 unsigned long rx_over_errors; /* receiver ring buff overflow */
128 unsigned long rx_crc_errors; /* recved pkt with crc error */
129 unsigned long rx_frame_errors; /* recv'd frame alignment error */
130 unsigned long rx_fifo_errors; /* recv'r fifo overrun */
131 unsigned long rx_missed_errors; /* receiver missed packet */
133 /* detailed tx_errors */
134 unsigned long tx_aborted_errors;
135 unsigned long tx_carrier_errors;
136 unsigned long tx_fifo_errors;
137 unsigned long tx_heartbeat_errors;
138 unsigned long tx_window_errors;
141 unsigned long rx_compressed;
142 unsigned long tx_compressed;
146 /* Private data structure used for ethernet device */
147 struct mv64360_eth_priv {
148 unsigned int port_num;
149 struct net_device_stats *stats;
151 /* to buffer area aligned */
152 char * p_eth_tx_buffer[MV64360_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
153 char * p_eth_rx_buffer[MV64360_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
155 /* Size of Tx Ring per queue */
156 unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
159 /* Size of Rx Ring per queue */
160 unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
162 /* Magic Number for Ethernet running */
163 unsigned int eth_running;
168 int mv64360_eth_init (struct eth_device *dev);
169 int mv64360_eth_stop (struct eth_device *dev);
170 int mv64360_eth_start_xmit(struct eth_device *dev, void *packet, int length);
171 int mv64360_eth_open (struct eth_device *dev);
174 /*************************************************************************
175 **************************************************************************
176 **************************************************************************
177 * The second part is the low level driver of the gigE ethernet ports. *
178 **************************************************************************
179 **************************************************************************
180 *************************************************************************/
183 /********************************************************************************
184 * Header File for : MV-643xx network interface header
187 * This header file contains macros typedefs and function declaration for
188 * the Marvell Gig Bit Ethernet Controller.
193 *******************************************************************************/
196 #ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
197 #ifdef CONFIG_MV64360_SRAM_CACHEABLE
198 /* In case SRAM is cacheable but not cache coherent */
199 #define D_CACHE_FLUSH_LINE(addr, offset) \
201 __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
204 /* In case SRAM is cache coherent or non-cacheable */
205 #define D_CACHE_FLUSH_LINE(addr, offset) ;
208 #ifdef CONFIG_NOT_COHERENT_CACHE
209 /* In case of descriptors on DDR but not cache coherent */
210 #define D_CACHE_FLUSH_LINE(addr, offset) \
212 __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
215 /* In case of descriptors on DDR and cache coherent */
216 #define D_CACHE_FLUSH_LINE(addr, offset) ;
217 #endif /* CONFIG_NOT_COHERENT_CACHE */
218 #endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
221 #define CPU_PIPE_FLUSH \
223 __asm__ __volatile__ ("eieio"); \
229 /* Default port configuration value */
230 #define PORT_CONFIG_VALUE \
231 ETH_UNICAST_NORMAL_MODE | \
232 ETH_DEFAULT_RX_QUEUE_0 | \
233 ETH_DEFAULT_RX_ARP_QUEUE_0 | \
234 ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
235 ETH_RECEIVE_BC_IF_IP | \
236 ETH_RECEIVE_BC_IF_ARP | \
237 ETH_CAPTURE_TCP_FRAMES_DIS | \
238 ETH_CAPTURE_UDP_FRAMES_DIS | \
239 ETH_DEFAULT_RX_TCP_QUEUE_0 | \
240 ETH_DEFAULT_RX_UDP_QUEUE_0 | \
241 ETH_DEFAULT_RX_BPDU_QUEUE_0
243 /* Default port extend configuration value */
244 #define PORT_CONFIG_EXTEND_VALUE \
245 ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
246 ETH_PARTITION_DISABLE
249 /* Default sdma control value */
250 #ifdef CONFIG_NOT_COHERENT_CACHE
251 #define PORT_SDMA_CONFIG_VALUE \
252 ETH_RX_BURST_SIZE_16_64BIT | \
253 GT_ETH_IPG_INT_RX(0) | \
254 ETH_TX_BURST_SIZE_16_64BIT;
256 #define PORT_SDMA_CONFIG_VALUE \
257 ETH_RX_BURST_SIZE_4_64BIT | \
258 GT_ETH_IPG_INT_RX(0) | \
259 ETH_TX_BURST_SIZE_4_64BIT;
262 #define GT_ETH_IPG_INT_RX(value) \
263 ((value & 0x3fff) << 8)
265 /* Default port serial control value */
266 #define PORT_SERIAL_CONTROL_VALUE \
267 ETH_FORCE_LINK_PASS | \
268 ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
269 ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
270 ETH_ADV_SYMMETRIC_FLOW_CTRL | \
271 ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
272 ETH_FORCE_BP_MODE_NO_JAM | \
274 ETH_DO_NOT_FORCE_LINK_FAIL | \
275 ETH_RETRANSMIT_16_ETTEMPTS | \
276 ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
278 ETH_DISABLE_AUTO_NEG_BYPASS | \
279 ETH_AUTO_NEG_NO_CHANGE | \
280 ETH_MAX_RX_PACKET_1552BYTE | \
281 ETH_CLR_EXT_LOOPBACK | \
282 ETH_SET_FULL_DUPLEX_MODE | \
283 ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
285 #define RX_BUFFER_MAX_SIZE 0xFFFF
286 #define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
288 #define RX_BUFFER_MIN_SIZE 0x8
289 #define TX_BUFFER_MIN_SIZE 0x8
291 /* Tx WRR confoguration macros */
292 #define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
293 #define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
294 #define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
296 /* MAC accepet/reject macros */
297 #define ACCEPT_MAC_ADDR 0
298 #define REJECT_MAC_ADDR 1
300 /* Size of a Tx/Rx descriptor used in chain list data structure */
301 #define RX_DESC_ALIGNED_SIZE 0x20
302 #define TX_DESC_ALIGNED_SIZE 0x20
304 /* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
305 #define TX_BUF_OFFSET_IN_DESC 0x18
306 /* Buffer offset from buffer pointer */
307 #define RX_BUF_OFFSET 0x2
310 #define ETH_BAR_GAP 0x8
311 #define ETH_SIZE_REG_GAP 0x8
312 #define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
313 #define ETH_PORT_ACCESS_CTRL_GAP 0x4
315 /* Gigabit Ethernet Unit Global Registers */
317 /* MIB Counters register definitions */
318 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
319 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
320 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
321 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
322 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
323 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
324 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
325 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
326 #define ETH_MIB_FRAMES_64_OCTETS 0x20
327 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
328 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
329 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
330 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
331 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
332 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
333 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
334 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
335 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
336 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
337 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
338 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
339 #define ETH_MIB_FC_SENT 0x54
340 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
341 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
342 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
343 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
344 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
345 #define ETH_MIB_JABBER_RECEIVED 0x6c
346 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
347 #define ETH_MIB_BAD_CRC_EVENT 0x74
348 #define ETH_MIB_COLLISION 0x78
349 #define ETH_MIB_LATE_COLLISION 0x7c
351 /* Port serial status reg (PSR) */
352 #define ETH_INTERFACE_GMII_MII 0
353 #define ETH_INTERFACE_PCM BIT0
354 #define ETH_LINK_IS_DOWN 0
355 #define ETH_LINK_IS_UP BIT1
356 #define ETH_PORT_AT_HALF_DUPLEX 0
357 #define ETH_PORT_AT_FULL_DUPLEX BIT2
358 #define ETH_RX_FLOW_CTRL_DISABLED 0
359 #define ETH_RX_FLOW_CTRL_ENBALED BIT3
360 #define ETH_GMII_SPEED_100_10 0
361 #define ETH_GMII_SPEED_1000 BIT4
362 #define ETH_MII_SPEED_10 0
363 #define ETH_MII_SPEED_100 BIT5
365 #define ETH_TX_IN_PROGRESS BIT7
366 #define ETH_BYPASS_NO_ACTIVE 0
367 #define ETH_BYPASS_ACTIVE BIT8
368 #define ETH_PORT_NOT_AT_PARTITION_STATE 0
369 #define ETH_PORT_AT_PARTITION_STATE BIT9
370 #define ETH_PORT_TX_FIFO_NOT_EMPTY 0
371 #define ETH_PORT_TX_FIFO_EMPTY BIT10
374 /* These macros describes the Port configuration reg (Px_cR) bits */
375 #define ETH_UNICAST_NORMAL_MODE 0
376 #define ETH_UNICAST_PROMISCUOUS_MODE BIT0
377 #define ETH_DEFAULT_RX_QUEUE_0 0
378 #define ETH_DEFAULT_RX_QUEUE_1 BIT1
379 #define ETH_DEFAULT_RX_QUEUE_2 BIT2
380 #define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
381 #define ETH_DEFAULT_RX_QUEUE_4 BIT3
382 #define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
383 #define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
384 #define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
385 #define ETH_DEFAULT_RX_ARP_QUEUE_0 0
386 #define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
387 #define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
388 #define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
389 #define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
390 #define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
391 #define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
392 #define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
393 #define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
394 #define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
395 #define ETH_RECEIVE_BC_IF_IP 0
396 #define ETH_REJECT_BC_IF_IP BIT8
397 #define ETH_RECEIVE_BC_IF_ARP 0
398 #define ETH_REJECT_BC_IF_ARP BIT9
399 #define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
400 #define ETH_CAPTURE_TCP_FRAMES_DIS 0
401 #define ETH_CAPTURE_TCP_FRAMES_EN BIT14
402 #define ETH_CAPTURE_UDP_FRAMES_DIS 0
403 #define ETH_CAPTURE_UDP_FRAMES_EN BIT15
404 #define ETH_DEFAULT_RX_TCP_QUEUE_0 0
405 #define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
406 #define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
407 #define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
408 #define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
409 #define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
410 #define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
411 #define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
412 #define ETH_DEFAULT_RX_UDP_QUEUE_0 0
413 #define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
414 #define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
415 #define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
416 #define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
417 #define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
418 #define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
419 #define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
420 #define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
421 #define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
422 #define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
423 #define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
424 #define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
425 #define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
426 #define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
427 #define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
430 /* These macros describes the Port configuration extend reg (Px_cXR) bits*/
431 #define ETH_CLASSIFY_EN BIT0
432 #define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
433 #define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
434 #define ETH_PARTITION_DISABLE 0
435 #define ETH_PARTITION_ENABLE BIT2
438 /* Tx/Rx queue command reg (RQCR/TQCR)*/
439 #define ETH_QUEUE_0_ENABLE BIT0
440 #define ETH_QUEUE_1_ENABLE BIT1
441 #define ETH_QUEUE_2_ENABLE BIT2
442 #define ETH_QUEUE_3_ENABLE BIT3
443 #define ETH_QUEUE_4_ENABLE BIT4
444 #define ETH_QUEUE_5_ENABLE BIT5
445 #define ETH_QUEUE_6_ENABLE BIT6
446 #define ETH_QUEUE_7_ENABLE BIT7
447 #define ETH_QUEUE_0_DISABLE BIT8
448 #define ETH_QUEUE_1_DISABLE BIT9
449 #define ETH_QUEUE_2_DISABLE BIT10
450 #define ETH_QUEUE_3_DISABLE BIT11
451 #define ETH_QUEUE_4_DISABLE BIT12
452 #define ETH_QUEUE_5_DISABLE BIT13
453 #define ETH_QUEUE_6_DISABLE BIT14
454 #define ETH_QUEUE_7_DISABLE BIT15
457 /* These macros describes the Port Sdma configuration reg (SDCR) bits */
458 #define ETH_RIFB BIT0
459 #define ETH_RX_BURST_SIZE_1_64BIT 0
460 #define ETH_RX_BURST_SIZE_2_64BIT BIT1
461 #define ETH_RX_BURST_SIZE_4_64BIT BIT2
462 #define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
463 #define ETH_RX_BURST_SIZE_16_64BIT BIT3
464 #define ETH_BLM_RX_NO_SWAP BIT4
465 #define ETH_BLM_RX_BYTE_SWAP 0
466 #define ETH_BLM_TX_NO_SWAP BIT5
467 #define ETH_BLM_TX_BYTE_SWAP 0
468 #define ETH_DESCRIPTORS_BYTE_SWAP BIT6
469 #define ETH_DESCRIPTORS_NO_SWAP 0
470 #define ETH_TX_BURST_SIZE_1_64BIT 0
471 #define ETH_TX_BURST_SIZE_2_64BIT BIT22
472 #define ETH_TX_BURST_SIZE_4_64BIT BIT23
473 #define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
474 #define ETH_TX_BURST_SIZE_16_64BIT BIT24
477 /* These macros describes the Port serial control reg (PSCR) bits */
478 #define ETH_SERIAL_PORT_DISABLE 0
479 #define ETH_SERIAL_PORT_ENABLE BIT0
480 #define ETH_FORCE_LINK_PASS BIT1
481 #define ETH_DO_NOT_FORCE_LINK_PASS 0
482 #define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
483 #define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
484 #define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
485 #define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
486 #define ETH_ADV_NO_FLOW_CTRL 0
487 #define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
488 #define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
489 #define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
490 #define ETH_FORCE_BP_MODE_NO_JAM 0
491 #define ETH_FORCE_BP_MODE_JAM_TX BIT7
492 #define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
493 #define ETH_FORCE_LINK_FAIL 0
494 #define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
495 #define ETH_RETRANSMIT_16_ETTEMPTS 0
496 #define ETH_RETRANSMIT_FOREVER BIT11
497 #define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
498 #define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
499 #define ETH_DTE_ADV_0 0
500 #define ETH_DTE_ADV_1 BIT14
501 #define ETH_DISABLE_AUTO_NEG_BYPASS 0
502 #define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
503 #define ETH_AUTO_NEG_NO_CHANGE 0
504 #define ETH_RESTART_AUTO_NEG BIT16
505 #define ETH_MAX_RX_PACKET_1518BYTE 0
506 #define ETH_MAX_RX_PACKET_1522BYTE BIT17
507 #define ETH_MAX_RX_PACKET_1552BYTE BIT18
508 #define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
509 #define ETH_MAX_RX_PACKET_9192BYTE BIT19
510 #define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
511 #define ETH_SET_EXT_LOOPBACK BIT20
512 #define ETH_CLR_EXT_LOOPBACK 0
513 #define ETH_SET_FULL_DUPLEX_MODE BIT21
514 #define ETH_SET_HALF_DUPLEX_MODE 0
515 #define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
516 #define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
517 #define ETH_SET_GMII_SPEED_TO_10_100 0
518 #define ETH_SET_GMII_SPEED_TO_1000 BIT23
519 #define ETH_SET_MII_SPEED_TO_10 0
520 #define ETH_SET_MII_SPEED_TO_100 BIT24
524 #define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
525 #define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
526 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
527 #define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
529 /* SDMA command status fields macros */
531 /* Tx & Rx descriptors status */
532 #define ETH_ERROR_SUMMARY (BIT0)
534 /* Tx & Rx descriptors command */
535 #define ETH_BUFFER_OWNED_BY_DMA (BIT31)
537 /* Tx descriptors status */
538 #define ETH_LC_ERROR (0 )
539 #define ETH_UR_ERROR (BIT1 )
540 #define ETH_RL_ERROR (BIT2 )
541 #define ETH_LLC_SNAP_FORMAT (BIT9 )
543 /* Rx descriptors status */
544 #define ETH_CRC_ERROR (0 )
545 #define ETH_OVERRUN_ERROR (BIT1 )
546 #define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
547 #define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
548 #define ETH_VLAN_TAGGED (BIT19)
549 #define ETH_BPDU_FRAME (BIT20)
550 #define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
551 #define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
552 #define ETH_OTHER_FRAME_TYPE (BIT22)
553 #define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
554 #define ETH_FRAME_TYPE_IP_V_4 (BIT24)
555 #define ETH_FRAME_HEADER_OK (BIT25)
556 #define ETH_RX_LAST_DESC (BIT26)
557 #define ETH_RX_FIRST_DESC (BIT27)
558 #define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
559 #define ETH_RX_ENABLE_INTERRUPT (BIT29)
560 #define ETH_LAYER_4_CHECKSUM_OK (BIT30)
562 /* Rx descriptors byte count */
563 #define ETH_FRAME_FRAGMENTED (BIT2)
565 /* Tx descriptors command */
566 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
567 #define ETH_FRAME_SET_TO_VLAN (BIT15)
568 #define ETH_TCP_FRAME (0 )
569 #define ETH_UDP_FRAME (BIT16)
570 #define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
571 #define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
572 #define ETH_ZERO_PADDING (BIT19)
573 #define ETH_TX_LAST_DESC (BIT20)
574 #define ETH_TX_FIRST_DESC (BIT21)
575 #define ETH_GEN_CRC (BIT22)
576 #define ETH_TX_ENABLE_INTERRUPT (BIT23)
577 #define ETH_AUTO_MODE (BIT30)
579 /* Address decode parameters */
580 /* Ethernet Base Address Register bits */
581 #define EBAR_TARGET_DRAM 0x00000000
582 #define EBAR_TARGET_DEVICE 0x00000001
583 #define EBAR_TARGET_CBS 0x00000002
584 #define EBAR_TARGET_PCI0 0x00000003
585 #define EBAR_TARGET_PCI1 0x00000004
586 #define EBAR_TARGET_CUNIT 0x00000005
587 #define EBAR_TARGET_AUNIT 0x00000006
588 #define EBAR_TARGET_GUNIT 0x00000007
590 /* Window attributes */
591 #define EBAR_ATTR_DRAM_CS0 0x00000E00
592 #define EBAR_ATTR_DRAM_CS1 0x00000D00
593 #define EBAR_ATTR_DRAM_CS2 0x00000B00
594 #define EBAR_ATTR_DRAM_CS3 0x00000700
596 /* DRAM Target interface */
597 #define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
598 #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
599 #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
601 /* Device Bus Target interface */
602 #define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
603 #define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
604 #define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
605 #define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
606 #define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
608 /* PCI Target interface */
609 #define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
610 #define EBAR_ATTR_PCI_NO_SWAP 0x00000100
611 #define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
612 #define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
613 #define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
614 #define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
615 #define EBAR_ATTR_PCI_IO_SPACE 0x00000000
616 #define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
617 #define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
618 #define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
620 /* CPU 60x bus or internal SRAM interface */
621 #define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
622 #define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
623 #define EBAR_ATTR_CBS_SRAM 0x00000000
624 #define EBAR_ATTR_CBS_CPU_BUS 0x00000800
626 /* Window access control */
627 #define EWIN_ACCESS_NOT_ALLOWED 0
628 #define EWIN_ACCESS_READ_ONLY BIT0
629 #define EWIN_ACCESS_FULL (BIT1 | BIT0)
630 #define EWIN0_ACCESS_MASK 0x0003
631 #define EWIN1_ACCESS_MASK 0x000C
632 #define EWIN2_ACCESS_MASK 0x0030
633 #define EWIN3_ACCESS_MASK 0x00C0
637 typedef enum _eth_port
644 typedef enum _eth_func_ret_status
646 ETH_OK, /* Returned as expected. */
647 ETH_ERROR, /* Fundamental error. */
648 ETH_RETRY, /* Could not process request. Try later. */
649 ETH_END_OF_JOB, /* Ring has nothing to process. */
650 ETH_QUEUE_FULL, /* Ring resource error. */
651 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
652 }ETH_FUNC_RET_STATUS;
654 typedef enum _eth_queue
666 typedef enum _addr_win
676 typedef enum _eth_target
685 typedef struct _eth_rx_desc
687 unsigned short byte_cnt ; /* Descriptor buffer byte count */
688 unsigned short buf_size ; /* Buffer size */
689 unsigned int cmd_sts ; /* Descriptor command status */
690 unsigned int next_desc_ptr; /* Next descriptor pointer */
691 unsigned int buf_ptr ; /* Descriptor buffer pointer */
692 unsigned int return_info ; /* User resource return information */
696 typedef struct _eth_tx_desc
698 unsigned short byte_cnt ; /* Descriptor buffer byte count */
699 unsigned short l4i_chk ; /* CPU provided TCP Checksum */
700 unsigned int cmd_sts ; /* Descriptor command status */
701 unsigned int next_desc_ptr; /* Next descriptor pointer */
702 unsigned int buf_ptr ; /* Descriptor buffer pointer */
703 unsigned int return_info ; /* User resource return information */
706 /* Unified struct for Rx and Tx operations. The user is not required to */
707 /* be familier with neither Tx nor Rx descriptors. */
708 typedef struct _pkt_info
710 unsigned short byte_cnt ; /* Descriptor buffer byte count */
711 unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
712 unsigned int cmd_sts ; /* Descriptor command status */
713 unsigned int buf_ptr ; /* Descriptor buffer pointer */
714 unsigned int return_info ; /* User resource return information */
718 typedef struct _eth_win_param
720 ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
721 ETH_TARGET target; /* System targets. See ETH_TARGET enum */
722 unsigned short attributes; /* BAR attributes. See above macros. */
723 unsigned int base_addr; /* Window base address in unsigned int form */
724 unsigned int high_addr; /* Window high address in unsigned int form */
725 unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
726 bool enable; /* Enable/disable access to the window. */
727 unsigned short access_ctrl; /* Access ctrl register. see above macros */
731 /* Ethernet port specific infomation */
733 typedef struct _eth_port_ctrl
735 ETH_PORT port_num; /* User Ethernet port number */
736 int port_phy_addr; /* User phy address of Ethrnet port */
737 unsigned char port_mac_addr[6]; /* User defined port MAC address. */
738 unsigned int port_config; /* User port configuration value */
739 unsigned int port_config_extend; /* User port config extend value */
740 unsigned int port_sdma_config; /* User port SDMA config value */
741 unsigned int port_serial_control; /* User port serial control value */
742 unsigned int port_tx_queue_command; /* Port active Tx queues summary */
743 unsigned int port_rx_queue_command; /* Port active Rx queues summary */
745 /* User function to cast virtual address to CPU bus address */
746 unsigned int (*port_virt_to_phys)(unsigned int addr);
747 /* User scratch pad for user specific data structures */
750 bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
751 bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
753 /* Tx/Rx rings managment indexes fields. For driver use */
755 /* Next available Rx resource */
756 volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
757 /* Returning Rx resource */
758 volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
760 /* Next available Tx resource */
761 volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
762 /* Returning Tx resource */
763 volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
764 /* An extra Tx index to support transmit of multiple buffers per packet */
765 volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
767 /* Tx/Rx rings size and base variables fields. For driver use */
769 volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
770 unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
771 char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
773 volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
774 unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
775 char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
780 /* ethernet.h API list */
782 /* Port operation control routines */
783 static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
784 static void eth_port_reset(ETH_PORT eth_port_num);
785 static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
788 /* Port MAC address routines */
789 static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
790 unsigned char *p_addr,
793 static void eth_port_mc_addr (ETH_PORT eth_port_num,
794 unsigned char *p_addr,
799 /* PHY and MIB routines */
800 static bool ethernet_phy_reset(ETH_PORT eth_port_num);
802 static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
803 unsigned int phy_reg,
806 static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
807 unsigned int phy_reg,
808 unsigned int* value);
810 static void eth_clear_mib_counters(ETH_PORT eth_port_num);
812 /* Port data flow control routines */
813 static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
815 PKT_INFO *p_pkt_info);
816 static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
818 PKT_INFO *p_pkt_info);
819 static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
821 PKT_INFO *p_pkt_info);
822 static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
824 PKT_INFO *p_pkt_info);
827 static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
831 unsigned int tx_desc_base_addr,
832 unsigned int tx_buff_base_addr);
834 static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
838 unsigned int rx_desc_base_addr,
839 unsigned int rx_buff_base_addr);
841 #endif /* MV64360_ETH_ */