3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 /*************************************************************************
9 * adaption for the Marvell DB64460 Board
10 * Ingo Assmus (ingo.assmus@keymile.com)
11 ************************************************************************/
14 /* sdram_init.c - automatic memory sizing */
18 #include "../include/memory.h"
19 #include "../include/pci.h"
20 #include "../include/mv_gen_reg.h"
25 #include "../common/i2c.h"
29 DECLARE_GLOBAL_DATA_PTR;
33 int set_dfcdlInit (void); /* setup delay line of Mv64460 */
34 int mvDmaIsChannelActive (int);
35 int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong);
36 int mvDmaTransfer (int, ulong, ulong, ulong, ulong);
38 /* ------------------------------------------------------------------------- */
41 memory_map_bank (unsigned int bankNo,
42 unsigned int bankBase, unsigned int bankLength)
50 debug("mapping bank %d at %08x - %08x\n",
51 bankNo, bankBase, bankBase + bankLength - 1);
53 debug("unmapping bank %d\n", bankNo);
56 memoryMapBank (bankNo, bankBase, bankLength);
59 for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
64 READ_LINE_AGGRESSIVE_PREFETCH |
65 READ_MULTI_AGGRESSIVE_PREFETCH |
66 MAX_BURST_4 | PCI_NO_SWAP;
68 pciMapMemoryBank (host, bankNo, bankBase, bankLength);
70 pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
73 pciSetRegionFeatures (host, bankNo, features, bankBase,
82 /* much of this code is based on (or is) the code in the pip405 port */
83 /* thanks go to the authors of said port - Josh */
85 /* structure to store the relevant information about an sdram bank */
86 typedef struct sdram_info {
88 uchar registered, ecc;
95 /* Typedefs for 'gtAuxilGetDIMMinfo' function */
97 typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE;
99 typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
100 SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
103 typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 =
104 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 =
105 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR;
106 typedef enum _max_CL_supported_SD { SD_CL_1 =
107 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7,
108 SD_FAULT } MAX_CL_SUPPORTED_SD;
111 /* SDRAM/DDR information struct */
112 typedef struct _gtMemoryDimmInfo {
113 MEMORY_TYPE memoryType;
114 unsigned int numOfRowAddresses;
115 unsigned int numOfColAddresses;
116 unsigned int numOfModuleBanks;
117 unsigned int dataWidth;
118 VOLTAGE_INTERFACE voltageInterface;
119 unsigned int errorCheckType; /* ECC , PARITY.. */
120 unsigned int sdramWidth; /* 4,8,16 or 32 */ ;
121 unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */
122 unsigned int minClkDelay;
123 unsigned int burstLengthSupported;
124 unsigned int numOfBanksOnEachDevice;
125 unsigned int suportedCasLatencies;
126 unsigned int RefreshInterval;
127 unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */
128 unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */
129 MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
130 MAX_CL_SUPPORTED_SD maxClSupported_SD;
131 unsigned int moduleBankDensity;
132 /* module attributes (true for yes) */
133 bool bufferedAddrAndControlInputs;
134 bool registeredAddrAndControlInputs;
136 bool bufferedDQMBinputs;
137 bool registeredDQMBinputs;
138 bool differentialClockInput;
139 bool redundantRowAddressing;
141 /* module general attributes */
142 bool suportedAutoPreCharge;
143 bool suportedPreChargeAll;
144 bool suportedEarlyRasPreCharge;
145 bool suportedWrite1ReadBurst;
146 bool suported5PercentLowVCC;
147 bool suported5PercentUpperVCC;
148 /* module timing parameters */
149 unsigned int minRasToCasDelay;
150 unsigned int minRowActiveRowActiveDelay;
151 unsigned int minRasPulseWidth;
152 unsigned int minRowPrechargeTime; /* measured in ns */
154 int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */
155 int addrAndCommandSetupTime; /* (measured in ns/100) */
156 int dataInputSetupTime; /* LoP left of point (measured in ns) */
157 int dataInputHoldTime; /* LoP left of point (measured in ns) */
158 /* tAC times for highest 2nd and 3rd highest CAS Latency values */
159 unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */
160 unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */
161 unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */
162 unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */
163 unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */
164 unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */
166 unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */
167 unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */
169 unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
170 unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
172 unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
173 unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
175 /* Parameters calculated from
176 the extracted DIMM information */
178 unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */
179 unsigned int numberOfDevices;
180 uchar drb_size; /* DRAM size in n*64Mbit */
181 uchar slot; /* Slot Number this module is inserted in */
182 uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */
184 uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */
185 uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */
186 uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */
187 unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */
188 unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */
189 unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */
190 uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */
197 * translate ns.ns/10 coding of SPD timing values
198 * into 10 ps unit values
200 static inline unsigned short NS10to10PS (unsigned char spd_byte)
202 unsigned short ns, ns10;
204 /* isolate upper nibble */
205 ns = (spd_byte >> 4) & 0x0F;
206 /* isolate lower nibble */
207 ns10 = (spd_byte & 0x0F);
209 return (ns * 100 + ns10 * 10);
213 * translate ns coding of SPD timing values
214 * into 10 ps unit values
216 static inline unsigned short NSto10PS (unsigned char spd_byte)
218 return (spd_byte * 100);
221 /* This code reads the SPD chip on the sdram and populates
222 * the array which is passed in with the relevant information */
223 /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
224 static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
226 unsigned long spd_checksum;
229 /* zero all the values */
230 memset (info, 0, sizeof (*info));
236 info->registered = 0;
237 info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */
239 info->tras_clocks = 5;
242 #ifdef CONFIG_MV64460_ECC
243 /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
244 dimmInfo->errorCheckType = 2;
252 uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
254 unsigned int i, j, density = 1;
259 unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
260 int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
261 uchar supp_cal, cal_val;
262 ulong memclk, tmemclk;
264 uchar trp_clocks = 0, tras_clocks;
267 memclk = gd->bus_clk;
268 tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */
270 debug("before i2c read\n");
272 ret = i2c_read (addr, 0, 1, data, 128);
274 debug("after i2c read\n");
276 /* zero all the values */
277 memset (dimmInfo, 0, sizeof (*dimmInfo));
279 /* copy the SPD content 1:1 into the dimmInfo structure */
280 for (i = 0; i <= 127; i++) {
281 dimmInfo->spd_raw_data[i] = data[i];
285 debug("No DIMM in slot %d [err = %x]\n", slot, ret);
288 dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */
290 #ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
292 for (i = 0; i <= 127; i++) {
293 printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
299 /* find Manufactura of Dimm Module */
300 for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
301 dimmInfo->manufactura[i] = data[64 + i];
303 printf ("\nThis RAM-Module is produced by: %s\n",
304 dimmInfo->manufactura);
306 /* find Manul-ID of Dimm Module */
307 for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
308 dimmInfo->modul_id[i] = data[73 + i];
310 printf ("The Module-ID of this RAM-Module is: %s\n",
313 /* find Vendor-Data of Dimm Module */
314 for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
315 dimmInfo->vendor_data[i] = data[99 + i];
317 printf ("Vendor Data of this RAM-Module is: %s\n",
318 dimmInfo->vendor_data);
320 /* find modul_serial_no of Dimm Module */
321 dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
322 printf ("Serial No. of this RAM-Module is: %ld (%lx)\n",
323 dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
325 /* find Manufac-Data of Dimm Module */
326 dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
327 printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */
329 /* find modul_revision of Dimm Module */
330 dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
331 printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */
333 /* find manufac_place of Dimm Module */
334 dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
335 printf ("manufac_place of this RAM-Module is: %d\n",
336 dimmInfo->manufac_place);
340 /*------------------------------------------------------------------------------------------------------------------------------*/
341 /* calculate SPD checksum */
342 /*------------------------------------------------------------------------------------------------------------------------------*/
345 for (i = 0; i <= 62; i++) {
346 spd_checksum += data[i];
349 if ((spd_checksum & 0xff) != data[63]) {
350 printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
355 printf ("SPD Checksum ok!\n");
358 /*------------------------------------------------------------------------------------------------------------------------------*/
359 for (i = 2; i <= 35; i++) {
361 case 2: /* Memory type (DDR / SDRAM) */
362 dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
364 if (dimmInfo->memoryType == 0)
366 ("Dram_type in slot %d is: SDRAM\n",
368 if (dimmInfo->memoryType == 1)
370 ("Dram_type in slot %d is: DDRAM\n",
374 /*------------------------------------------------------------------------------------------------------------------------------*/
376 case 3: /* Number Of Row Addresses */
377 dimmInfo->numOfRowAddresses = data[i];
379 ("Module Number of row addresses: %d\n",
380 dimmInfo->numOfRowAddresses);
382 /*------------------------------------------------------------------------------------------------------------------------------*/
384 case 4: /* Number Of Column Addresses */
385 dimmInfo->numOfColAddresses = data[i];
387 ("Module Number of col addresses: %d\n",
388 dimmInfo->numOfColAddresses);
390 /*------------------------------------------------------------------------------------------------------------------------------*/
392 case 5: /* Number Of Module Banks */
393 dimmInfo->numOfModuleBanks = data[i];
395 ("Number of Banks on Mod. : %d\n",
396 dimmInfo->numOfModuleBanks);
398 /*------------------------------------------------------------------------------------------------------------------------------*/
400 case 6: /* Data Width */
401 dimmInfo->dataWidth = data[i];
403 ("Module Data Width: %d\n",
404 dimmInfo->dataWidth);
406 /*------------------------------------------------------------------------------------------------------------------------------*/
408 case 8: /* Voltage Interface */
411 dimmInfo->voltageInterface = TTL_5V_TOLERANT;
413 ("Module is TTL_5V_TOLERANT\n");
416 dimmInfo->voltageInterface = LVTTL;
418 ("Module is LVTTL\n");
421 dimmInfo->voltageInterface = HSTL_1_5V;
423 ("Module is TTL_5V_TOLERANT\n");
426 dimmInfo->voltageInterface = SSTL_3_3V;
428 ("Module is HSTL_1_5V\n");
431 dimmInfo->voltageInterface = SSTL_2_5V;
433 ("Module is SSTL_2_5V\n");
436 dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
438 ("Module is VOLTAGE_UNKNOWN\n");
442 /*------------------------------------------------------------------------------------------------------------------------------*/
444 case 9: /* Minimum Cycle Time At Max CasLatancy */
445 shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
446 mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
448 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
450 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
451 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
452 rightOfPoint = (data[i] & maskRightOfPoint) * mult;
453 dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
455 dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
458 ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n",
459 leftOfPoint, rightOfPoint);
461 /*------------------------------------------------------------------------------------------------------------------------------*/
463 case 10: /* Clock To Data Out */
464 div = (dimmInfo->memoryType == DDR) ? 100 : 10;
466 (((data[i] & 0xf0) >> 4) * 10) +
468 leftOfPoint = time_tmp / div;
469 rightOfPoint = time_tmp % div;
470 dimmInfo->clockToDataOut_LoP = leftOfPoint;
471 dimmInfo->clockToDataOut_RoP = rightOfPoint;
472 debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */
474 /*------------------------------------------------------------------------------------------------------------------------------*/
476 /*#ifdef CONFIG_ECC */
477 case 11: /* Error Check Type */
478 dimmInfo->errorCheckType = data[i];
480 ("Error Check Type (0=NONE): %d\n",
481 dimmInfo->errorCheckType);
484 /*------------------------------------------------------------------------------------------------------------------------------*/
486 case 12: /* Refresh Interval */
487 dimmInfo->RefreshInterval = data[i];
489 ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
490 dimmInfo->RefreshInterval);
492 /*------------------------------------------------------------------------------------------------------------------------------*/
494 case 13: /* Sdram Width */
495 dimmInfo->sdramWidth = data[i];
497 ("Sdram Width: %d\n",
498 dimmInfo->sdramWidth);
500 /*------------------------------------------------------------------------------------------------------------------------------*/
502 case 14: /* Error Check Data Width */
503 dimmInfo->errorCheckDataWidth = data[i];
505 ("Error Check Data Width: %d\n",
506 dimmInfo->errorCheckDataWidth);
508 /*------------------------------------------------------------------------------------------------------------------------------*/
510 case 15: /* Minimum Clock Delay */
511 dimmInfo->minClkDelay = data[i];
513 ("Minimum Clock Delay: %d\n",
514 dimmInfo->minClkDelay);
516 /*------------------------------------------------------------------------------------------------------------------------------*/
518 case 16: /* Burst Length Supported */
519 /******-******-******-*******
520 * bit3 | bit2 | bit1 | bit0 *
521 *******-******-******-*******
522 burst length = * 8 | 4 | 2 | 1 *
523 *****************************
525 If for example bit0 and bit2 are set, the burst
526 length supported are 1 and 4. */
528 dimmInfo->burstLengthSupported = data[i];
531 ("Burst Length Supported: ");
532 if (dimmInfo->burstLengthSupported & 0x01)
534 if (dimmInfo->burstLengthSupported & 0x02)
536 if (dimmInfo->burstLengthSupported & 0x04)
538 if (dimmInfo->burstLengthSupported & 0x08)
543 /*------------------------------------------------------------------------------------------------------------------------------*/
545 case 17: /* Number Of Banks On Each Device */
546 dimmInfo->numOfBanksOnEachDevice = data[i];
548 ("Number Of Banks On Each Chip: %d\n",
549 dimmInfo->numOfBanksOnEachDevice);
551 /*------------------------------------------------------------------------------------------------------------------------------*/
553 case 18: /* Suported Cas Latencies */
556 *******-******-******-******-******-******-******-*******
557 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
558 *******-******-******-******-******-******-******-*******
559 CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 *
560 *********************************************************
562 *******-******-******-******-******-******-******-*******
563 * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
564 *******-******-******-******-******-******-******-*******
565 CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 *
566 ********************************************************/
567 dimmInfo->suportedCasLatencies = data[i];
570 ("Suported Cas Latencies: (CL) ");
571 if (dimmInfo->memoryType == 0) { /* SDRAM */
572 for (k = 0; k <= 7; k++) {
574 suportedCasLatencies & (1 << k))
580 } else { /* DDR-RAM */
582 if (dimmInfo->suportedCasLatencies & 1)
584 if (dimmInfo->suportedCasLatencies & 2)
586 if (dimmInfo->suportedCasLatencies & 4)
588 if (dimmInfo->suportedCasLatencies & 8)
590 if (dimmInfo->suportedCasLatencies & 16)
592 if (dimmInfo->suportedCasLatencies & 32)
598 /* Calculating MAX CAS latency */
599 for (j = 7; j > 0; j--) {
601 suportedCasLatencies >> j) & 0x1) ==
603 switch (dimmInfo->memoryType) {
605 /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
609 ("Max. Cas Latencies (DDR): ERROR !!!\n");
618 ("Max. Cas Latencies (DDR): ERROR !!!\n");
627 ("Max. Cas Latencies (DDR): 3.5 clk's\n");
634 ("Max. Cas Latencies (DDR): 3 clk's \n");
641 ("Max. Cas Latencies (DDR): 2.5 clk's \n");
648 ("Max. Cas Latencies (DDR): 2 clk's \n");
655 ("Max. Cas Latencies (DDR): 1.5 clk's \n");
662 /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy
663 lower then our SDRAM cycle count, we won't be able to support this CAL
664 and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */
666 minimumCycleTimeAtMaxCasLatancy_LoP
668 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
671 minimumCycleTimeAtMaxCasLatancy_LoP
673 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
675 minimumCycleTimeAtMaxCasLatancy_RoP
677 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
686 ("*** Change actual Cas Latencies cause of minimumCycleTime n");
688 /* ronen - checkif the Dimm frequency compared to the Sysclock. */
690 minimumCycleTimeAtMaxCasLatancy_LoP
692 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
695 minimumCycleTimeAtMaxCasLatancy_LoP
697 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
699 minimumCycleTimeAtMaxCasLatancy_RoP
701 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
703 printf ("*********************************************************\n");
704 printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
705 printf ("*********************************************************\n");
710 maxCASlatencySupported_LoP
714 if (((5 * j) % 10) != 0)
716 maxCASlatencySupported_RoP
720 maxCASlatencySupported_RoP
723 ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
725 maxCASlatencySupported_LoP,
727 maxCASlatencySupported_RoP);
730 /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
731 dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */
733 ("Max. Cas Latencies (SD): %d\n",
737 maxCASlatencySupported_LoP
740 maxCASlatencySupported_RoP
743 ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
745 maxCASlatencySupported_LoP,
747 maxCASlatencySupported_RoP);
754 /*------------------------------------------------------------------------------------------------------------------------------*/
756 case 21: /* Buffered Address And Control Inputs */
757 debug("\nModul Attributes (SPD Byte 21): \n");
758 dimmInfo->bufferedAddrAndControlInputs =
760 dimmInfo->registeredAddrAndControlInputs =
761 (data[i] & BIT1) >> 1;
762 dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
763 dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
764 dimmInfo->registeredDQMBinputs =
765 (data[i] & BIT4) >> 4;
766 dimmInfo->differentialClockInput =
767 (data[i] & BIT5) >> 5;
768 dimmInfo->redundantRowAddressing =
769 (data[i] & BIT6) >> 6;
771 if (dimmInfo->bufferedAddrAndControlInputs == 1)
773 (" - Buffered Address/Control Input: Yes \n");
776 (" - Buffered Address/Control Input: No \n");
778 if (dimmInfo->registeredAddrAndControlInputs == 1)
780 (" - Registered Address/Control Input: Yes \n");
783 (" - Registered Address/Control Input: No \n");
785 if (dimmInfo->onCardPLL == 1)
787 (" - On-Card PLL (clock): Yes \n");
790 (" - On-Card PLL (clock): No \n");
792 if (dimmInfo->bufferedDQMBinputs == 1)
794 (" - Bufferd DQMB Inputs: Yes \n");
797 (" - Bufferd DQMB Inputs: No \n");
799 if (dimmInfo->registeredDQMBinputs == 1)
801 (" - Registered DQMB Inputs: Yes \n");
804 (" - Registered DQMB Inputs: No \n");
806 if (dimmInfo->differentialClockInput == 1)
808 (" - Differential Clock Input: Yes \n");
811 (" - Differential Clock Input: No \n");
813 if (dimmInfo->redundantRowAddressing == 1)
815 (" - redundant Row Addressing: Yes \n");
818 (" - redundant Row Addressing: No \n");
822 /*------------------------------------------------------------------------------------------------------------------------------*/
824 case 22: /* Suported AutoPreCharge */
825 debug("\nModul Attributes (SPD Byte 22): \n");
826 dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
827 dimmInfo->suportedAutoPreCharge =
828 (data[i] & BIT1) >> 1;
829 dimmInfo->suportedPreChargeAll =
830 (data[i] & BIT2) >> 2;
831 dimmInfo->suportedWrite1ReadBurst =
832 (data[i] & BIT3) >> 3;
833 dimmInfo->suported5PercentLowVCC =
834 (data[i] & BIT4) >> 4;
835 dimmInfo->suported5PercentUpperVCC =
836 (data[i] & BIT5) >> 5;
838 if (dimmInfo->suportedEarlyRasPreCharge == 1)
840 (" - Early Ras Precharge: Yes \n");
843 (" - Early Ras Precharge: No \n");
845 if (dimmInfo->suportedAutoPreCharge == 1)
847 (" - AutoPreCharge: Yes \n");
850 (" - AutoPreCharge: No \n");
852 if (dimmInfo->suportedPreChargeAll == 1)
854 (" - Precharge All: Yes \n");
857 (" - Precharge All: No \n");
859 if (dimmInfo->suportedWrite1ReadBurst == 1)
861 (" - Write 1/ReadBurst: Yes \n");
864 (" - Write 1/ReadBurst: No \n");
866 if (dimmInfo->suported5PercentLowVCC == 1)
868 (" - lower VCC tolerance: 5 Percent \n");
871 (" - lower VCC tolerance: 10 Percent \n");
873 if (dimmInfo->suported5PercentUpperVCC == 1)
875 (" - upper VCC tolerance: 5 Percent \n");
878 (" - upper VCC tolerance: 10 Percent \n");
882 /*------------------------------------------------------------------------------------------------------------------------------*/
884 case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
885 shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
886 mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
888 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
890 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
891 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
892 rightOfPoint = (data[i] & maskRightOfPoint) * mult;
893 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
895 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
897 debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
899 /*------------------------------------------------------------------------------------------------------------------------------*/
901 case 24: /* Clock To Data Out 2nd highest Cas Latency Value */
902 div = (dimmInfo->memoryType == DDR) ? 100 : 10;
904 (((data[i] & 0xf0) >> 4) * 10) +
906 leftOfPoint = time_tmp / div;
907 rightOfPoint = time_tmp % div;
908 dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
909 dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
911 ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n",
912 leftOfPoint, rightOfPoint);
914 /*------------------------------------------------------------------------------------------------------------------------------*/
916 case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
917 shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
918 mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
920 (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
922 (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
923 leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
924 rightOfPoint = (data[i] & maskRightOfPoint) * mult;
925 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
927 dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
929 debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
931 /*------------------------------------------------------------------------------------------------------------------------------*/
933 case 26: /* Clock To Data Out 3rd highest Cas Latency Value */
934 div = (dimmInfo->memoryType == DDR) ? 100 : 10;
936 (((data[i] & 0xf0) >> 4) * 10) +
938 leftOfPoint = time_tmp / div;
939 rightOfPoint = time_tmp % div;
940 dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
941 dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
943 ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n",
944 leftOfPoint, rightOfPoint);
946 /*------------------------------------------------------------------------------------------------------------------------------*/
948 case 27: /* Minimum Row Precharge Time */
949 shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
951 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
953 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
954 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
955 rightOfPoint = (data[i] & maskRightOfPoint) * 25;
957 dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */
959 (dimmInfo->minRowPrechargeTime +
960 (tmemclk - 1)) / tmemclk;
962 ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n",
963 tmemclk, tmemclk / 100, tmemclk % 100);
965 ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n",
966 leftOfPoint, rightOfPoint, trp_clocks);
968 /*------------------------------------------------------------------------------------------------------------------------------*/
970 case 28: /* Minimum Row Active to Row Active Time */
971 shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
973 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
975 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
976 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
977 rightOfPoint = (data[i] & maskRightOfPoint) * 25;
979 dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
981 ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n",
982 leftOfPoint, rightOfPoint, trp_clocks);
984 /*------------------------------------------------------------------------------------------------------------------------------*/
986 case 29: /* Minimum Ras-To-Cas Delay */
987 shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
989 (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
991 (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
992 leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
993 rightOfPoint = (data[i] & maskRightOfPoint) * 25;
995 dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */
997 ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n",
998 leftOfPoint, rightOfPoint, trp_clocks);
1000 /*------------------------------------------------------------------------------------------------------------------------------*/
1002 case 30: /* Minimum Ras Pulse Width */
1003 dimmInfo->minRasPulseWidth = data[i];
1005 (NSto10PS (data[i]) +
1006 (tmemclk - 1)) / tmemclk;
1008 ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n",
1009 dimmInfo->minRasPulseWidth, tras_clocks);
1012 /*------------------------------------------------------------------------------------------------------------------------------*/
1014 case 31: /* Module Bank Density */
1015 dimmInfo->moduleBankDensity = data[i];
1017 ("Module Bank Density: %d\n",
1018 dimmInfo->moduleBankDensity);
1021 ("*** Offered Densities (more than 1 = Multisize-Module): ");
1023 if (dimmInfo->moduleBankDensity & 1)
1025 if (dimmInfo->moduleBankDensity & 2)
1027 if (dimmInfo->moduleBankDensity & 4)
1029 if (dimmInfo->moduleBankDensity & 8)
1031 if (dimmInfo->moduleBankDensity & 16)
1033 if (dimmInfo->moduleBankDensity & 32)
1035 if ((dimmInfo->moduleBankDensity & 64)
1036 || (dimmInfo->moduleBankDensity & 128)) {
1044 /*------------------------------------------------------------------------------------------------------------------------------*/
1046 case 32: /* Address And Command Setup Time (measured in ns/1000) */
1048 switch (dimmInfo->memoryType) {
1051 (((data[i] & 0xf0) >> 4) * 10) +
1053 leftOfPoint = time_tmp / 100;
1054 rightOfPoint = time_tmp % 100;
1057 leftOfPoint = (data[i] & 0xf0) >> 4;
1058 if (leftOfPoint > 7) {
1059 leftOfPoint = data[i] & 0x70 >> 4;
1062 rightOfPoint = (data[i] & 0x0f);
1065 dimmInfo->addrAndCommandSetupTime =
1066 (leftOfPoint * 100 + rightOfPoint) * sign;
1068 ("Address And Command Setup Time [ns]: %d.%d\n",
1069 sign * leftOfPoint, rightOfPoint);
1071 /*------------------------------------------------------------------------------------------------------------------------------*/
1073 case 33: /* Address And Command Hold Time */
1075 switch (dimmInfo->memoryType) {
1078 (((data[i] & 0xf0) >> 4) * 10) +
1080 leftOfPoint = time_tmp / 100;
1081 rightOfPoint = time_tmp % 100;
1084 leftOfPoint = (data[i] & 0xf0) >> 4;
1085 if (leftOfPoint > 7) {
1086 leftOfPoint = data[i] & 0x70 >> 4;
1089 rightOfPoint = (data[i] & 0x0f);
1092 dimmInfo->addrAndCommandHoldTime =
1093 (leftOfPoint * 100 + rightOfPoint) * sign;
1095 ("Address And Command Hold Time [ns]: %d.%d\n",
1096 sign * leftOfPoint, rightOfPoint);
1098 /*------------------------------------------------------------------------------------------------------------------------------*/
1100 case 34: /* Data Input Setup Time */
1102 switch (dimmInfo->memoryType) {
1105 (((data[i] & 0xf0) >> 4) * 10) +
1107 leftOfPoint = time_tmp / 100;
1108 rightOfPoint = time_tmp % 100;
1111 leftOfPoint = (data[i] & 0xf0) >> 4;
1112 if (leftOfPoint > 7) {
1113 leftOfPoint = data[i] & 0x70 >> 4;
1116 rightOfPoint = (data[i] & 0x0f);
1119 dimmInfo->dataInputSetupTime =
1120 (leftOfPoint * 100 + rightOfPoint) * sign;
1122 ("Data Input Setup Time [ns]: %d.%d\n",
1123 sign * leftOfPoint, rightOfPoint);
1125 /*------------------------------------------------------------------------------------------------------------------------------*/
1127 case 35: /* Data Input Hold Time */
1129 switch (dimmInfo->memoryType) {
1132 (((data[i] & 0xf0) >> 4) * 10) +
1134 leftOfPoint = time_tmp / 100;
1135 rightOfPoint = time_tmp % 100;
1138 leftOfPoint = (data[i] & 0xf0) >> 4;
1139 if (leftOfPoint > 7) {
1140 leftOfPoint = data[i] & 0x70 >> 4;
1143 rightOfPoint = (data[i] & 0x0f);
1146 dimmInfo->dataInputHoldTime =
1147 (leftOfPoint * 100 + rightOfPoint) * sign;
1149 ("Data Input Hold Time [ns]: %d.%d\n\n",
1150 sign * leftOfPoint, rightOfPoint);
1152 /*------------------------------------------------------------------------------------------------------------------------------*/
1155 /* calculating the sdram density */
1157 i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
1159 density = density * 2;
1161 dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
1162 dimmInfo->sdramWidth;
1163 dimmInfo->numberOfDevices =
1164 (dimmInfo->dataWidth / dimmInfo->sdramWidth) *
1165 dimmInfo->numOfModuleBanks;
1166 if ((dimmInfo->errorCheckType == 0x1)
1167 || (dimmInfo->errorCheckType == 0x2)
1168 || (dimmInfo->errorCheckType == 0x3)) {
1170 (dimmInfo->deviceDensity / 8) *
1171 (dimmInfo->numberOfDevices -
1172 /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */
1173 dimmInfo->numberOfDevices / 8);
1176 (dimmInfo->deviceDensity / 8) *
1177 dimmInfo->numberOfDevices;
1180 /* compute the module DRB size */
1182 (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
1183 tmp *= dimmInfo->numOfModuleBanks;
1184 tmp *= dimmInfo->sdramWidth;
1185 tmp = tmp >> 24; /* div by 0x4000000 (64M) */
1186 dimmInfo->drb_size = (uchar) tmp;
1187 debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
1189 /* try a CAS latency of 3 first... */
1191 /* bit 1 is CL2, bit 2 is CL3 */
1192 supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1;
1196 if (NS10to10PS (data[9]) <= tmemclk)
1202 if (NS10to10PS (data[23]) <= tmemclk)
1206 debug("cal_val = %d\n", cal_val);
1208 /* bummer, did't work... */
1210 debug("Couldn't find a good CAS latency\n");
1219 /* sets up the GT properly with information passed in */
1220 int setup_sdram (AUX_MEM_DIMM_INFO * info)
1223 ulong tmp_sdram_mode = 0; /* 0x141c */
1224 ulong tmp_dunit_control_low = 0; /* 0x1404 */
1227 /* added 8/21/2003 P. Marchese */
1228 unsigned int sdram_config_reg;
1230 /* added 10/10/2003 P. Marchese */
1231 ulong sdram_chip_size;
1233 /* sanity checking */
1234 if (!info->numOfModuleBanks) {
1235 printf ("setup_sdram called with 0 banks\n");
1240 set_dfcdlInit (); /* may be its not needed */
1241 debug("Delay line set done\n");
1243 /* set SDRAM mode NOP */ /* To_do check it */
1244 GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1245 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1247 ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
1250 /* SDRAM configuration */
1251 /* added 8/21/2003 P. Marchese */
1252 /* code allows usage of registered DIMMS */
1254 /* figure out the memory refresh internal */
1255 switch (info->RefreshInterval) {
1257 case 0x80: /* refresh period is 15.625 usec */
1259 (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_CLK)
1260 / (float) 1000000.0);
1263 case 0x81: /* refresh period is 3.9 usec */
1265 (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_CLK) /
1269 case 0x82: /* refresh period is 7.8 usec */
1271 (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_CLK) /
1275 case 0x83: /* refresh period is 31.3 usec */
1277 (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_CLK) /
1281 case 0x84: /* refresh period is 62.5 usec */
1283 (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_CLK) /
1287 case 0x85: /* refresh period is 125 usec */
1289 (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_CLK) /
1292 default: /* refresh period undefined */
1293 printf ("DRAM refresh period is unknown!\n");
1294 printf ("Aborting DRAM setup with an error\n");
1298 debug("calculated refresh interval %0x\n", sdram_config_reg);
1300 /* make sure the refresh value is only 14 bits */
1301 if (sdram_config_reg > 0x1fff)
1302 sdram_config_reg = 0x1fff;
1303 debug("adjusted refresh interval %0x\n", sdram_config_reg);
1305 /* we want physical bank interleaving and */
1306 /* virtual bank interleaving enabled so do nothing */
1307 /* since these bits need to be zero to enable the interleaving */
1309 /* registered DRAM ? */
1310 if (info->registeredAddrAndControlInputs == 1) {
1311 /* it's registered DRAM, so set the reg. DRAM bit */
1312 sdram_config_reg = sdram_config_reg | BIT17;
1313 debug("Enabling registered DRAM bit\n");
1315 /* turn on DRAM ECC? */
1316 #ifdef CONFIG_MV64460_ECC
1317 if (info->errorCheckType == 0x2) {
1318 /* DRAM has ECC, so turn it on */
1319 sdram_config_reg = sdram_config_reg | BIT18;
1320 debug("Enabling ECC\n");
1323 /* set the data DQS pin configuration */
1324 switch (info->sdramWidth) {
1325 case 0x4: /* memory is x4 */
1326 sdram_config_reg = sdram_config_reg | BIT20 | BIT21;
1327 debug("Data DQS pins set for 16 pins\n");
1329 case 0x8: /* memory is x8 or x16 */
1331 sdram_config_reg = sdram_config_reg | BIT21;
1332 debug("Data DQS pins set for 8 pins\n");
1334 case 0x20: /* memory is x32 */
1335 /* both bits are cleared for x32 so nothing to do */
1336 debug("Data DQS pins set for 2 pins\n");
1338 default: /* memory width unsupported */
1339 printf ("DRAM chip width is unknown!\n");
1340 printf ("Aborting DRAM setup with an error\n");
1346 /* perform read buffer assignments */
1347 /* we are going to use the Power-up defaults */
1348 /* bit 27 = PCI bus #0 = buffer 0 */
1349 /* bit 28 = PCI bus #1 = buffer 0 */
1350 /* bit 29 = MPSC = buffer 0 */
1351 /* bit 30 = IDMA = buffer 0 */
1352 /* bit 31 = Gigabit = buffer 0 */
1353 sdram_config_reg = sdram_config_reg | 0x58000000;
1354 sdram_config_reg = sdram_config_reg & 0xffffff00;
1355 /* bit 14 FBSplit = FCRAM controller bsplit enable. */
1356 /* bit 15 vw = FCRAM Variable write length enable. */
1357 /* bit 16 DType = Dram Type (0 = FCRAM,1 = Standard) */
1358 sdram_config_reg = sdram_config_reg | BIT14 | BIT15;
1360 /* write the value into the SDRAM configuration register */
1361 GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg);
1362 debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG));
1364 /* SDRAM open pages control keep open as much as I can */
1365 GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
1367 ("sdram_open_pages_controll 0x1414: %08x\n",
1368 GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
1370 /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1371 tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */
1373 debug("Core Signals are sync (by HW-Setting)!!!\n");
1376 ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
1378 /* SDRAM set CAS Latency according to SPD information */
1379 switch (info->memoryType) {
1381 printf ("### SD-RAM not supported !!!\n");
1382 printf ("Aborting!!!\n");
1384 /* ToDo fill SD-RAM if needed !!!!! */
1386 /* Calculate the settings for SDRAM mode and Dunit control low registers */
1387 /* Values set according to technical bulletin TB-92 rev. c */
1389 debug("### SET-CL for DDR-RAM\n");
1390 /* ronen db64460 - change the tmp_dunit_control_low setting!!! */
1391 switch (info->maxClSupported_DDR) {
1393 tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */
1394 if (tmp == 1) { /* clocks sync */
1395 if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
1396 tmp_dunit_control_low = 0x05110051;
1398 tmp_dunit_control_low = 0x24110051;
1400 ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1401 tmp_sdram_mode, tmp_dunit_control_low);
1402 printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
1403 } else { /* clk sync. bypassed */
1405 if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
1406 tmp_dunit_control_low = 0xC5000540;
1408 tmp_dunit_control_low = 0xC4000540;
1410 ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1411 tmp_sdram_mode, tmp_dunit_control_low);
1415 tmp_sdram_mode = 0x62; /* CL=2.5 Burstlength = 4 */
1416 if (tmp == 1) { /* clocks sync */
1417 if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
1418 tmp_dunit_control_low = 0x25110051;
1420 tmp_dunit_control_low = 0x24110051;
1422 ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1423 tmp_sdram_mode, tmp_dunit_control_low);
1424 printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
1425 } else { /* clk sync. bypassed */
1427 if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
1428 tmp_dunit_control_low = 0xC5000540;
1429 /* printf("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
1430 /* printf("Aborting!!!\n");1 */
1433 tmp_dunit_control_low = 0xC4000540;
1435 ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1436 tmp_sdram_mode, tmp_dunit_control_low);
1440 tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */
1441 if (tmp == 1) { /* clocks sync */
1442 if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
1443 tmp_dunit_control_low = 0x04110051;
1445 tmp_dunit_control_low = 0x03110051;
1447 ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1448 tmp_sdram_mode, tmp_dunit_control_low);
1449 printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
1450 } else { /* clk sync. bypassed */
1452 if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
1453 /*printf("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
1454 /*printf("Aborting!!!\n");1 */
1456 tmp_dunit_control_low = 0xC4000540;
1458 tmp_dunit_control_low = 0xC3000540;;
1460 ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1461 tmp_sdram_mode, tmp_dunit_control_low);
1465 tmp_sdram_mode = 0x52; /* CL=1.5 Burstlength = 4 */
1466 if (tmp == 1) { /* clocks sync */
1467 if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */
1468 tmp_dunit_control_low = 0x24110051;
1470 tmp_dunit_control_low = 0x23110051;
1472 ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1473 tmp_sdram_mode, tmp_dunit_control_low);
1474 printf ("Warnning: DRAM ClkSync was never tested(db64460)!!!!!\n");
1475 } else { /* clk sync. bypassed */
1477 if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */
1478 /*printf("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n");1 */
1479 /*printf("Aborting!!!\n");1 */
1481 tmp_dunit_control_low = 0xC4000540;
1483 tmp_dunit_control_low = 0xC3000540;
1485 ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1486 tmp_sdram_mode, tmp_dunit_control_low);
1491 printf ("Max. CL is out of range %d\n",
1492 info->maxClSupported_DDR);
1495 } /* end DDR switch */
1497 } /* end CL switch */
1499 /* Write results of CL detection procedure */
1500 /* set SDRAM mode reg. 0x141c */
1501 GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
1503 /* set SDRAM mode SetCommand 0x1418 */
1504 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1505 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1507 ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1510 /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1511 GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low);
1513 /* set SDRAM mode SetCommand 0x1418 */
1514 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1515 while (GTREGREAD (SDRAM_OPERATION) != 0) {
1517 ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
1520 /*------------------------------------------------------------------------------ */
1522 /* bank parameters */
1523 /* SDRAM address decode register 0x1410 */
1524 /* program this with the default value */
1525 tmp = 0x02; /* power-up default address select decoding value */
1527 debug("drb_size (n*64Mbit): %d\n", info->drb_size);
1528 /* figure out the DRAM chip size */
1530 (1 << (info->numOfRowAddresses + info->numOfColAddresses));
1531 sdram_chip_size *= info->sdramWidth;
1532 sdram_chip_size *= 4;
1533 debug("computed sdram chip size is %#lx\n", sdram_chip_size);
1534 /* divide sdram chip size by 64 Mbits */
1535 sdram_chip_size = sdram_chip_size / 0x4000000;
1536 switch (sdram_chip_size) {
1537 case 1: /* 64 Mbit */
1538 case 2: /* 128 Mbit */
1539 debug("RAM-Device_size 64Mbit or 128Mbit)\n");
1542 case 4: /* 256 Mbit */
1543 case 8: /* 512 Mbit */
1544 debug("RAM-Device_size 256Mbit or 512Mbit)\n");
1547 case 16: /* 1 Gbit */
1548 case 32: /* 2 Gbit */
1549 debug("RAM-Device_size 1Gbit or 2Gbit)\n");
1553 printf ("Error in dram size calculation\n");
1554 printf ("RAM-Device_size is unsupported\n");
1558 /* SDRAM address control */
1559 GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
1561 ("setting up sdram address control (0x1410) with: %08lx \n",
1564 /* ------------------------------------------------------------------------------ */
1565 /* same settings for registerd & non-registerd DDR SDRAM */
1567 ("setting up sdram_timing_control_low (0x1408) with: %08x \n",
1570 GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x01501220);
1573 /* ------------------------------------------------------------------------------ */
1575 /* SDRAM configuration */
1576 tmp = GTREGREAD (SDRAM_CONFIG);
1578 if (info->registeredAddrAndControlInputs
1579 || info->registeredDQMBinputs) {
1582 ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
1583 info->registeredAddrAndControlInputs,
1584 info->registeredDQMBinputs);
1587 /* Use buffer 1 to return read data to the CPU
1588 * Page 426 MV6indent: Standard input:1464: Warning:old style assignment ambiguity in "=*". Assuming "= *"
1590 indent: Standard input:1465: Warning:old style assignment ambiguity in "=*". Assuming "= *"
1595 ("Before Buffer assignment - sdram_conf (0x1400): %08x\n",
1596 GTREGREAD (SDRAM_CONFIG));
1598 ("After Buffer assignment - sdram_conf (0x1400): %08x\n",
1599 GTREGREAD (SDRAM_CONFIG));
1601 /* SDRAM timing To_do: */
1602 /* ------------------------------------------------------------------------------ */
1605 ("setting up sdram_timing_control_high (0x140c) with: %08x \n",
1607 GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0xc);
1610 ("setting up sdram address pads control (0x14c0) with: %08x \n",
1612 GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a);
1615 ("setting up sdram data pads control (0x14c4) with: %08x \n",
1617 GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a);
1619 /* ------------------------------------------------------------------------------ */
1621 /* set the SDRAM configuration for each bank */
1623 /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
1627 ("\n*** Running a MRS cycle for bank %d ***\n", i);
1630 memory_map_bank (i, 0, GB / 4);
1632 /* set SDRAM mode */ /* To_do check it */
1633 GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1634 check = GTREGREAD (SDRAM_OPERATION);
1636 ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
1640 /* switch back to normal operation mode */
1641 GT_REG_WRITE (SDRAM_OPERATION, 0);
1642 check = GTREGREAD (SDRAM_OPERATION);
1644 ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n",
1647 /* unmap the bank */
1648 memory_map_bank (i, 0, 0);
1656 * Check memory range for valid RAM. A simple memory test determines
1657 * the actually available RAM size between addresses `base' and
1658 * `base + maxsize'. Some (not all) hardware errors are detected:
1659 * - short between address lines
1660 * - short between data lines
1662 long int dram_size (long int *base, long int maxsize)
1664 volatile long int *addr, *b = base;
1665 long int cnt, val, save1, save2;
1667 #define STARTVAL (1<<20) /* start test at 1M */
1668 for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
1670 addr = base + cnt; /* pointer arith! */
1672 save1 = *addr; /* save contents of addr */
1673 save2 = *b; /* save contents of base */
1675 *addr = cnt; /* write cnt to addr */
1676 *b = 0; /* put null at base */
1678 /* check at base address */
1680 *addr = save1; /* restore *addr */
1681 *b = save2; /* restore *b */
1684 val = *addr; /* read *addr */
1685 val = *addr; /* read *addr */
1692 ("Found %08x at Address %08x (failure)\n",
1693 (unsigned int) val, (unsigned int) addr);
1694 /* fix boundary condition.. STARTVAL means zero */
1695 if (cnt == STARTVAL / sizeof (long))
1697 return (cnt * sizeof (long));
1703 /* ------------------------------------------------------------------------- */
1705 /* ppcboot interface function to SDRAM init - this is where all the
1706 * controlling logic happens */
1707 phys_size_t initdram (int board_type)
1709 int checkbank[4] = {[0 ... 3] = 0 };
1710 ulong realsize, total;
1711 AUX_MEM_DIMM_INFO dimmInfo1;
1712 AUX_MEM_DIMM_INFO dimmInfo2;
1714 ulong dest, memSpaceAttr;
1716 /* first, use the SPD to get info about the SDRAM/ DDRRAM */
1718 /* check the NHR bit and skip mem init if it's already done */
1719 nhr = get_hid0 () & (1 << 16);
1722 printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n");
1725 check_dimm (0, &dimmInfo1);
1728 check_dimm (1, &dimmInfo2);
1730 memory_map_bank (0, 0, 0);
1731 memory_map_bank (1, 0, 0);
1732 memory_map_bank (2, 0, 0);
1733 memory_map_bank (3, 0, 0);
1735 /* ronen check correct set of DIMMS */
1736 if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) {
1737 if (dimmInfo1.errorCheckType !=
1738 dimmInfo2.errorCheckType)
1739 printf ("***WARNNING***!!!! different ECC support of the DIMMS\n");
1740 if (dimmInfo1.maxClSupported_DDR !=
1741 dimmInfo2.maxClSupported_DDR)
1742 printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n");
1743 if (dimmInfo1.registeredAddrAndControlInputs !=
1744 dimmInfo2.registeredAddrAndControlInputs)
1745 printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n");
1748 if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) {
1749 printf ("Setup for DIMM1 failed.\n");
1752 if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) {
1753 printf ("Setup for DIMM2 failed.\n");
1756 /* set the NHR bit */
1757 set_hid0 (get_hid0 () | (1 << 16));
1759 /* next, size the SDRAM banks */
1761 realsize = total = 0;
1762 if (dimmInfo1.numOfModuleBanks > 0) {
1765 if (dimmInfo1.numOfModuleBanks > 1) {
1768 if (dimmInfo1.numOfModuleBanks > 2)
1769 printf ("Error, SPD claims DIMM1 has >2 banks\n");
1771 printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks);
1773 if (dimmInfo2.numOfModuleBanks > 0) {
1776 if (dimmInfo2.numOfModuleBanks > 1) {
1779 if (dimmInfo2.numOfModuleBanks > 2)
1780 printf ("Error, SPD claims DIMM2 has >2 banks\n");
1782 printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
1784 for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
1785 /* skip over banks that are not populated */
1786 if (!checkbank[bank_no])
1789 /* ronen - realsize = dram_size((long int *)total, check); */
1790 if (bank_no == 0 || bank_no == 1) {
1791 if (checkbank[1] == 1)
1792 realsize = dimmInfo1.size / 2;
1794 realsize = dimmInfo1.size;
1796 if (bank_no == 2 || bank_no == 3) {
1797 if (checkbank[3] == 1)
1798 realsize = dimmInfo2.size / 2;
1800 realsize = dimmInfo2.size;
1802 memory_map_bank (bank_no, total, realsize);
1804 /* ronen - initialize the DRAM for ECC */
1805 #ifdef CONFIG_MV64460_ECC
1806 if ((dimmInfo1.errorCheckType != 0) &&
1807 ((dimmInfo2.errorCheckType != 0)
1808 || (dimmInfo2.numOfModuleBanks == 0))) {
1809 printf ("ECC Initialization of Bank %d:", bank_no);
1810 memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8;
1811 mvDmaSetMemorySpace (0, 0, memSpaceAttr, total,
1813 for (dest = total; dest < total + realsize;
1815 mvDmaTransfer (0, total, dest, _8M,
1816 BIT8 /*DMA_DTL_128BYTES */ |
1817 BIT3 /*DMA_HOLD_SOURCE_ADDR */
1820 /*DMA_BLOCK_TRANSFER_MODE */ );
1821 while (mvDmaIsChannelActive (0));
1831 switch ((GTREGREAD (0x141c) >> 4) & 0x7) {
1833 printf ("CAS Latency = 2");
1836 printf ("CAS Latency = 3");
1839 printf ("CAS Latency = 1.5");
1842 printf ("CAS Latency = 2.5");
1845 printf (" tRP = %d tRAS = %d tRCD=%d\n",
1846 ((GTREGREAD (0x1408) >> 8) & 0xf) + 1,
1847 ((GTREGREAD (0x1408) >> 20) & 0xf) + 1,
1848 ((GTREGREAD (0x1408) >> 4) & 0xf) + 1);
1850 /* Setup Ethernet DMA Adress window to DRAM Area */
1852 printf ("*** ONLY the first 256MB DRAM memory are used out of the ");
1854 printf ("Total SDRAM memory is ");
1855 /* (cause all the 4 BATS are taken) */
1860 /* ronen- add Idma functions for usage of the ecc dram init. */
1861 /*******************************************************************************
1862 * mvDmaIsChannelActive - Checks if a engine is busy.
1863 ********************************************************************************/
1864 int mvDmaIsChannelActive (int engine)
1868 data = GTREGREAD (MV64460_DMA_CHANNEL0_CONTROL + 4 * engine);
1869 if (data & BIT14 /*activity status */ ) {
1875 /*******************************************************************************
1876 * mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding
1878 *******************************************************************************/
1879 int mvDmaSetMemorySpace (ulong memSpace,
1880 ulong memSpaceTarget,
1881 ulong memSpaceAttr, ulong baseAddress, ulong size)
1885 /* The base address must be aligned to the size. */
1886 if (baseAddress % size != 0) {
1889 if (size >= 0x10000 /*64K */ ) {
1891 baseAddress = (baseAddress & 0xffff0000);
1892 /* Set the new attributes */
1893 GT_REG_WRITE (MV64460_DMA_BASE_ADDR_REG0 + memSpace * 8,
1894 (baseAddress | memSpaceTarget | memSpaceAttr));
1895 GT_REG_WRITE ((MV64460_DMA_SIZE_REG0 + memSpace * 8),
1896 (size - 1) & 0xffff0000);
1897 temp = GTREGREAD (MV64460_DMA_BASE_ADDR_ENABLE_REG);
1898 GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG,
1899 (temp & ~(BIT0 << memSpace)));
1906 /*******************************************************************************
1907 * mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4
1909 ********************************************************************************/
1910 int mvDmaTransfer (int engine, ulong sourceAddr,
1911 ulong destAddr, ulong numOfBytes, ulong command)
1913 ulong engOffReg = 0; /* Engine Offset Register */
1915 if (numOfBytes > 0xffff) {
1916 command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ;
1918 command = command | ((command >> 6) & 0x7);
1919 engOffReg = engine * 4;
1920 GT_REG_WRITE (MV64460_DMA_CHANNEL0_BYTE_COUNT + engOffReg,
1922 GT_REG_WRITE (MV64460_DMA_CHANNEL0_SOURCE_ADDR + engOffReg,
1924 GT_REG_WRITE (MV64460_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg,
1927 command | BIT12 /*DMA_CHANNEL_ENABLE */ | BIT9
1928 /*DMA_NON_CHAIN_MODE */ ;
1929 /* Activate DMA engine By writting to mvDmaControlRegister */
1930 GT_REG_WRITE (MV64460_DMA_CHANNEL0_CONTROL + engOffReg, command);
1934 /****************************************************************************************
1936 * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb *
1937 * This procedure fits only the Atlantis *
1939 ***************************************************************************************/
1942 /****************************************************************************************
1943 * DFCDL initialize MV643xx Design Considerations *
1945 ***************************************************************************************/
1946 int set_dfcdlInit (void)
1948 /*ronen the dfcdl init are done by the I2C */