3 * Jason Cooper <u-boot@lakedaemon.net>
6 * Marvell Semiconductor <www.marvell.com>
7 * Written-by: Siddarth Gore <gores@marvell.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/kirkwood.h>
32 #include <asm/arch/mpp.h>
33 #include "dreamplug.h"
35 DECLARE_GLOBAL_DATA_PTR;
37 int board_early_init_f(void)
40 * default gpio configuration
41 * There are maximum 64 gpios controlled through 2 sets of registers
42 * the below configuration configures mainly initial LED status
44 kw_config_gpio(DREAMPLUG_OE_VAL_LOW,
45 DREAMPLUG_OE_VAL_HIGH,
46 DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
48 /* Multi-Purpose Pins Functionality configuration */
49 static const u32 kwmpp_config[] = {
50 MPP0_SPI_SCn, /* SPI Flash */
60 MPP10_UART0_TXD, /* Serial */
62 MPP12_SD_CLK, /* SDIO Slot */
70 MPP20_GE1_0, /* Gigabit Ethernet */
86 MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
97 MPP47_GPIO, /* Bluetooth LED */
98 MPP48_GPIO, /* Wifi LED */
99 MPP49_GPIO, /* Wifi AP LED */
102 kirkwood_mpp_conf(kwmpp_config, NULL);
108 /* adress of boot parameters */
109 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
114 #ifdef CONFIG_RESET_PHY_R
115 void mv_phy_88e1116_init(char *name)
120 if (miiphy_set_current_dev(name))
123 /* command to read PHY dev address */
124 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
125 printf("Err..%s could not read PHY dev address\n",
131 * Enable RGMII delay on Tx and Rx for CPU port
132 * Ref: sec 4.7.2 of chip datasheet
134 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
135 miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
136 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
137 miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
138 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
141 miiphy_reset(name, devadr);
143 printf("88E1116 Initialized on %s\n", name);
148 /* configure and initialize both PHY's */
149 mv_phy_88e1116_init("egiga0");
150 mv_phy_88e1116_init("egiga1");
152 #endif /* CONFIG_RESET_PHY_R */