1 # SPDX-License-Identifier: GPL-2.0+
4 # Marvell Semiconductor <www.marvell.com>
5 # Written-by: Siddarth Gore <gores@marvell.com>
6 # Refer doc/README.kwbimage for more details about how-to configure
7 # and create kirkwood boot image
10 # Boot Media configurations
15 # SOC registers configuration using bootrom header extension
16 # Maximum KWBIMAGE_MAX_CONFIG configurations allowed
18 # Configure RGMII-0/1 interface pad voltage to 1.8V
19 DATA 0xFFD100e0 0x1b1b9b9b
21 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
22 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
23 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
25 # bit24: 1= enable exit self refresh mode on DDR access
30 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
31 # bit 4: 0=addr/cmd in smame cycle
32 # bit 5: 0=clk is driven during self refresh, we don't care for APX
33 # bit 6: 0=use recommended falling edge of clk for addr/cmd
34 # bit14: 0=input buffer always powered up
35 # bit18: 1=cpu lock transaction enabled
36 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
37 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
38 # bit30-28: 3 required
39 # bit31: 0=no additional STARTBURST delay
41 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
52 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
57 # bit31-13: zero required
59 DATA 0xFFD01410 0x000000cc # DDR Address Control
60 # bit1-0: 01, Cs0width=x8
61 # bit3-2: 10, Cs0size=1Gb
62 # bit5-4: 01, Cs1width=x8
63 # bit7-6: 10, Cs1size=1Gb
64 # bit9-8: 00, Cs2width=nonexistent
65 # bit11-10: 00, Cs2size =nonexistent
66 # bit13-12: 00, Cs3width=nonexistent
67 # bit15-14: 00, Cs3size =nonexistent
68 # bit16: 0, Cs0AddrSel
69 # bit17: 0, Cs1AddrSel
70 # bit18: 0, Cs2AddrSel
71 # bit19: 0, Cs3AddrSel
72 # bit31-20: 0 required
74 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
75 # bit0: 0, OpenPage enabled
78 DATA 0xFFD01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000C52 # DDR Mode
83 # bit2-0: 2, BurstLen=2 required
84 # bit3: 0, BurstType=0 required
86 # bit7: 0, TestMode=0 normal
87 # bit8: 0, DLL reset=0 normal
88 # bit11-9: 6, auto-precharge write recovery ????????????
89 # bit12: 0, PD must be zero
90 # bit31-13: 0 required
92 DATA 0xFFD01420 0x00000040 # DDR Extended Mode
93 # bit0: 0, DDR DLL enabled
94 # bit1: 0, DDR drive strenght normal
95 # bit2: 0, DDR ODT control lsd (disabled)
96 # bit5-3: 000, required
97 # bit6: 1, DDR ODT control msb, (disabled)
98 # bit9-7: 000, required
99 # bit10: 0, differential DQS enabled
101 # bit12: 0, DDR output buffer enabled
102 # bit31-13: 0 required
104 DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
105 # bit2-0: 111, required
106 # bit3 : 1 , MBUS Burst Chop disabled
107 # bit6-4: 111, required
109 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
110 # bit9 : 0 , no half clock cycle addition to dataout
111 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
112 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
113 # bit15-12: 1111 required
114 # bit31-16: 0 required
116 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
119 DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
120 DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
121 # bit0: 1, Window enabled
122 # bit1: 0, Write Protect disabled
123 # bit3-2: 00, CS0 hit selected
124 # bit23-4: ones, required
125 # bit31-24: 0x0F, Size (i.e. 256MB)
127 DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
128 DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
130 DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
131 DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
133 DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
134 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
135 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
136 # bit3-2: 01, ODT1 active NEVER!
137 # bit31-4: zero, required
139 DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
140 DATA 0xFFD01480 0x00000001 # DDR Initialization Control
141 #bit0=1, enable DDR init upon this register write
143 # End of Header extension