3 # Marvell Semiconductor <www.marvell.com>
4 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 # See file CREDITS for list of people who contributed to this
9 # This program is free software; you can redistribute it and/or
10 # modify it under the terms of the GNU General Public License as
11 # published by the Free Software Foundation; either version 2 of
12 # the License, or (at your option) any later version.
14 # This program is distributed in the hope that it will be useful,
15 # but WITHOUT ANY WARRANTY; without even the implied warranty of
16 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 # GNU General Public License for more details.
19 # You should have received a copy of the GNU General Public License
20 # along with this program; if not, write to the Free Software
21 # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
24 # Refer doc/README.kwbimage for more details about how-to configure
25 # and create kirkwood boot image
28 # Boot Media configurations
29 BOOT_FROM spi # Boot from SPI flash
31 # SOC registers configuration using bootrom header extension
32 # Maximum KWBIMAGE_MAX_CONFIG configurations allowed
34 # Configure RGMII-0 interface pad voltage to 1.8V
35 DATA 0xFFD100e0 0x1b1b1b9b
37 #Dram initalization for SINGLE x16 CL=5 @ 400MHz
38 DATA 0xFFD01400 0x43000a00 # DDR Configuration register
39 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
41 # bit24: 1= enable exit self refresh mode on DDR access
46 DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
47 # bit 4: 0=addr/cmd in smame cycle
48 # bit 5: 0=clk is driven during self refresh, we don't care for APX
49 # bit 6: 0=use recommended falling edge of clk for addr/cmd
50 # bit14: 0=input buffer always powered up
51 # bit18: 1=cpu lock transaction enabled
52 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
53 # bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
54 # bit30-28: 3 required
55 # bit31: 0=no additional STARTBURST delay
57 DATA 0xFFD01408 0x2202433D # DDR Timing (Low) (active cycles value +1)
68 DATA 0xFFD0140C 0x0000002A # DDR Timing (High)
73 # bit31-13: zero required
75 DATA 0xFFD01410 0x0000000D # DDR Address Control
76 # bit1-0: 01, Cs0width=x16
77 # bit3-2: 11, Cs0size=1Gb
78 # bit5-4: 00, Cs2width=nonexistent
79 # bit7-6: 00, Cs1size =nonexistent
80 # bit9-8: 00, Cs2width=nonexistent
81 # bit11-10: 00, Cs2size =nonexistent
82 # bit13-12: 00, Cs3width=nonexistent
83 # bit15-14: 00, Cs3size =nonexistent
84 # bit16: 0, Cs0AddrSel
85 # bit17: 0, Cs1AddrSel
86 # bit18: 0, Cs2AddrSel
87 # bit19: 0, Cs3AddrSel
88 # bit31-20: 0 required
90 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
91 # bit0: 0, OpenPage enabled
94 DATA 0xFFD01418 0x00000000 # DDR Operation
95 # bit3-0: 0x0, DDR cmd
98 DATA 0xFFD0141C 0x00000C52 # DDR Mode
99 # bit2-0: 2, BurstLen=2 required
100 # bit3: 0, BurstType=0 required
102 # bit7: 0, TestMode=0 normal
103 # bit8: 0, DLL reset=0 normal
104 # bit11-9: 6, auto-precharge write recovery ????????????
105 # bit12: 0, PD must be zero
106 # bit31-13: 0 required
108 DATA 0xFFD01420 0x00000046 # DDR Extended Mode
109 # bit0: 0, DDR DLL enabled
110 # bit1: 1, DDR drive strenght reduced
111 # bit2: 1, DDR ODT control lsd enabled
112 # bit5-3: 000, required
113 # bit6: 1, DDR ODT control msb, enabled
114 # bit9-7: 000, required
115 # bit10: 0, differential DQS enabled
117 # bit12: 0, DDR output buffer enabled
118 # bit31-13: 0 required
120 DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High
121 # bit2-0: 111, required
122 # bit3 : 1 , MBUS Burst Chop disabled
123 # bit6-4: 111, required
124 # bit7 : 1 , D2P Latency enabled
125 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
126 # bit9 : 0 , no half clock cycle addition to dataout
127 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
128 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
129 # bit15-12: 1111 required
130 # bit31-16: 0 required
132 DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
133 DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
135 DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
136 DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
137 # bit0: 1, Window enabled
138 # bit1: 0, Write Protect disabled
139 # bit3-2: 00, CS0 hit selected
140 # bit23-4: ones, required
141 # bit31-24: 0x07, Size (i.e. 128MB)
143 DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
144 DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
145 DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
147 DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
148 # bit3-0: 1, ODT0Rd, MODT[0] asserted during read from DRAM CS0
149 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
151 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
152 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
153 # bit3-2: 01, ODT1 active NEVER!
154 # bit31-4: zero, required
156 DATA 0xFFD0149C 0x0000E811 # CPU ODT Control
157 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
158 # bit7-4: 1, ODT0Wr, Internal ODT asserted during write to DRAM bank0
159 # bit11-10:1, DQ_ODTSel. ODT select turned on
161 DATA 0xFFD01480 0x00000001 # DDR Initialization Control
162 #bit0=1, enable DDR init upon this register write
164 # End of Header extension