3 * Stäubli Faverges - <www.staubli.com>
4 * Pierre AUBERT p.aubert@staubli.com
5 * U-Boot port on RPXClassic LF (CLLF_BW31) board
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 * SPDX-License-Identifier: GPL-2.0+
19 /* ------------------------------------------------------------------------- */
21 static long int dram_size (long int, long int *, long int);
22 static unsigned char aschex_to_byte (unsigned char *cp);
24 /* ------------------------------------------------------------------------- */
26 #define _NOT_USED_ 0xFFFFCC25
28 const uint sdram_table[] =
31 * Single Read. (Offset 00h in UPMA RAM)
33 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
34 0x3FBFCC27, /* last */
35 _NOT_USED_, _NOT_USED_, _NOT_USED_,
38 * Burst Read. (Offset 08h in UPMA RAM)
40 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
41 0x3FBFCC27, /* last */
42 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
43 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
44 _NOT_USED_, _NOT_USED_, _NOT_USED_,
47 * Single Write. (Offset 18h in UPMA RAM)
49 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
50 0x3FFFCC27, /* last */
51 _NOT_USED_, _NOT_USED_, _NOT_USED_,
54 * Burst Write. (Offset 20h in UPMA RAM)
56 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
57 0x0CFFCC00, 0x33FFCC27, /* last */
58 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
59 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
60 _NOT_USED_, _NOT_USED_,
63 * Refresh. (Offset 30h in UPMA RAM)
65 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
66 0x3FFFCC27, /* last */
67 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
68 _NOT_USED_, _NOT_USED_, _NOT_USED_,
71 * Exception. (Offset 3Ch in UPMA RAM)
73 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
76 /* ------------------------------------------------------------------------- */
80 * Check Board Identity:
85 puts ("Board: RPXClassic\n");
89 /*-----------------------------------------------------------------------------
90 * board_get_enetaddr -- Read the MAC Address in the I2C EEPROM
91 *-----------------------------------------------------------------------------
93 static void board_get_enetaddr(uchar *enet)
99 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
101 /* Read 256 bytes in EEPROM */
102 i2c_read (0x54, 0, 1, (uchar *)buff, 128);
103 i2c_read (0x54, 128, 1, (uchar *)buff + 128, 128);
105 /* Retrieve MAC address in buffer (key EA) */
107 if (cp[0] == 'E' && cp[1] == 'A') {
109 /* Read MAC address */
110 for (i = 0; i < 6; i++, cp += 2) {
111 enet[i] = aschex_to_byte ((unsigned char *)cp);
114 /* Scan to the end of the record */
115 while ((*cp != '\n') && (*cp != (char)0xff)) {
118 /* If the next character is a \n, 0 or ff, we are done. */
120 if ((*cp == '\n') || (*cp == 0) || (*cp == (char)0xff))
124 #ifdef CONFIG_FEC_ENET
125 /* The MAC address is the same as normal ethernet except the 3rd byte */
126 /* (See the E.P. Planet Core Overview manual */
130 printf("MAC address = %pM\n", enet);
133 int misc_init_r(void)
137 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
138 board_get_enetaddr(enetaddr);
139 eth_setenv_enetaddr("ethaddr", enetaddr);
145 void rpxclassic_init (void)
148 *((uchar *) BCSR0) |= BCSR0_ENNVRAM;
150 #ifdef CONFIG_FEC_ENET
152 /* Validate the fast ethernet tranceiver */
153 *((volatile uchar *) BCSR2) &= ~BCSR2_MIICTL;
154 *((volatile uchar *) BCSR2) &= ~BCSR2_MIIPWRDWN;
155 *((volatile uchar *) BCSR2) |= BCSR2_MIIRST;
156 *((volatile uchar *) BCSR2) |= BCSR2_MIIPWRDWN;
161 /* ------------------------------------------------------------------------- */
163 phys_size_t initdram (int board_type)
165 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
166 volatile memctl8xx_t *memctl = &immap->im_memctl;
169 upmconfig (UPMA, (uint *) sdram_table,
170 sizeof (sdram_table) / sizeof (uint));
172 /* Refresh clock prescalar */
173 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
175 memctl->memc_mar = 0x00000000;
177 /* Map controller banks 1 to the SDRAM bank */
178 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
179 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
181 memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
185 /* perform SDRAM initializsation sequence */
187 memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */
190 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
194 /* Check Bank 0 Memory Size
198 size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
204 /* ------------------------------------------------------------------------- */
207 * Check memory range for valid RAM. A simple memory test determines
208 * the actually available RAM size between addresses `base' and
209 * `base + maxsize'. Some (not all) hardware errors are detected:
210 * - short between address lines
211 * - short between data lines
214 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
216 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
217 volatile memctl8xx_t *memctl = &immap->im_memctl;
219 memctl->memc_mamr = mamr_value;
221 return (get_ram_size(base, maxsize));
223 /*-----------------------------------------------------------------------------
225 *-----------------------------------------------------------------------------
227 static unsigned char aschex_to_byte (unsigned char *cp)
233 if ((c >= 'A') && (c <= 'F')) {
236 } else if ((c >= 'a') && (c <= 'f')) {
247 if ((c >= 'A') && (c <= 'F')) {
250 } else if ((c >= 'a') && (c <= 'f')) {