3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
9 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/processor.h>
37 #include <led-display.h>
39 #include "mt46v32m16.h"
41 #ifndef CONFIG_SYS_RAMBOOT
42 static void sdram_start (int hi_addr)
44 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
45 long control = SDRAM_CONTROL | hi_addr_bit;
47 /* unlock mode register */
48 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
49 __asm__ volatile ("sync");
51 /* precharge all banks */
52 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
53 __asm__ volatile ("sync");
56 /* set mode register: extended mode */
57 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
58 __asm__ volatile ("sync");
60 /* set mode register: reset DLL */
61 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
62 __asm__ volatile ("sync");
65 /* precharge all banks */
66 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
67 __asm__ volatile ("sync");
70 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
71 __asm__ volatile ("sync");
73 /* set mode register */
74 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
75 __asm__ volatile ("sync");
77 /* normal operation */
78 out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
79 __asm__ volatile ("sync");
84 * ATTENTION: Although partially referenced initdram does NOT make real use
85 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
86 * is something else than 0x00000000.
89 phys_size_t initdram (int board_type)
94 #ifndef CONFIG_SYS_RAMBOOT
97 /* setup SDRAM chip selects */
98 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
99 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
100 __asm__ volatile ("sync");
102 /* setup config registers */
103 out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
104 out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
105 __asm__ volatile ("sync");
109 out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
110 __asm__ volatile ("sync");
113 /* find RAM size using SDRAM CS0 only */
115 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
117 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
125 /* memory smaller than 1MB is impossible */
126 if (dramsize < (1 << 20)) {
130 /* set SDRAM CS0 size according to the amount of RAM found */
132 out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
133 0x13 + __builtin_ffs(dramsize >> 20) - 1);
135 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
138 #else /* CONFIG_SYS_RAMBOOT */
140 /* retrieve size of memory connected to SDRAM CS0 */
141 dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
142 if (dramsize >= 0x13) {
143 dramsize = (1 << (dramsize - 0x13)) << 20;
148 #endif /* CONFIG_SYS_RAMBOOT */
151 * On MPC5200B we need to set the special configuration delay in the
152 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
153 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
155 * "The SDelay should be written to a value of 0x00000004. It is
156 * required to account for changes caused by normal wafer processing
161 if ((SVR_MJREV(svr) >= 2) &&
162 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
164 out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
165 __asm__ volatile ("sync");
171 int checkboard (void)
173 puts ("Board: A4M072\n");
178 static struct pci_controller hose;
180 extern void pci_mpc5xxx_init(struct pci_controller *);
182 void pci_init_board(void)
184 pci_mpc5xxx_init(&hose);
188 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
190 ft_board_setup(void *blob, bd_t *bd)
192 ft_cpu_setup(blob, bd);
196 int board_eth_init(bd_t *bis)
200 /* Initialize TSECs first */
201 if ((rv = cpu_eth_init(bis)) >= 0)
204 printf("ERROR: failed to initialize FEC.\n");
206 if ((rv = pci_eth_init(bis)) >= 0)
209 printf("ERROR: failed to initialize PCI Ethernet.\n");
214 * Miscellaneous late-boot configurations
216 * Initialize EEPROM write-protect GPIO pin.
218 int misc_init_r(void)
220 #if defined(CONFIG_SYS_EEPROM_WREN)
221 /* Enable GPIO pin */
222 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
223 /* Set direction, output */
224 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
225 /* De-assert write enable */
226 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
230 #if defined(CONFIG_SYS_EEPROM_WREN)
231 /* Input: <dev_addr> I2C address of EEPROM device to enable.
232 * <state> -1: deliver current state
235 * Returns: -1: wrong device address
236 * 0: dis-/en- able done
237 * 0/1: current state if <state> was -1.
239 int eeprom_write_enable (unsigned dev_addr, int state)
241 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
246 /* Enable write access */
247 clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
251 /* Disable write access */
252 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
256 /* Read current status back. */
257 state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
258 CONFIG_SYS_EEPROM_WP));
266 #ifdef CONFIG_CMD_DISPLAY
267 #define DISPLAY_BUF_SIZE 2
268 static u8 display_buf[DISPLAY_BUF_SIZE];
269 static u8 display_putc_pos;
270 static u8 display_out_pos;
272 static u8 display_dot_enable;
274 void display_set(int cmd) {
276 if (cmd & DISPLAY_CLEAR) {
277 display_buf[0] = display_buf[1] = 0;
280 if (cmd & DISPLAY_HOME) {
281 display_putc_pos = 0;
284 if (cmd & DISPLAY_MARK) {
285 display_dot_enable = 1;
287 display_dot_enable = 0;
318 #define SYMBOL_DASH (36)
319 #define SYMBOL_UNDERLINE (37)
321 static u8 display_char2seg7_tbl[]=
323 SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* 0 */
324 SEG_B | SEG_C, /* 1 */
325 SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* 2 */
326 SEG_A | SEG_B | SEG_C | SEG_D | SEG_G, /* 3 */
327 SEG_B | SEG_C | SEG_F | SEG_G, /* 4 */
328 SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* 5 */
329 SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 6 */
330 SEG_A | SEG_B | SEG_C, /* 7 */
331 SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 8 */
332 SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* 9 */
333 SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* A */
334 SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* b */
335 SEG_A | SEG_D | SEG_E | SEG_F, /* C */
336 SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, /* d */
337 SEG_A | SEG_D | SEG_E | SEG_F | SEG_G, /* E */
338 SEG_A | SEG_E | SEG_F | SEG_G, /* F */
339 SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* g */
340 SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* H */
341 SEG_E | SEG_F, /* I */
342 SEG_B | SEG_C | SEG_D | SEG_E, /* J */
343 SEG_A, /* K - special 1 */
344 SEG_D | SEG_E | SEG_F, /* L */
345 SEG_B, /* m - special 2 */
346 SEG_C | SEG_E | SEG_G, /* n */
347 SEG_C | SEG_D | SEG_E | SEG_G, /* o */
348 SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, /* P */
349 SEG_A | SEG_B | SEG_C | SEG_F | SEG_G, /* q */
350 SEG_E | SEG_G, /* r */
351 SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* S */
352 SEG_D | SEG_E | SEG_F | SEG_G, /* t */
353 SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* U */
354 SEG_C | SEG_D | SEG_E | SEG_F, /* V */
355 SEG_C, /* w - special 3 */
356 SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* X */
357 SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* Y */
358 SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* Z */
363 /* Convert char to the LED segments representation */
364 static u8 display_char2seg7(char c)
368 if (c >= '0' && c <= '9')
370 else if (c >= 'a' && c <= 'z')
372 else if (c >= 'A' && c <= 'Z')
376 else if ((c == '_') || (c == '.'))
377 c = SYMBOL_UNDERLINE;
379 c = ' '; /* display unsupported symbols as space */
382 val = display_char2seg7_tbl[(int)c];
384 /* Handle DP LED here */
385 if (display_dot_enable) {
392 static inline int display_putc_nomark(char c)
394 if (display_putc_pos >= DISPLAY_BUF_SIZE)
397 display_buf[display_putc_pos++] = display_char2seg7(c);
398 /* one-symbol message should be steady */
399 if (display_putc_pos == 1)
400 display_buf[display_putc_pos] = display_char2seg7(c);
405 int display_putc(char c)
407 /* Mark the codes from the "display" command with the DP LED */
408 display_set(DISPLAY_MARK);
409 return display_putc_nomark(c);
413 * Output content of the software display buffer to the LED display every 0.5s
415 void board_show_activity(ulong timestamp)
421 if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) {
422 val = display_buf[display_out_pos];
423 val |= (val << 8) | (val << 16) | (val << 24);
424 out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val);
425 display_out_pos ^= 1;
432 * Empty fake function
434 void show_activity(int arg)