3 * Michael Schwingen, michael@schwingen.org
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13 * Marius Groeger <mgroeger@sysgo.de>
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/arch/ixp425.h>
40 #include "actux3_hw.h"
42 DECLARE_GLOBAL_DATA_PTR;
44 int board_early_init_f(void)
47 writel(0x94d10013, IXP425_EXP_CS1);
49 writel(0x9d520003, IXP425_EXP_CS5);
50 /* CS6: Release/Option register */
51 writel(0x81860001, IXP425_EXP_CS6);
53 writel(0x80900003, IXP425_EXP_CS7);
60 /* adress of boot parameters */
61 gd->bd->bi_boot_params = 0x00000100;
63 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
64 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST);
65 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR);
66 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD);
67 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN);
68 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT);
69 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN);
71 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
72 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST);
74 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR);
75 GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD);
77 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN);
78 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT);
79 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN);
82 * Setup GPIO's for Interrupt inputs
84 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT);
85 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT);
88 * Setup GPIO's for 33MHz clock output
90 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
91 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
92 writel(0x011001FF, IXP425_GPIO_GPCLKR);
94 /* we need a minimum PCI reset pulse width after enabling the clock */
96 GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
97 GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST);
112 * Check Board Identity
117 int i = getenv_f("serial#", buf, sizeof(buf));
119 puts("Board: AcTux-3 rev.");
120 putc(ACTUX3_BOARDREL + 'A' - 1);
131 /*************************************************************************
132 * get_board_rev() - setup to pass kernel board revision information
136 *************************************************************************/
137 u32 get_board_rev(void)
139 return ACTUX3_BOARDREL;
144 gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
152 /* initialize the PHY */
153 miiphy_reset("NPE0", CONFIG_PHY_ADDR);
155 /* all LED outputs = Link/Act */
156 miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA);
159 * The Marvell 88E6060 switch comes up with all ports disabled.
160 * set all ethernet switch ports to forwarding state
162 for (i = 1; i <= 5; i++)
163 miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03);