2 * Copyright (C) 2004-2005 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
5 * Support for Analogue&Micro Adder boards family.
6 * Tested on AdderII and Adder87x.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * SDRAM is single Samsung K4S643232F-T70 chip (8MB)
32 * or single Micron MT48LC4M32B2TG-7 chip (16MB).
33 * Minimal CPU frequency is 40MHz.
35 static uint sdram_table[] = {
36 /* Single read (offset 0x00 in UPM RAM) */
37 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
38 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
40 /* Burst read (offset 0x08 in UPM RAM) */
41 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
42 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
43 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
44 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
46 /* Single write (offset 0x18 in UPM RAM) */
47 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
48 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
50 /* Burst write (offset 0x20 in UPM RAM) */
51 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
52 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
53 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
54 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
56 /* Refresh (offset 0x30 in UPM RAM) */
57 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
58 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
59 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
61 /* Exception (offset 0x3C in UPM RAM) */
62 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
65 long int initdram (int board_type)
68 volatile immap_t *immap = (volatile immap_t *)CFG_IMMR;
69 volatile memctl8xx_t *memctl = &immap->im_memctl;
71 upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
73 /* Configure SDRAM refresh */
74 memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
76 memctl->memc_mamr = (94 << 24) | CFG_MAMR; /* No refresh */
79 /* Run precharge from location 0x15 */
80 memctl->memc_mar = 0x0;
81 memctl->memc_mcr = 0x80002115;
84 /* Run 8 refresh cycles */
85 memctl->memc_mcr = 0x80002830;
88 /* Run MRS pattern from location 0x16 */
89 memctl->memc_mar = 0x88;
90 memctl->memc_mcr = 0x80002116;
93 memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */
94 memctl->memc_or1 = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
95 memctl->memc_br1 = CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
97 msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
98 memctl->memc_or1 |= ~(msize - 1);
103 int checkboard( void )
105 puts("Board: Adder");
106 #if defined(CONFIG_MPC885_FAMILY)
108 #elif defined(CONFIG_MPC866_FAMILY)