2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * Check Board Identity:
32 int checkboard( void )
35 puts("AdderII(MPC852T)\n" );
40 #if defined( CONFIG_SDRAM_50MHZ )
42 /******************************************************************************
43 ** for chip Samsung K4S643232F - T70
44 ** this table is for 32-50MHz operation
45 *******************************************************************************/
47 #define SDRAM_MPTPRVALUE 0x0200
49 #define SDRAM_MAMRVALUE0 0x00802114 /* refresh at 32MHz */
50 #define SDRAM_MAMRVALUE1 0x00802118
52 #define SDRAM_OR1VALUE 0xff800e00
53 #define SDRAM_BR1VALUE 0x00000081
55 #define SDRAM_MARVALUE 94
57 #define SDRAM_MCRVALUE0 0x80808105
58 #define SDRAM_MCRVALUE1 0x80808130
60 const uint sdram_table[] = {
62 /* single read (offset 0x00 in upm ram) */
63 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
64 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
66 /* burst read (offset 0x08 in upm ram) */
67 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
68 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
69 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
70 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
72 /* single write (offset 0x18 in upm ram) */
73 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
74 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
76 /* burst write (offset 0x20 in upm ram) */
77 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
78 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
79 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
80 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
82 /* refresh (offset 0x30 in upm ram) */
83 0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
84 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
85 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
87 /* exception (offset 0x3C in upm ram) */
88 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04,
92 #error SDRAM not correctly configured
95 int _initsdram (uint base, uint noMbytes)
97 volatile immap_t *immap = (immap_t *) CFG_IMMR;
98 volatile memctl8xx_t *memctl = &immap->im_memctl;
104 upmconfig (UPMA, (uint *) sdram_table,
105 sizeof (sdram_table) / sizeof (uint));
107 memctl->memc_mptpr = SDRAM_MPTPRVALUE;
109 /* Configure the refresh (mostly). This needs to be
110 * based upon processor clock speed and optimized to provide
111 * the highest level of performance. For multiple banks,
112 * this time has to be divided by the number of banks.
113 * Although it is not clear anywhere, it appears the
114 * refresh steps through the chip selects for this UPM
115 * on each refresh cycle.
116 * We have to be careful changing
117 * UPM registers after we ask it to run these commands.
120 memctl->memc_mamr = (SDRAM_MAMRVALUE0 | (SDRAM_MARVALUE << 24));
121 memctl->memc_mar = 0x0;
124 /* Now run the precharge/nop/mrs commands.
126 memctl->memc_mcr = 0x80002115;
129 /* Run 8 refresh cycles */
130 memctl->memc_mcr = 0x80002380;
133 memctl->memc_mar = 0x88;
136 memctl->memc_mcr = 0x80002116;
139 memctl->memc_or1 = SDRAM_OR1VALUE;
140 memctl->memc_br1 = SDRAM_BR1VALUE | base;
145 void _sdramdisable( void )
147 volatile immap_t *immap = (immap_t *)CFG_IMMR;
148 volatile memctl8xx_t *memctl = &immap->im_memctl;
150 memctl->memc_br1 = 0x00000000;
152 /* maybe we should turn off upma here or something */
155 int initsdram (uint base, uint * noMbytes)
161 if (!_initsdram (base, m)) {
169 long int initdram (int board_type)
171 /* AdderII: has 8MB SDRAM */
175 if (!initsdram (0x00000000, &sdramsz)) {
185 /* TODO: XXX XXX XXX not an actual SDRAM test */
186 printf ("Test: 8MB SDRAM\n");