2 * (C) Copyright 2007 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/bitops.h>
28 #include <fdt_support.h>
31 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
32 CLOCK_SCCR1_LPC_EN | \
33 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
34 CLOCK_SCCR1_PSCFIFO_EN | \
35 CLOCK_SCCR1_DDR_EN | \
36 CLOCK_SCCR1_FEC_EN | \
37 CLOCK_SCCR1_PCI_EN | \
40 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
41 CLOCK_SCCR2_SPDIF_EN | \
42 CLOCK_SCCR2_DIU_EN | \
45 #define CSAW_START(start) ((start) & 0xFFFF0000)
46 #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
48 long int fixed_sdram(void);
50 int board_early_init_f (void)
52 volatile immap_t *im = (immap_t *) CFG_IMMR;
57 * Initialize Local Window for the CPLD registers access (CS2 selects
60 im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
61 CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
62 im->lpc.cs_cfg[2] = CFG_CS2_CFG;
65 * According to MPC5121e RM, configuring local access windows should
66 * be followed by a dummy read of the config register that was
67 * modified last and an isync
69 lpcaw = im->sysconf.lpcs2aw;
70 __asm__ __volatile__ ("isync");
73 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
75 * Without this the flash identification routine fails, as it needs to issue
76 * write commands in order to establish the device ID.
78 *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
83 im->clk.sccr[0] = SCCR1_CLOCKS_EN;
84 im->clk.sccr[1] = SCCR2_CLOCKS_EN;
89 phys_size_t initdram (int board_type)
93 msize = fixed_sdram ();
99 * fixed sdram init -- the board doesn't use memory modules that have serial presence
100 * detect or similar mechanism for discovery of the DRAM settings
102 long int fixed_sdram (void)
104 volatile immap_t *im = (immap_t *) CFG_IMMR;
105 u32 msize = CFG_DDR_SIZE * 1024 * 1024;
106 u32 msize_log2 = __ilog2 (msize);
109 /* Initialize IO Control */
110 im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;
112 /* Initialize DDR Local Window */
113 im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
114 im->sysconf.ddrlaw.ar = msize_log2 - 1;
117 * According to MPC5121e RM, configuring local access windows should
118 * be followed by a dummy read of the config register that was
119 * modified last and an isync
121 i = im->sysconf.ddrlaw.ar;
122 __asm__ __volatile__ ("isync");
125 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;
127 /* Initialize DDR Priority Manager */
128 im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
129 im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
130 im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
131 im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
132 im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
133 im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
134 im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
135 im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
136 im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
137 im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
138 im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
139 im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
140 im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
141 im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
142 im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
143 im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
144 im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
145 im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
146 im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
147 im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
148 im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
149 im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
150 im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
152 /* Initialize MDDRC */
153 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
154 im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
155 im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
156 im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;
159 for (i = 0; i < 10; i++)
160 im->mddrc.ddr_command = CFG_MICRON_NOP;
162 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
163 im->mddrc.ddr_command = CFG_MICRON_NOP;
164 im->mddrc.ddr_command = CFG_MICRON_RFSH;
165 im->mddrc.ddr_command = CFG_MICRON_NOP;
166 im->mddrc.ddr_command = CFG_MICRON_RFSH;
167 im->mddrc.ddr_command = CFG_MICRON_NOP;
168 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
169 im->mddrc.ddr_command = CFG_MICRON_NOP;
170 im->mddrc.ddr_command = CFG_MICRON_EM2;
171 im->mddrc.ddr_command = CFG_MICRON_NOP;
172 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
173 im->mddrc.ddr_command = CFG_MICRON_EM2;
174 im->mddrc.ddr_command = CFG_MICRON_EM3;
175 im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
176 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
177 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
178 im->mddrc.ddr_command = CFG_MICRON_RFSH;
179 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
180 im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
181 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
182 im->mddrc.ddr_command = CFG_MICRON_NOP;
185 im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
186 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;
191 int misc_init_r(void)
195 /* Using this for DIU init before the driver in linux takes over
196 * Enable the TFP410 Encoder (I2C address 0x38)
201 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
202 /* Verify if enabled */
204 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
205 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
208 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
209 /* Verify if enabled */
211 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
212 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
214 #ifdef CONFIG_FSL_DIU_FB
215 #if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
223 int checkboard (void)
225 ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
226 uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
228 printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
230 /* initialize function mux & slew rate IO inter alia on IO Pins */
236 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
237 void ft_board_setup(void *blob, bd_t *bd)
239 ft_cpu_setup(blob, bd);
240 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
242 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */