2 * (C) Copyright 2007 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/bitops.h>
28 #include <fdt_support.h>
31 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
32 CLOCK_SCCR1_LPC_EN | \
33 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
34 CLOCK_SCCR1_PSCFIFO_EN | \
35 CLOCK_SCCR1_DDR_EN | \
38 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
39 CLOCK_SCCR2_SPDIF_EN | \
42 #define CSAW_START(start) ((start) & 0xFFFF0000)
43 #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
45 long int fixed_sdram(void);
47 int board_early_init_f (void)
49 volatile immap_t *im = (immap_t *) CFG_IMMR;
53 * Initialize Local Window for the CPLD registers access (CS2 selects
56 im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
57 CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
58 im->lpc.cs_cfg[2] = CFG_CS2_CFG;
61 * According to MPC5121e RM, configuring local access windows should
62 * be followed by a dummy read of the config register that was
63 * modified last and an isync
65 lpcaw = im->sysconf.lpcs2aw;
66 __asm__ __volatile__ ("isync");
69 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
71 * Without this the flash identification routine fails, as it needs to issue
72 * write commands in order to establish the device ID.
74 *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
79 im->clk.sccr[0] = SCCR1_CLOCKS_EN;
80 im->clk.sccr[1] = SCCR2_CLOCKS_EN;
85 long int initdram (int board_type)
89 msize = fixed_sdram ();
95 * fixed sdram init -- the board doesn't use memory modules that have serial presence
96 * detect or similar mechanism for discovery of the DRAM settings
98 long int fixed_sdram (void)
100 volatile immap_t *im = (immap_t *) CFG_IMMR;
101 u32 msize = CFG_DDR_SIZE * 1024 * 1024;
102 u32 msize_log2 = __ilog2 (msize);
105 /* Initialize IO Control */
106 im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;
108 /* Initialize DDR Local Window */
109 im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
110 im->sysconf.ddrlaw.ar = msize_log2 - 1;
113 * According to MPC5121e RM, configuring local access windows should
114 * be followed by a dummy read of the config register that was
115 * modified last and an isync
117 i = im->sysconf.ddrlaw.ar;
118 __asm__ __volatile__ ("isync");
121 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;
123 /* Initialize DDR Priority Manager */
124 im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
125 im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
126 im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
127 im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
128 im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
129 im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
130 im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
131 im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
132 im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
133 im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
134 im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
135 im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
136 im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
137 im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
138 im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
139 im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
140 im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
141 im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
142 im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AU;
143 im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
144 im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
145 im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
146 im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
148 /* Initialize MDDRC */
149 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
150 im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
151 im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
152 im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;
155 for (i = 0; i < 10; i++)
156 im->mddrc.ddr_command = CFG_MICRON_NOP;
158 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
159 im->mddrc.ddr_command = CFG_MICRON_EM2;
160 im->mddrc.ddr_command = CFG_MICRON_EM3;
161 im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
162 im->mddrc.ddr_command = CFG_MICRON_RST_DLL;
163 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
164 im->mddrc.ddr_command = CFG_MICRON_RFSH;
165 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
166 im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
167 im->mddrc.ddr_command = CFG_MICRON_OCD_EXIT;
169 for (i = 0; i < 10; i++)
170 im->mddrc.ddr_command = CFG_MICRON_NOP;
173 im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
174 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;
179 int checkboard (void)
181 ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
182 uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
184 printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
189 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
190 void ft_board_setup(void *blob, bd_t *bd)
192 ft_cpu_setup(blob, bd);
193 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
195 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */