2 * (C) Copyright 2007 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/bitops.h>
28 #include <fdt_support.h>
29 #ifdef CONFIG_MISC_INIT_R
32 #include "iopin.h" /* for iopin_initialize() prototype */
35 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
36 CLOCK_SCCR1_LPC_EN | \
37 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
38 CLOCK_SCCR1_PSCFIFO_EN | \
39 CLOCK_SCCR1_DDR_EN | \
40 CLOCK_SCCR1_FEC_EN | \
41 CLOCK_SCCR1_PCI_EN | \
44 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
45 CLOCK_SCCR2_SPDIF_EN | \
46 CLOCK_SCCR2_DIU_EN | \
49 #define CSAW_START(start) ((start) & 0xFFFF0000)
50 #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
52 long int fixed_sdram(void);
54 int board_early_init_f (void)
56 volatile immap_t *im = (immap_t *) CFG_IMMR;
60 * Initialize Local Window for the CPLD registers access (CS2 selects
63 im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
64 CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
65 im->lpc.cs_cfg[2] = CFG_CS2_CFG;
68 * According to MPC5121e RM, configuring local access windows should
69 * be followed by a dummy read of the config register that was
70 * modified last and an isync
72 lpcaw = im->sysconf.lpcs2aw;
73 __asm__ __volatile__ ("isync");
76 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
78 * Without this the flash identification routine fails, as it needs to issue
79 * write commands in order to establish the device ID.
82 #ifdef CONFIG_ADS5121_REV2
83 *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
85 if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) {
86 *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
88 /* running from Backup flash */
89 *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32;
93 * Configure Flash Speed
95 *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG;
99 im->clk.sccr[0] = SCCR1_CLOCKS_EN;
100 im->clk.sccr[1] = SCCR2_CLOCKS_EN;
105 phys_size_t initdram (int board_type)
109 msize = fixed_sdram ();
115 * fixed sdram init -- the board doesn't use memory modules that have serial presence
116 * detect or similar mechanism for discovery of the DRAM settings
118 long int fixed_sdram (void)
120 volatile immap_t *im = (immap_t *) CFG_IMMR;
121 u32 msize = CFG_DDR_SIZE * 1024 * 1024;
122 u32 msize_log2 = __ilog2 (msize);
125 /* Initialize IO Control */
126 im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;
128 /* Initialize DDR Local Window */
129 im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
130 im->sysconf.ddrlaw.ar = msize_log2 - 1;
133 * According to MPC5121e RM, configuring local access windows should
134 * be followed by a dummy read of the config register that was
135 * modified last and an isync
137 i = im->sysconf.ddrlaw.ar;
138 __asm__ __volatile__ ("isync");
141 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;
143 /* Initialize DDR Priority Manager */
144 im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
145 im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
146 im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
147 im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
148 im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
149 im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
150 im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
151 im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
152 im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
153 im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
154 im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
155 im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
156 im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
157 im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
158 im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
159 im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
160 im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
161 im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
162 im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
163 im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
164 im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
165 im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
166 im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
168 /* Initialize MDDRC */
169 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
170 im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
171 im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
172 im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;
175 for (i = 0; i < 10; i++)
176 im->mddrc.ddr_command = CFG_MICRON_NOP;
178 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
179 im->mddrc.ddr_command = CFG_MICRON_NOP;
180 im->mddrc.ddr_command = CFG_MICRON_RFSH;
181 im->mddrc.ddr_command = CFG_MICRON_NOP;
182 im->mddrc.ddr_command = CFG_MICRON_RFSH;
183 im->mddrc.ddr_command = CFG_MICRON_NOP;
184 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
185 im->mddrc.ddr_command = CFG_MICRON_NOP;
186 im->mddrc.ddr_command = CFG_MICRON_EM2;
187 im->mddrc.ddr_command = CFG_MICRON_NOP;
188 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
189 im->mddrc.ddr_command = CFG_MICRON_EM2;
190 im->mddrc.ddr_command = CFG_MICRON_EM3;
191 im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
192 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
193 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
194 im->mddrc.ddr_command = CFG_MICRON_RFSH;
195 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
196 im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
197 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
198 im->mddrc.ddr_command = CFG_MICRON_NOP;
201 im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
202 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;
207 int misc_init_r(void)
210 extern int ads5121_diu_init(void);
212 /* Using this for DIU init before the driver in linux takes over
213 * Enable the TFP410 Encoder (I2C address 0x38)
218 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
219 /* Verify if enabled */
221 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
222 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
225 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
226 /* Verify if enabled */
228 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
229 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
231 #ifdef CONFIG_FSL_DIU_FB
232 #if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
240 int checkboard (void)
242 ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
243 uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
245 printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
247 /* initialize function mux & slew rate IO inter alia on IO Pins */
253 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
254 void ft_board_setup(void *blob, bd_t *bd)
256 ft_cpu_setup(blob, bd);
257 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
259 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */