git.sur5r.net Git - u-boot/blob - board/advantech/dms-ba16/dms-ba16.c

   1 /*
   2  * Copyright 2016 Timesys Corporation
   3  * Copyright 2016 Advantech Corporation
   4  * Copyright 2012 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <linux/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/imx-common/mxc_i2c.h>
  16 #include <asm/imx-common/iomux-v3.h>
  17 #include <asm/imx-common/boot_mode.h>
  18 #include <asm/imx-common/video.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <miiphy.h>
  22 #include <netdev.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <i2c.h>
  28 #include <pwm.h>
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  32         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  33         PAD_CTL_HYS)
  34
  35 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  36         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  37         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  38
  39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  40         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  41         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  42
  43 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  44         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  45
  46 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  47         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  48
  49 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  50         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  51
  52 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  53                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  54
  55 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  57         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  58
  59 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  60
  61 int dram_init(void)
  62 {
  63         gd->ram_size = imx_ddr_size();
  64
  65         return 0;
  66 }
  67
  68 static iomux_v3_cfg_t const uart3_pads[] = {
  69         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  70         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  71         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  72         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  73 };
  74
  75 static iomux_v3_cfg_t const uart4_pads[] = {
  76         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  77         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  78 };
  79
  80 static iomux_v3_cfg_t const enet_pads[] = {
  81         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82         MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  90         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  91         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  92         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  93         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  94         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  95         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  96         /* AR8033 PHY Reset */
  97         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  98 };
  99
 100 static void setup_iomux_enet(void)
 101 {
 102         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 103
 104         /* Reset AR8033 PHY */
 105         gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
 106         mdelay(10);
 107         gpio_set_value(IMX_GPIO_NR(1, 28), 1);
 108         mdelay(1);
 109 }
 110
 111 static iomux_v3_cfg_t const usdhc2_pads[] = {
 112         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 113         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 114         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(NO_PAD_CTRL),
 119 };
 120
 121 static iomux_v3_cfg_t const usdhc3_pads[] = {
 122         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 123         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 124         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 125         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 126         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 127         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133 };
 134
 135 static iomux_v3_cfg_t const usdhc4_pads[] = {
 136         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 147         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 148 };
 149
 150 static iomux_v3_cfg_t const ecspi1_pads[] = {
 151         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 152         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 153         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 154         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 155 };
 156
 157 static struct i2c_pads_info i2c_pad_info1 = {
 158         .scl = {
 159                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
 160                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
 161                 .gp = IMX_GPIO_NR(5, 27)
 162         },
 163         .sda = {
 164                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
 165                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
 166                 .gp = IMX_GPIO_NR(5, 26)
 167         }
 168 };
 169
 170 static struct i2c_pads_info i2c_pad_info2 = {
 171         .scl = {
 172                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 173                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 174                 .gp = IMX_GPIO_NR(4, 12)
 175         },
 176         .sda = {
 177                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 178                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 179                 .gp = IMX_GPIO_NR(4, 13)
 180         }
 181 };
 182
 183 static struct i2c_pads_info i2c_pad_info3 = {
 184         .scl = {
 185                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
 186                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
 187                 .gp = IMX_GPIO_NR(1, 3)
 188         },
 189         .sda = {
 190                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 191                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 192                 .gp = IMX_GPIO_NR(1, 6)
 193         }
 194 };
 195
 196 #ifdef CONFIG_MXC_SPI
 197 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 198 {
 199         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
 200 }
 201
 202 static void setup_spi(void)
 203 {
 204         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 205 }
 206 #endif
 207
 208 static iomux_v3_cfg_t const pcie_pads[] = {
 209         MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 210         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 211 };
 212
 213 static void setup_pcie(void)
 214 {
 215         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 216 }
 217
 218 static void setup_iomux_uart(void)
 219 {
 220         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 221         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 222 }
 223
 224 #ifdef CONFIG_FSL_ESDHC
 225 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 226         {USDHC2_BASE_ADDR},
 227         {USDHC3_BASE_ADDR},
 228         {USDHC4_BASE_ADDR},
 229 };
 230
 231 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 232 #define USDHC4_CD_GPIO  IMX_GPIO_NR(6, 11)
 233
 234 int board_mmc_getcd(struct mmc *mmc)
 235 {
 236         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 237         int ret = 0;
 238
 239         switch (cfg->esdhc_base) {
 240         case USDHC2_BASE_ADDR:
 241                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 242                 break;
 243         case USDHC3_BASE_ADDR:
 244                 ret = 1; /* eMMC is always present */
 245                 break;
 246         case USDHC4_BASE_ADDR:
 247                 ret = !gpio_get_value(USDHC4_CD_GPIO);
 248                 break;
 249         }
 250
 251         return ret;
 252 }
 253
 254 int board_mmc_init(bd_t *bis)
 255 {
 256         int ret;
 257         int i;
 258
 259         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 260                 switch (i) {
 261                 case 0:
 262                         imx_iomux_v3_setup_multiple_pads(
 263                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 264                         gpio_direction_input(USDHC2_CD_GPIO);
 265                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 266                         break;
 267                 case 1:
 268                         imx_iomux_v3_setup_multiple_pads(
 269                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 270                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 271                         break;
 272                 case 2:
 273                         imx_iomux_v3_setup_multiple_pads(
 274                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 275                         gpio_direction_input(USDHC4_CD_GPIO);
 276                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 277                         break;
 278                 default:
 279                         printf("Warning: you configured more USDHC controllers\n"
 280                                "(%d) then supported by the board (%d)\n",
 281                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 282                         return -EINVAL;
 283                 }
 284
 285                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 286                 if (ret)
 287                         return ret;
 288         }
 289
 290         return 0;
 291 }
 292 #endif
 293
 294 static int mx6_rgmii_rework(struct phy_device *phydev)
 295 {
 296         /* set device address 0x7 */
 297         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 298         /* offset 0x8016: CLK_25M Clock Select */
 299         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 300         /* enable register write, no post increment, address 0x7 */
 301         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 302         /* set to 125 MHz from local PLL source */
 303         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 304         /* set debug port address: SerDes Test and System Mode Control */
 305         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 306         /* enable rgmii tx clock delay */
 307         /* set the reserved bits to avoid board specific voltage peak issue*/
 308         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 309
 310         return 0;
 311 }
 312
 313 int board_phy_config(struct phy_device *phydev)
 314 {
 315         mx6_rgmii_rework(phydev);
 316
 317         if (phydev->drv->config)
 318                 phydev->drv->config(phydev);
 319
 320         return 0;
 321 }
 322
 323 #if defined(CONFIG_VIDEO_IPUV3)
 324 static iomux_v3_cfg_t const backlight_pads[] = {
 325         /* Power for LVDS Display */
 326         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 327 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 328         /* Backlight enable for LVDS display */
 329         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 330 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 331         /* backlight PWM brightness control */
 332         MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 333 };
 334
 335 static void do_enable_hdmi(struct display_info_t const *dev)
 336 {
 337         imx_enable_hdmi_phy();
 338 }
 339
 340 int board_cfb_skip(void)
 341 {
 342         gpio_direction_output(LVDS_POWER_GP, 1);
 343
 344         return 0;
 345 }
 346
 347 static int detect_baseboard(struct display_info_t const *dev)
 348 {
 349         return 0 == dev->addr;
 350 }
 351
 352 struct display_info_t const displays[] = {{
 353         .bus    = -1,
 354         .addr   = 0,
 355         .pixfmt = IPU_PIX_FMT_RGB24,
 356         .detect = detect_baseboard,
 357         .enable = NULL,
 358         .mode   = {
 359                 .name           = "SHARP-LQ156M1LG21",
 360                 .refresh        = 60,
 361                 .xres           = 1920,
 362                 .yres           = 1080,
 363                 .pixclock       = 7851,
 364                 .left_margin    = 100,
 365                 .right_margin   = 40,
 366                 .upper_margin   = 30,
 367                 .lower_margin   = 3,
 368                 .hsync_len      = 10,
 369                 .vsync_len      = 2,
 370                 .sync           = FB_SYNC_EXT,
 371                 .vmode          = FB_VMODE_NONINTERLACED
 372 } }, {
 373         .bus    = -1,
 374         .addr   = 3,
 375         .pixfmt = IPU_PIX_FMT_RGB24,
 376         .detect = detect_hdmi,
 377         .enable = do_enable_hdmi,
 378         .mode   = {
 379                 .name           = "HDMI",
 380                 .refresh        = 60,
 381                 .xres           = 1024,
 382                 .yres           = 768,
 383                 .pixclock       = 15385,
 384                 .left_margin    = 220,
 385                 .right_margin   = 40,
 386                 .upper_margin   = 21,
 387                 .lower_margin   = 7,
 388                 .hsync_len      = 60,
 389                 .vsync_len      = 10,
 390                 .sync           = FB_SYNC_EXT,
 391                 .vmode          = FB_VMODE_NONINTERLACED
 392 } } };
 393 size_t display_count = ARRAY_SIZE(displays);
 394
 395 static void setup_display(void)
 396 {
 397         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 398         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 399
 400         clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 401
 402         imx_setup_hdmi();
 403
 404         /* Set LDB_DI0 as clock source for IPU_DI0 */
 405         clrsetbits_le32(&mxc_ccm->chsccdr,
 406                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 407                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 408                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 409
 410         /* Turn on IPU LDB DI0 clocks */
 411         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 412
 413         enable_ipu_clock();
 414
 415         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 416                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
 417                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 418                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 419                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 420                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 421                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 422                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 423                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 424                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 425                &iomux->gpr[2]);
 426
 427         clrsetbits_le32(&iomux->gpr[3],
 428                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 429                         IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 430                         IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
 431                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 432                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 433
 434         /* backlights off until needed */
 435         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 436                                          ARRAY_SIZE(backlight_pads));
 437
 438         gpio_direction_input(LVDS_POWER_GP);
 439         gpio_direction_input(LVDS_BACKLIGHT_GP);
 440 }
 441 #endif /* CONFIG_VIDEO_IPUV3 */
 442
 443 /*
 444  * Do not overwrite the console
 445  * Use always serial for U-Boot console
 446  */
 447 int overwrite_console(void)
 448 {
 449         return 1;
 450 }
 451
 452 int board_eth_init(bd_t *bis)
 453 {
 454         setup_iomux_enet();
 455         setup_pcie();
 456
 457         return cpu_eth_init(bis);
 458 }
 459
 460 static iomux_v3_cfg_t const misc_pads[] = {
 461         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 462         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 463         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 464         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 465         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 466         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 467         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 468 };
 469 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 470 #define WIFI_EN IMX_GPIO_NR(6, 14)
 471
 472 int setup_ba16_sata(void)
 473 {
 474         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 475         int ret;
 476
 477         ret = enable_sata_clock();
 478         if (ret)
 479                 return ret;
 480
 481         clrsetbits_le32(&iomuxc_regs->gpr[13],
 482                         IOMUXC_GPR13_SATA_MASK,
 483                         IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
 484                         |IOMUXC_GPR13_SATA_PHY_7_SATA2M
 485                         |IOMUXC_GPR13_SATA_SPEED_3G
 486                         |(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
 487                         |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
 488                         |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
 489                         |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
 490                         |IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
 491                         |IOMUXC_GPR13_SATA_PHY_1_SLOW);
 492
 493         return 0;
 494 }
 495
 496 int board_early_init_f(void)
 497 {
 498         imx_iomux_v3_setup_multiple_pads(misc_pads,
 499                                          ARRAY_SIZE(misc_pads));
 500
 501         setup_iomux_uart();
 502
 503 #if defined(CONFIG_VIDEO_IPUV3)
 504         /* Set LDB clock to PLL2 PFD0 */
 505         select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK);
 506 #endif
 507         return 0;
 508 }
 509
 510 int board_init(void)
 511 {
 512         gpio_direction_output(SUS_S3_OUT, 1);
 513         gpio_direction_output(WIFI_EN, 1);
 514 #if defined(CONFIG_VIDEO_IPUV3)
 515         setup_display();
 516 #endif
 517         /* address of boot parameters */
 518         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 519
 520 #ifdef CONFIG_MXC_SPI
 521         setup_spi();
 522 #endif
 523         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 524         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 525         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 526
 527         return 0;
 528 }
 529
 530 #ifdef CONFIG_CMD_BMODE
 531 static const struct boot_mode board_boot_modes[] = {
 532         /* 4 bit bus width */
 533         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 534         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 535         {NULL,   0},
 536 };
 537 #endif
 538
 539 void pmic_init(void)
 540 {
 541
 542 #define DA9063_ADDR 0x58
 543 #define BCORE2_CONF 0x9D
 544 #define BCORE1_CONF 0x9E
 545 #define BPRO_CONF 0x9F
 546 #define BIO_CONF 0xA0
 547 #define BMEM_CONF 0xA1
 548 #define BPERI_CONF 0xA2
 549 #define MODE_BIT_H 7
 550 #define MODE_BIT_L 6
 551
 552         uchar val;
 553         i2c_set_bus_num(2);
 554
 555         i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1);
 556         val |= (1 << MODE_BIT_H);
 557         val &= ~(1 << MODE_BIT_L);
 558         i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1);
 559
 560         i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1);
 561         val |= (1 << MODE_BIT_H);
 562         val &= ~(1 << MODE_BIT_L);
 563         i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1);
 564
 565         i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1);
 566         val |= (1 << MODE_BIT_H);
 567         val &= ~(1 << MODE_BIT_L);
 568         i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1);
 569
 570         i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1);
 571         val |= (1 << MODE_BIT_H);
 572         val &= ~(1 << MODE_BIT_L);
 573         i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1);
 574
 575         i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1);
 576         val |= (1 << MODE_BIT_H);
 577         val &= ~(1 << MODE_BIT_L);
 578         i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1);
 579
 580         i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1);
 581         val |= (1 << MODE_BIT_H);
 582         val &= ~(1 << MODE_BIT_L);
 583         i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1);
 584
 585 }
 586
 587 int board_late_init(void)
 588 {
 589 #ifdef CONFIG_CMD_BMODE
 590         add_board_boot_modes(board_boot_modes);
 591 #endif
 592
 593 #if defined(CONFIG_VIDEO_IPUV3)
 594         /*
 595          * We need at least 200ms between power on and backlight on
 596          * as per specifications from CHI MEI
 597          */
 598         mdelay(250);
 599
 600         /* enable backlight PWM 1 */
 601         pwm_init(0, 0, 0);
 602
 603         /* duty cycle 5000000ns, period: 5000000ns */
 604         pwm_config(0, 5000000, 5000000);
 605
 606         /* Backlight Power */
 607         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 608
 609         pwm_enable(0);
 610 #endif
 611
 612 #ifdef CONFIG_CMD_SATA
 613         setup_ba16_sata();
 614 #endif
 615
 616         /* board specific pmic init */
 617         pmic_init();
 618
 619         return 0;
 620 }
 621
 622 int checkboard(void)
 623 {
 624         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 625         return 0;
 626 }