git.sur5r.net Git - u-boot/blob - board/alphaproject/ap_sh4a_4a/lowlevel_init.S

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2011, 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   4  * Copyright (C) 2011, 2012 Renesas Solutions Corp.
   5  */
   6 #include <config.h>
   7 #include <asm/processor.h>
   8 #include <asm/macro.h>
   9
  10 #include <asm/processor.h>
  11
  12         .global lowlevel_init
  13
  14         .text
  15         .align  2
  16
  17 lowlevel_init:
  18
  19         /* WDT */
  20         write32 WDTCSR_A, WDTCSR_D
  21
  22         /* MMU */
  23         write32 MMUCR_A, MMUCR_D
  24
  25         write32 FRQCR2_A, FRQCR2_D
  26         write32 FRQCR0_A, FRQCR0_D
  27
  28         write32 CS0CTRL_A, CS0CTRL_D
  29         write32 CS1CTRL_A, CS1CTRL_D
  30         write32 CS0CTRL2_A, CS0CTRL2_D
  31
  32         write32 CSPWCR0_A, CSPWCR0_D
  33         write32 CSPWCR1_A, CSPWCR1_D
  34         write32 CS1GDST_A, CS1GDST_D
  35
  36         # clock mode check
  37         mov.l   MODEMR, r1
  38         mov.l   @r1, r0
  39         and             #6, r0 /* Check 1 and 2 bit.*/
  40         cmp/eq  #2, r0 /* 0x02 is 533Mhz mode */
  41         bt      init_lbsc_533
  42
  43 init_lbsc_400:
  44
  45         write32 CSWCR0_A, CSWCR0_D_400
  46         write32 CSWCR1_A, CSWCR1_D
  47
  48         bra     init_dbsc3_400_pad
  49         nop
  50
  51         .align 2
  52
  53 MODEMR:         .long   0xFFCC0020
  54 WDTCSR_A:       .long   0xFFCC0004
  55 WDTCSR_D:       .long   0xA5000000
  56 MMUCR_A:        .long   0xFF000010
  57 MMUCR_D:        .long   0x00000004
  58
  59 FRQCR2_A:       .long   0xFFC80008
  60 FRQCR2_D:       .long   0x00000000
  61 FRQCR0_A:       .long   0xFFC80000
  62 FRQCR0_D:       .long   0xCF000001
  63
  64 CS0CTRL_A:      .long   0xFF800200
  65 CS0CTRL_D:      .long   0x00000020
  66 CS1CTRL_A:      .long   0xFF800204
  67 CS1CTRL_D:      .long   0x00000020
  68
  69 CS0CTRL2_A:     .long   0xFF800220
  70 CS0CTRL2_D:     .long   0x00004000
  71
  72 CSPWCR0_A:      .long   0xFF800280
  73 CSPWCR0_D:      .long   0x00000000
  74 CSPWCR1_A:      .long   0xFF800284
  75 CSPWCR1_D:      .long   0x00000000
  76 CS1GDST_A:      .long   0xFF8002C0
  77 CS1GDST_D:      .long   0x00000011
  78
  79 init_lbsc_533:
  80
  81         write32 CSWCR0_A, CSWCR0_D_533
  82         write32 CSWCR1_A, CSWCR1_D
  83
  84         bra     init_dbsc3_533_pad
  85         nop
  86
  87         .align 2
  88
  89 CSWCR0_A:       .long   0xFF800230
  90 CSWCR0_D_533:   .long   0x01120104
  91 CSWCR0_D_400:   .long   0x02120114
  92 CSWCR1_A:       .long   0xFF800234
  93 CSWCR1_D:       .long   0x077F077F
  94
  95 init_dbsc3_400_pad:
  96
  97         write32 DBPDCNT3_A,     DBPDCNT3_D
  98         wait_timer      WAIT_200US_400
  99
 100         write32 DBPDCNT0_A,     DBPDCNT0_D_400
 101         write32 DBPDCNT3_A,     DBPDCNT3_D0
 102         write32 DBPDCNT1_A,     DBPDCNT1_D
 103
 104         write32 DBPDCNT3_A,     DBPDCNT3_D1
 105         wait_timer WAIT_32MCLK
 106
 107         write32 DBPDCNT3_A,     DBPDCNT3_D2
 108         wait_timer WAIT_100US_400
 109
 110         write32 DBPDCNT3_A,     DBPDCNT3_D3
 111         wait_timer WAIT_16MCLK
 112
 113         write32 DBPDCNT3_A,     DBPDCNT3_D4
 114         wait_timer WAIT_200US_400
 115
 116         write32 DBPDCNT3_A,     DBPDCNT3_D5
 117         wait_timer WAIT_1MCLK
 118
 119         write32 DBPDCNT3_A,     DBPDCNT3_D6
 120         wait_timer WAIT_10KMCLK
 121
 122         bra init_dbsc3_ctrl_400
 123         nop
 124
 125         .align 2
 126
 127 init_dbsc3_533_pad:
 128
 129         write32 DBPDCNT3_A,     DBPDCNT3_D
 130         wait_timer      WAIT_200US_533
 131
 132         write32 DBPDCNT0_A,     DBPDCNT0_D_533
 133         write32 DBPDCNT3_A,     DBPDCNT3_D0
 134         write32 DBPDCNT1_A,     DBPDCNT1_D
 135
 136         write32 DBPDCNT3_A,     DBPDCNT3_D1
 137         wait_timer WAIT_32MCLK
 138
 139         write32 DBPDCNT3_A,     DBPDCNT3_D2
 140         wait_timer WAIT_100US_533
 141
 142         write32 DBPDCNT3_A,     DBPDCNT3_D3
 143         wait_timer WAIT_16MCLK
 144
 145         write32 DBPDCNT3_A,     DBPDCNT3_D4
 146         wait_timer WAIT_200US_533
 147
 148         write32 DBPDCNT3_A,     DBPDCNT3_D5
 149         wait_timer WAIT_1MCLK
 150
 151         write32 DBPDCNT3_A,     DBPDCNT3_D6
 152         wait_timer      WAIT_10KMCLK
 153
 154         bra init_dbsc3_ctrl_533
 155         nop
 156
 157         .align 2
 158
 159 WAIT_200US_400: .long   40000
 160 WAIT_200US_533: .long   53300
 161 WAIT_100US_400: .long   20000
 162 WAIT_100US_533: .long   26650
 163 WAIT_32MCLK:    .long   32
 164 WAIT_16MCLK:    .long   16
 165 WAIT_1MCLK:             .long   1
 166 WAIT_10KMCLK:   .long   10000
 167
 168 DBPDCNT0_A:             .long   0xFE800200
 169 DBPDCNT0_D_533: .long   0x00010245
 170 DBPDCNT0_D_400: .long   0x00010235
 171 DBPDCNT1_A:             .long   0xFE800204
 172 DBPDCNT1_D:             .long   0x00000014
 173 DBPDCNT3_A:             .long   0xFE80020C
 174 DBPDCNT3_D:             .long   0x80000000
 175 DBPDCNT3_D0:    .long   0x800F0000
 176 DBPDCNT3_D1:    .long   0x800F1000
 177 DBPDCNT3_D2:    .long   0x820F1000
 178 DBPDCNT3_D3:    .long   0x860F1000
 179 DBPDCNT3_D4:    .long   0x870F1000
 180 DBPDCNT3_D5:    .long   0x870F3000
 181 DBPDCNT3_D6:    .long   0x870F7000
 182
 183 init_dbsc3_ctrl_400:
 184
 185         write32 DBKIND_A, DBKIND_D
 186         write32 DBCONF_A, DBCONF_D
 187
 188         write32 DBTR0_A,        DBTR0_D_400
 189         write32 DBTR1_A,        DBTR1_D_400
 190         write32 DBTR2_A,        DBTR2_D
 191         write32 DBTR3_A,        DBTR3_D_400
 192         write32 DBTR4_A,        DBTR4_D_400
 193         write32 DBTR5_A,        DBTR5_D_400
 194         write32 DBTR6_A,        DBTR6_D_400
 195         write32 DBTR7_A,        DBTR7_D
 196         write32 DBTR8_A,        DBTR8_D_400
 197         write32 DBTR9_A,        DBTR9_D
 198         write32 DBTR10_A,       DBTR10_D_400
 199         write32 DBTR11_A,       DBTR11_D
 200         write32 DBTR12_A,       DBTR12_D_400
 201         write32 DBTR13_A,       DBTR13_D_400
 202         write32 DBTR14_A,       DBTR14_D
 203         write32 DBTR15_A,       DBTR15_D
 204         write32 DBTR16_A,       DBTR16_D_400
 205         write32 DBTR17_A,       DBTR17_D_400
 206         write32 DBTR18_A,       DBTR18_D_400
 207
 208         write32 DBBL_A, DBBL_D
 209         write32 DBRNK0_A,       DBRNK0_D
 210
 211         write32 DBCMD_A,        DBCMD_D0_400
 212         write32 DBCMD_A,        DBCMD_D1
 213         write32 DBCMD_A,        DBCMD_D2
 214         write32 DBCMD_A,        DBCMD_D3
 215         write32 DBCMD_A,        DBCMD_D4
 216         write32 DBCMD_A,        DBCMD_D5_400
 217         write32 DBCMD_A,        DBCMD_D6
 218         write32 DBCMD_A,        DBCMD_D7
 219         write32 DBCMD_A,        DBCMD_D8
 220         write32 DBCMD_A,        DBCMD_D9_400
 221         write32 DBCMD_A,        DBCMD_D10
 222         write32 DBCMD_A,        DBCMD_D11
 223         write32 DBCMD_A,        DBCMD_D12
 224
 225         write32 DBRFCNF0_A,     DBRFCNF0_D
 226         write32 DBRFCNF1_A,     DBRFCNF1_D_400
 227         write32 DBRFCNF2_A,     DBRFCNF2_D
 228         write32 DBRFEN_A,       DBRFEN_D
 229         write32 DBACEN_A,       DBACEN_D
 230         write32 DBACEN_A,       DBACEN_D
 231
 232         /* Dummy read */
 233         mov.l DBWAIT_A, r1
 234         synco
 235         mov.l @r1, r0
 236         synco
 237
 238         /* Dummy read */
 239         mov.l SDRAM_A, r1
 240         synco
 241         mov.l @r1, r0
 242         synco
 243
 244         /* need sleep 186A0 */
 245
 246         bra     finish_init_sh7734
 247         nop
 248
 249         .align 2
 250
 251 init_dbsc3_ctrl_533:
 252
 253         write32 DBKIND_A, DBKIND_D
 254         write32 DBCONF_A, DBCONF_D
 255
 256         write32 DBTR0_A,        DBTR0_D_533
 257         write32 DBTR1_A,        DBTR1_D_533
 258         write32 DBTR2_A,        DBTR2_D
 259         write32 DBTR3_A,        DBTR3_D_533
 260         write32 DBTR4_A,        DBTR4_D_533
 261         write32 DBTR5_A,        DBTR5_D_533
 262         write32 DBTR6_A,        DBTR6_D_533
 263         write32 DBTR7_A,        DBTR7_D
 264         write32 DBTR8_A,        DBTR8_D_533
 265         write32 DBTR9_A,        DBTR9_D
 266         write32 DBTR10_A,       DBTR10_D_533
 267         write32 DBTR11_A,       DBTR11_D
 268         write32 DBTR12_A,       DBTR12_D_533
 269         write32 DBTR13_A,       DBTR13_D_533
 270         write32 DBTR14_A,       DBTR14_D
 271         write32 DBTR15_A,       DBTR15_D
 272         write32 DBTR16_A,       DBTR16_D_533
 273         write32 DBTR17_A,       DBTR17_D_533
 274         write32 DBTR18_A,       DBTR18_D_533
 275
 276         write32 DBBL_A, DBBL_D
 277         write32 DBRNK0_A,       DBRNK0_D
 278
 279         write32 DBCMD_A,        DBCMD_D0_533
 280         write32 DBCMD_A,        DBCMD_D1
 281         write32 DBCMD_A,        DBCMD_D2
 282         write32 DBCMD_A,        DBCMD_D3
 283         write32 DBCMD_A,        DBCMD_D4
 284         write32 DBCMD_A,        DBCMD_D5_533
 285         write32 DBCMD_A,        DBCMD_D6
 286         write32 DBCMD_A,        DBCMD_D7
 287         write32 DBCMD_A,        DBCMD_D8
 288         write32 DBCMD_A,        DBCMD_D9_533
 289         write32 DBCMD_A,        DBCMD_D10
 290         write32 DBCMD_A,        DBCMD_D11
 291         write32 DBCMD_A,        DBCMD_D12
 292
 293         write32 DBRFCNF0_A,     DBRFCNF0_D
 294         write32 DBRFCNF1_A,     DBRFCNF1_D_533
 295         write32 DBRFCNF2_A,     DBRFCNF2_D
 296         write32 DBRFEN_A,       DBRFEN_D
 297         write32 DBACEN_A,       DBACEN_D
 298         write32 DBACEN_A,       DBACEN_D
 299
 300         /* Dummy read */
 301         mov.l DBWAIT_A, r1
 302         synco
 303         mov.l @r1, r0
 304         synco
 305
 306         /* Dummy read */
 307         mov.l SDRAM_A, r1
 308         synco
 309         mov.l @r1, r0
 310         synco
 311
 312         /* need sleep 186A0 */
 313
 314         bra     finish_init_sh7734
 315         nop
 316
 317         .align 2
 318
 319 DBKIND_A:       .long   0xFE800020
 320 DBKIND_D:       .long   0x00000005
 321 DBCONF_A:       .long   0xFE800024
 322 DBCONF_D:       .long   0x0D020A01
 323
 324 DBTR0_A:        .long   0xFE800040
 325 DBTR0_D_533:.long       0x00000004
 326 DBTR0_D_400:.long       0x00000003
 327 DBTR1_A:        .long   0xFE800044
 328 DBTR1_D_533:.long       0x00000003
 329 DBTR1_D_400:.long       0x00000002
 330 DBTR2_A:        .long   0xFE800048
 331 DBTR2_D:        .long   0x00000000
 332 DBTR3_A:        .long   0xFE800050
 333 DBTR3_D_533:.long       0x00000004
 334 DBTR3_D_400:.long       0x00000003
 335
 336 DBTR4_A:        .long   0xFE800054
 337 DBTR4_D_533:.long       0x00050004
 338 DBTR4_D_400:.long       0x00050003
 339
 340 DBTR5_A:        .long   0xFE800058
 341 DBTR5_D_533:.long       0x0000000F
 342 DBTR5_D_400:.long       0x0000000B
 343
 344 DBTR6_A:        .long   0xFE80005C
 345 DBTR6_D_533:.long       0x0000000B
 346 DBTR6_D_400:.long       0x00000008
 347
 348 DBTR7_A:        .long   0xFE800060
 349 DBTR7_D:        .long   0x00000002
 350
 351 DBTR8_A:        .long   0xFE800064
 352 DBTR8_D_533:.long       0x0000000D
 353 DBTR8_D_400:.long       0x0000000A
 354
 355 DBTR9_A:        .long   0xFE800068
 356 DBTR9_D:        .long   0x00000002
 357
 358 DBTR10_A:       .long   0xFE80006C
 359 DBTR10_D_533:.long      0x00000004
 360 DBTR10_D_400:.long      0x00000003
 361
 362 DBTR11_A:       .long   0xFE800070
 363 DBTR11_D:       .long   0x00000008
 364
 365 DBTR12_A:       .long   0xFE800074
 366 DBTR12_D_533:.long      0x00000009
 367 DBTR12_D_400:.long      0x00000008
 368
 369 DBTR13_A:       .long   0xFE800078
 370 DBTR13_D_533:.long      0x00000022
 371 DBTR13_D_400:.long      0x0000001A
 372
 373 DBTR14_A:       .long   0xFE80007C
 374 DBTR14_D:       .long   0x00070002
 375
 376 DBTR15_A:       .long   0xFE800080
 377 DBTR15_D:       .long   0x00000003
 378
 379 DBTR16_A:       .long   0xFE800084
 380 DBTR16_D_533:.long      0x120A1001
 381 DBTR16_D_400:.long      0x12091001
 382
 383 DBTR17_A:       .long   0xFE800088
 384 DBTR17_D_533:.long      0x00040000
 385 DBTR17_D_400:.long      0x00030000
 386
 387 DBTR18_A:       .long   0xFE80008C
 388 DBTR18_D_533:.long      0x02010200
 389 DBTR18_D_400:.long      0x02000207
 390
 391 DBBL_A: .long   0xFE8000B0
 392 DBBL_D: .long   0x00000000
 393
 394 DBRNK0_A:               .long   0xFE800100
 395 DBRNK0_D:               .long   0x00000001
 396
 397 DBCMD_A:                .long   0xFE800018
 398 DBCMD_D0_533:   .long   0x1100006B
 399 DBCMD_D0_400:   .long   0x11000050
 400 DBCMD_D1:               .long   0x0B000000
 401 DBCMD_D2:               .long   0x2A004000
 402 DBCMD_D3:               .long   0x2B006000
 403 DBCMD_D4:               .long   0x29002044
 404 DBCMD_D5_533:   .long   0x28000743
 405 DBCMD_D5_400:   .long   0x28000533
 406 DBCMD_D6:               .long   0x0B000000
 407 DBCMD_D7:               .long   0x0C000000
 408 DBCMD_D8:               .long   0x0C000000
 409 DBCMD_D9_533:   .long   0x28000643
 410 DBCMD_D9_400:   .long   0x28000433
 411 DBCMD_D10:              .long   0x000000C8
 412 DBCMD_D11:              .long   0x290023C4
 413 DBCMD_D12:              .long   0x29002004
 414
 415 DBRFCNF0_A:             .long   0xFE8000E0
 416 DBRFCNF0_D:             .long   0x000001FF
 417 DBRFCNF1_A:             .long   0xFE8000E4
 418 DBRFCNF1_D_533: .long   0x00000805
 419 DBRFCNF1_D_400: .long   0x00000618
 420
 421 DBRFCNF2_A:             .long   0xFE8000E8
 422 DBRFCNF2_D:             .long   0x00000000
 423
 424 DBRFEN_A:               .long   0xFE800014
 425 DBRFEN_D:               .long   0x00000001
 426
 427 DBACEN_A:               .long   0xFE800010
 428 DBACEN_D:               .long   0x00000001
 429
 430 DBWAIT_A:               .long   0xFE80001C
 431 SDRAM_A:                .long   0x0C000000
 432
 433 finish_init_sh7734:
 434         write32 CCR_A,  CCR_D
 435
 436         stc sr, r0
 437         mov.l  SR_MASK_D, r1
 438         and r1, r0
 439         ldc r0, sr
 440
 441         rts
 442         nop
 443
 444         .align  2
 445
 446 CCR_A:  .long   0xFF00001C
 447 CCR_D:  .long   0x0000090B
 448 SR_MASK_D:      .long   0xEFFFFF0F