git.sur5r.net Git - u-boot/blob - board/alphaproject/ap_sh4a_4a/lowlevel_init.S

   1 /*
   2  * Copyright (C) 2011, 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   3  * Copyright (C) 2011, 2012 Renesas Solutions Corp.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16 #include <config.h>
  17 #include <version.h>
  18 #include <asm/processor.h>
  19 #include <asm/macro.h>
  20
  21 #include <asm/processor.h>
  22
  23         .global lowlevel_init
  24
  25         .text
  26         .align  2
  27
  28 lowlevel_init:
  29
  30         /* WDT */
  31         write32 WDTCSR_A, WDTCSR_D
  32
  33         /* MMU */
  34         write32 MMUCR_A, MMUCR_D
  35
  36         write32 FRQCR2_A, FRQCR2_D
  37         write32 FRQCR0_A, FRQCR0_D
  38
  39         write32 CS0CTRL_A, CS0CTRL_D
  40         write32 CS1CTRL_A, CS1CTRL_D
  41         write32 CS0CTRL2_A, CS0CTRL2_D
  42
  43         write32 CSPWCR0_A, CSPWCR0_D
  44         write32 CSPWCR1_A, CSPWCR1_D
  45         write32 CS1GDST_A, CS1GDST_D
  46
  47         # clock mode check
  48         mov.l   MODEMR, r1
  49         mov.l   @r1, r0
  50         and             #6, r0 /* Check 1 and 2 bit.*/
  51         cmp/eq  #2, r0 /* 0x02 is 533Mhz mode */
  52         bt      init_lbsc_533
  53
  54 init_lbsc_400:
  55
  56         write32 CSWCR0_A, CSWCR0_D_400
  57         write32 CSWCR1_A, CSWCR1_D
  58
  59         bra     init_dbsc3_400_pad
  60         nop
  61
  62         .align 2
  63
  64 MODEMR:         .long   0xFFCC0020
  65 WDTCSR_A:       .long   0xFFCC0004
  66 WDTCSR_D:       .long   0xA5000000
  67 MMUCR_A:        .long   0xFF000010
  68 MMUCR_D:        .long   0x00000004
  69
  70 FRQCR2_A:       .long   0xFFC80008
  71 FRQCR2_D:       .long   0x00000000
  72 FRQCR0_A:       .long   0xFFC80000
  73 FRQCR0_D:       .long   0xCF000001
  74
  75 CS0CTRL_A:      .long   0xFF800200
  76 CS0CTRL_D:      .long   0x00000020
  77 CS1CTRL_A:      .long   0xFF800204
  78 CS1CTRL_D:      .long   0x00000020
  79
  80 CS0CTRL2_A:     .long   0xFF800220
  81 CS0CTRL2_D:     .long   0x00004000
  82
  83 CSPWCR0_A:      .long   0xFF800280
  84 CSPWCR0_D:      .long   0x00000000
  85 CSPWCR1_A:      .long   0xFF800284
  86 CSPWCR1_D:      .long   0x00000000
  87 CS1GDST_A:      .long   0xFF8002C0
  88 CS1GDST_D:      .long   0x00000011
  89
  90 init_lbsc_533:
  91
  92         write32 CSWCR0_A, CSWCR0_D_533
  93         write32 CSWCR1_A, CSWCR1_D
  94
  95         bra     init_dbsc3_533_pad
  96         nop
  97
  98         .align 2
  99
 100 CSWCR0_A:       .long   0xFF800230
 101 CSWCR0_D_533:   .long   0x01120104
 102 CSWCR0_D_400:   .long   0x02120114
 103 CSWCR1_A:       .long   0xFF800234
 104 CSWCR1_D:       .long   0x077F077F
 105
 106 init_dbsc3_400_pad:
 107
 108         write32 DBPDCNT3_A,     DBPDCNT3_D
 109         wait_timer      WAIT_200US_400
 110
 111         write32 DBPDCNT0_A,     DBPDCNT0_D_400
 112         write32 DBPDCNT3_A,     DBPDCNT3_D0
 113         write32 DBPDCNT1_A,     DBPDCNT1_D
 114
 115         write32 DBPDCNT3_A,     DBPDCNT3_D1
 116         wait_timer WAIT_32MCLK
 117
 118         write32 DBPDCNT3_A,     DBPDCNT3_D2
 119         wait_timer WAIT_100US_400
 120
 121         write32 DBPDCNT3_A,     DBPDCNT3_D3
 122         wait_timer WAIT_16MCLK
 123
 124         write32 DBPDCNT3_A,     DBPDCNT3_D4
 125         wait_timer WAIT_200US_400
 126
 127         write32 DBPDCNT3_A,     DBPDCNT3_D5
 128         wait_timer WAIT_1MCLK
 129
 130         write32 DBPDCNT3_A,     DBPDCNT3_D6
 131         wait_timer WAIT_10KMCLK
 132
 133         bra init_dbsc3_ctrl_400
 134         nop
 135
 136         .align 2
 137
 138 init_dbsc3_533_pad:
 139
 140         write32 DBPDCNT3_A,     DBPDCNT3_D
 141         wait_timer      WAIT_200US_533
 142
 143         write32 DBPDCNT0_A,     DBPDCNT0_D_533
 144         write32 DBPDCNT3_A,     DBPDCNT3_D0
 145         write32 DBPDCNT1_A,     DBPDCNT1_D
 146
 147         write32 DBPDCNT3_A,     DBPDCNT3_D1
 148         wait_timer WAIT_32MCLK
 149
 150         write32 DBPDCNT3_A,     DBPDCNT3_D2
 151         wait_timer WAIT_100US_533
 152
 153         write32 DBPDCNT3_A,     DBPDCNT3_D3
 154         wait_timer WAIT_16MCLK
 155
 156         write32 DBPDCNT3_A,     DBPDCNT3_D4
 157         wait_timer WAIT_200US_533
 158
 159         write32 DBPDCNT3_A,     DBPDCNT3_D5
 160         wait_timer WAIT_1MCLK
 161
 162         write32 DBPDCNT3_A,     DBPDCNT3_D6
 163         wait_timer      WAIT_10KMCLK
 164
 165         bra init_dbsc3_ctrl_533
 166         nop
 167
 168         .align 2
 169
 170 WAIT_200US_400: .long   40000
 171 WAIT_200US_533: .long   53300
 172 WAIT_100US_400: .long   20000
 173 WAIT_100US_533: .long   26650
 174 WAIT_32MCLK:    .long   32
 175 WAIT_16MCLK:    .long   16
 176 WAIT_1MCLK:             .long   1
 177 WAIT_10KMCLK:   .long   10000
 178
 179 DBPDCNT0_A:             .long   0xFE800200
 180 DBPDCNT0_D_533: .long   0x00010245
 181 DBPDCNT0_D_400: .long   0x00010235
 182 DBPDCNT1_A:             .long   0xFE800204
 183 DBPDCNT1_D:             .long   0x00000014
 184 DBPDCNT3_A:             .long   0xFE80020C
 185 DBPDCNT3_D:             .long   0x80000000
 186 DBPDCNT3_D0:    .long   0x800F0000
 187 DBPDCNT3_D1:    .long   0x800F1000
 188 DBPDCNT3_D2:    .long   0x820F1000
 189 DBPDCNT3_D3:    .long   0x860F1000
 190 DBPDCNT3_D4:    .long   0x870F1000
 191 DBPDCNT3_D5:    .long   0x870F3000
 192 DBPDCNT3_D6:    .long   0x870F7000
 193
 194 init_dbsc3_ctrl_400:
 195
 196         write32 DBKIND_A, DBKIND_D
 197         write32 DBCONF_A, DBCONF_D
 198
 199         write32 DBTR0_A,        DBTR0_D_400
 200         write32 DBTR1_A,        DBTR1_D_400
 201         write32 DBTR2_A,        DBTR2_D
 202         write32 DBTR3_A,        DBTR3_D_400
 203         write32 DBTR4_A,        DBTR4_D_400
 204         write32 DBTR5_A,        DBTR5_D_400
 205         write32 DBTR6_A,        DBTR6_D_400
 206         write32 DBTR7_A,        DBTR7_D
 207         write32 DBTR8_A,        DBTR8_D_400
 208         write32 DBTR9_A,        DBTR9_D
 209         write32 DBTR10_A,       DBTR10_D_400
 210         write32 DBTR11_A,       DBTR11_D
 211         write32 DBTR12_A,       DBTR12_D_400
 212         write32 DBTR13_A,       DBTR13_D_400
 213         write32 DBTR14_A,       DBTR14_D
 214         write32 DBTR15_A,       DBTR15_D
 215         write32 DBTR16_A,       DBTR16_D_400
 216         write32 DBTR17_A,       DBTR17_D_400
 217         write32 DBTR18_A,       DBTR18_D_400
 218
 219         write32 DBBL_A, DBBL_D
 220         write32 DBRNK0_A,       DBRNK0_D
 221
 222         write32 DBCMD_A,        DBCMD_D0_400
 223         write32 DBCMD_A,        DBCMD_D1
 224         write32 DBCMD_A,        DBCMD_D2
 225         write32 DBCMD_A,        DBCMD_D3
 226         write32 DBCMD_A,        DBCMD_D4
 227         write32 DBCMD_A,        DBCMD_D5_400
 228         write32 DBCMD_A,        DBCMD_D6
 229         write32 DBCMD_A,        DBCMD_D7
 230         write32 DBCMD_A,        DBCMD_D8
 231         write32 DBCMD_A,        DBCMD_D9_400
 232         write32 DBCMD_A,        DBCMD_D10
 233         write32 DBCMD_A,        DBCMD_D11
 234         write32 DBCMD_A,        DBCMD_D12
 235
 236         write32 DBRFCNF0_A,     DBRFCNF0_D
 237         write32 DBRFCNF1_A,     DBRFCNF1_D_400
 238         write32 DBRFCNF2_A,     DBRFCNF2_D
 239         write32 DBRFEN_A,       DBRFEN_D
 240         write32 DBACEN_A,       DBACEN_D
 241         write32 DBACEN_A,       DBACEN_D
 242
 243         /* Dummy read */
 244         mov.l DBWAIT_A, r1
 245         synco
 246         mov.l @r1, r0
 247         synco
 248
 249         /* Dummy read */
 250         mov.l SDRAM_A, r1
 251         synco
 252         mov.l @r1, r0
 253         synco
 254
 255         /* need sleep 186A0 */
 256
 257         bra     finish_init_sh7734
 258         nop
 259
 260         .align 2
 261
 262 init_dbsc3_ctrl_533:
 263
 264         write32 DBKIND_A, DBKIND_D
 265         write32 DBCONF_A, DBCONF_D
 266
 267         write32 DBTR0_A,        DBTR0_D_533
 268         write32 DBTR1_A,        DBTR1_D_533
 269         write32 DBTR2_A,        DBTR2_D
 270         write32 DBTR3_A,        DBTR3_D_533
 271         write32 DBTR4_A,        DBTR4_D_533
 272         write32 DBTR5_A,        DBTR5_D_533
 273         write32 DBTR6_A,        DBTR6_D_533
 274         write32 DBTR7_A,        DBTR7_D
 275         write32 DBTR8_A,        DBTR8_D_533
 276         write32 DBTR9_A,        DBTR9_D
 277         write32 DBTR10_A,       DBTR10_D_533
 278         write32 DBTR11_A,       DBTR11_D
 279         write32 DBTR12_A,       DBTR12_D_533
 280         write32 DBTR13_A,       DBTR13_D_533
 281         write32 DBTR14_A,       DBTR14_D
 282         write32 DBTR15_A,       DBTR15_D
 283         write32 DBTR16_A,       DBTR16_D_533
 284         write32 DBTR17_A,       DBTR17_D_533
 285         write32 DBTR18_A,       DBTR18_D_533
 286
 287         write32 DBBL_A, DBBL_D
 288         write32 DBRNK0_A,       DBRNK0_D
 289
 290         write32 DBCMD_A,        DBCMD_D0_533
 291         write32 DBCMD_A,        DBCMD_D1
 292         write32 DBCMD_A,        DBCMD_D2
 293         write32 DBCMD_A,        DBCMD_D3
 294         write32 DBCMD_A,        DBCMD_D4
 295         write32 DBCMD_A,        DBCMD_D5_533
 296         write32 DBCMD_A,        DBCMD_D6
 297         write32 DBCMD_A,        DBCMD_D7
 298         write32 DBCMD_A,        DBCMD_D8
 299         write32 DBCMD_A,        DBCMD_D9_533
 300         write32 DBCMD_A,        DBCMD_D10
 301         write32 DBCMD_A,        DBCMD_D11
 302         write32 DBCMD_A,        DBCMD_D12
 303
 304         write32 DBRFCNF0_A,     DBRFCNF0_D
 305         write32 DBRFCNF1_A,     DBRFCNF1_D_533
 306         write32 DBRFCNF2_A,     DBRFCNF2_D
 307         write32 DBRFEN_A,       DBRFEN_D
 308         write32 DBACEN_A,       DBACEN_D
 309         write32 DBACEN_A,       DBACEN_D
 310
 311         /* Dummy read */
 312         mov.l DBWAIT_A, r1
 313         synco
 314         mov.l @r1, r0
 315         synco
 316
 317         /* Dummy read */
 318         mov.l SDRAM_A, r1
 319         synco
 320         mov.l @r1, r0
 321         synco
 322
 323         /* need sleep 186A0 */
 324
 325         bra     finish_init_sh7734
 326         nop
 327
 328         .align 2
 329
 330 DBKIND_A:       .long   0xFE800020
 331 DBKIND_D:       .long   0x00000005
 332 DBCONF_A:       .long   0xFE800024
 333 DBCONF_D:       .long   0x0D020901
 334
 335 DBTR0_A:        .long   0xFE800040
 336 DBTR0_D_533:.long       0x00000004
 337 DBTR0_D_400:.long       0x00000003
 338 DBTR1_A:        .long   0xFE800044
 339 DBTR1_D_533:.long       0x00000003
 340 DBTR1_D_400:.long       0x00000002
 341 DBTR2_A:        .long   0xFE800048
 342 DBTR2_D:        .long   0x00000000
 343 DBTR3_A:        .long   0xFE800050
 344 DBTR3_D_533:.long       0x00000004
 345 DBTR3_D_400:.long       0x00000003
 346
 347 DBTR4_A:        .long   0xFE800054
 348 DBTR4_D_533:.long       0x00050004
 349 DBTR4_D_400:.long       0x00050003
 350
 351 DBTR5_A:        .long   0xFE800058
 352 DBTR5_D_533:.long       0x0000000F
 353 DBTR5_D_400:.long       0x0000000B
 354
 355 DBTR6_A:        .long   0xFE80005C
 356 DBTR6_D_533:.long       0x0000000B
 357 DBTR6_D_400:.long       0x00000008
 358
 359 DBTR7_A:        .long   0xFE800060
 360 DBTR7_D:        .long   0x00000002
 361
 362 DBTR8_A:        .long   0xFE800064
 363 DBTR8_D_533:.long       0x0000000D
 364 DBTR8_D_400:.long       0x0000000A
 365
 366 DBTR9_A:        .long   0xFE800068
 367 DBTR9_D:        .long   0x00000002
 368
 369 DBTR10_A:       .long   0xFE80006C
 370 DBTR10_D_533:.long      0x00000004
 371 DBTR10_D_400:.long      0x00000003
 372
 373 DBTR11_A:       .long   0xFE800070
 374 DBTR11_D:       .long   0x00000008
 375
 376 DBTR12_A:       .long   0xFE800074
 377 DBTR12_D_533:.long      0x00000009
 378 DBTR12_D_400:.long      0x00000008
 379
 380 DBTR13_A:       .long   0xFE800078
 381 DBTR13_D_533:.long      0x00000022
 382 DBTR13_D_400:.long      0x0000001A
 383
 384 DBTR14_A:       .long   0xFE80007C
 385 DBTR14_D:       .long   0x00070002
 386
 387 DBTR15_A:       .long   0xFE800080
 388 DBTR15_D:       .long   0x00000003
 389
 390 DBTR16_A:       .long   0xFE800084
 391 DBTR16_D_533:.long      0x120A1001
 392 DBTR16_D_400:.long      0x12091001
 393
 394 DBTR17_A:       .long   0xFE800088
 395 DBTR17_D_533:.long      0x00040000
 396 DBTR17_D_400:.long      0x00030000
 397
 398 DBTR18_A:       .long   0xFE80008C
 399 DBTR18_D_533:.long      0x02010200
 400 DBTR18_D_400:.long      0x02000207
 401
 402 DBBL_A: .long   0xFE8000B0
 403 DBBL_D: .long   0x00000000
 404
 405 DBRNK0_A:               .long   0xFE800100
 406 DBRNK0_D:               .long   0x00000001
 407
 408 DBCMD_A:                .long   0xFE800018
 409 DBCMD_D0_533:   .long   0x1100006B
 410 DBCMD_D0_400:   .long   0x11000050
 411 DBCMD_D1:               .long   0x0B000000
 412 DBCMD_D2:               .long   0x2A004000
 413 DBCMD_D3:               .long   0x2B006000
 414 DBCMD_D4:               .long   0x29002044
 415 DBCMD_D5_533:   .long   0x28000743
 416 DBCMD_D5_400:   .long   0x28000533
 417 DBCMD_D6:               .long   0x0B000000
 418 DBCMD_D7:               .long   0x0C000000
 419 DBCMD_D8:               .long   0x0C000000
 420 DBCMD_D9_533:   .long   0x28000643
 421 DBCMD_D9_400:   .long   0x28000433
 422 DBCMD_D10:              .long   0x000000C8
 423 DBCMD_D11:              .long   0x290023C4
 424 DBCMD_D12:              .long   0x29002004
 425
 426 DBRFCNF0_A:             .long   0xFE8000E0
 427 DBRFCNF0_D:             .long   0x000001FF
 428 DBRFCNF1_A:             .long   0xFE8000E4
 429 DBRFCNF1_D_533: .long   0x00000805
 430 DBRFCNF1_D_400: .long   0x00000618
 431
 432 DBRFCNF2_A:             .long   0xFE8000E8
 433 DBRFCNF2_D:             .long   0x00000000
 434
 435 DBRFEN_A:               .long   0xFE800014
 436 DBRFEN_D:               .long   0x00000001
 437
 438 DBACEN_A:               .long   0xFE800010
 439 DBACEN_D:               .long   0x00000001
 440
 441 DBWAIT_A:               .long   0xFE80001C
 442 SDRAM_A:                .long   0x0C000000
 443
 444 finish_init_sh7734:
 445         write32 CCR_A,  CCR_D
 446
 447         stc sr, r0
 448         mov.l  SR_MASK_D, r1
 449         and r1, r0
 450         ldc r0, sr
 451
 452         rts
 453         nop
 454
 455         .align  2
 456
 457 CCR_A:  .long   0xFF00001C
 458 CCR_D:  .long   0x0000090B
 459 SR_MASK_D:      .long   0xEFFFFF0F