3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
27 #define CRAM_BANK0_BASE 0x0
28 #define CRAM_DIDR 0x00100000
29 #define MICRON_MT45W8MW16BGX_CRAM_ID 0x1b431b43
30 #define MICRON_MT45W8MW16BGX_CRAM_ID2 0x13431343
31 #define MICRON_DIDR_VENDOR_ID 0x00030003 /* 00011b */
32 #define CRAM_DIDR_VENDOR_ID_MASK 0x001f001f /* DIDR[4:0] */
33 #define CRAM_DEVID_NOT_SUPPORTED 0x00000000
35 #define PSRAM_PASS 0x50415353 /* "PASS" */
36 #define PSRAM_FAIL 0x4641494C /* "FAIL" */
38 static u32 is_cram_inited(void);
39 static u32 is_cram(void);
40 static long int cram_init(u32);
41 static void cram_bcr_write(u32);
42 void udelay (unsigned long);
46 volatile unsigned long spr_reg;
49 * If CRAM not initialized or CRAM looks initialized because this
50 * is after a warm reboot then set SPRG7 to indicate CRAM needs
51 * initialization. Note that CRAM is initialized by the SPI and
54 spr_reg = (volatile unsigned long) mfspr(SPRG6);
55 if ((is_cram_inited() != 1) || (spr_reg != LOAK_SPL)) {
56 mtspr(SPRG7, LOAK_NONE); /* "NONE" */
61 * When running the NAND SPL, the normal EBC configuration is not
62 * done, so We need to enable EPLD access on EBC_CS_2 and the memory
66 /* Enable CPLD - Needed for PSRAM Access */
69 /* Init SDRAM by setting EBC Bank 3 for PSRAM */
70 mtebc(pb1ap, CFG_EBC_PB1AP);
71 mtebc(pb1cr, CFG_EBC_PB1CR);
73 mtebc(pb2ap, CFG_EBC_PB2AP);
74 mtebc(pb2cr, CFG_EBC_PB2CR);
76 /* pre-boot loader code: we are in OCM */
77 mtspr(SPRG6, LOAK_SPL); /* "SPL " */
78 mtspr(SPRG7, LOAK_OCM); /* "OCM " */
84 static void cram_bcr_write(u32 wr_val)
88 volatile u32 gpio_reg;
90 /* # Program CRAM write */
94 * set wr_val = wr_val << 2
96 gpio_reg = in32(GPIO1_OR);
97 out32(GPIO1_OR, gpio_reg | 0x00000400);
99 /* wr_val = 0x1c048; */
103 * # stop PLL clock before programming CRAM
104 * set EPLD0_MUX_CTL.OESPR3 = 1
112 * #shift 2 bit left before write
113 * set val = wr_val + 0x00200000
115 * read 0x00200000 val
118 tmp_reg = in32(0x00200000);
119 val = wr_val + 0x00200000;
120 /* val = 0x0021c048; */
123 val = in32(0x00200000);
125 debug("CRAM VAL: %x for CS1 ", val);
130 * #shift 2 bit left before write
131 * set val = wr_val + 0x02200000
133 * read 0x02200000 val
136 tmp_reg = in32(0x02200000);
137 val = wr_val + 0x02200000;
138 /* val = 0x0221c048; */
141 val = in32(0x02200000);
143 debug("CRAM VAL: %x for CS2 ", val);
146 * # Start PLL clock before programming CRAM
147 * set EPLD0_MUX_CTL.OESPR3 = 0
154 gpio_reg = in32(GPIO1_OR);
155 out32(GPIO1_OR, gpio_reg | 0x00000400);
158 * # read CRAM config BCR ( bit19:18 = 10b )
160 * # 1001_1001_0001_1111 ( 991f ) =>
161 * #10_0110_0100_0111_1100 => 2647c => 0022647c
162 * #0011_0010_0011_1110 (323e)
167 * set EPLD0_MUX_CTL.CRAMCR = 0x0
169 gpio_reg = in32(GPIO1_OR);
170 out32(GPIO1_OR, gpio_reg & 0xFFFFFBFF);
174 static u32 is_cram_inited()
176 volatile unsigned long spr_reg;
179 * If CRAM is initialized already, then don't reinitialize it again.
180 * In the case of NAND boot and SPI boot, CRAM will already be
181 * initialized by the pre-loader
183 spr_reg = (volatile unsigned long) mfspr(SPRG7);
184 if (spr_reg == LOAK_CRAM) {
192 * return 0 if not CRAM
193 * return 1 if CRAM and it's already inited by preloader
194 * else return cram_id (CRAM Device Identification Register)
196 static u32 is_cram(void)
198 u32 gpio_TCR, gpio_OSRL, gpio_OR, gpio_ISR1L;
199 volatile u32 gpio_reg;
200 volatile u32 cram_id = 0;
202 if (is_cram_inited() == 1) {
203 /* this is CRAM and it is already inited (by preloader) */
208 * set GPIO0_TCR.G8 = 1
209 * set GPIO0_OSRL.G8 = 0
210 * set GPIO0_OR.G8 = 0
212 gpio_reg = in32(GPIO0_TCR);
214 out32(GPIO0_TCR, gpio_reg | 0x00800000);
215 gpio_reg = in32(GPIO0_OSRL);
216 gpio_OSRL = gpio_reg;
217 out32(GPIO0_OSRL, gpio_reg & 0xffffbfff);
218 gpio_reg = in32(GPIO0_OR);
220 out32(GPIO0_OR, gpio_reg & 0xff7fffff);
223 * # CRAM Addreaa Valid
224 * set GPIO0_TCR.G10 = 1
225 * set GPIO0_OSRL.G10 = 0
226 * set GPIO0_OR.G10 = 0
228 gpio_reg = in32(GPIO0_TCR);
229 out32(GPIO0_TCR, gpio_reg | 0x00200000);
230 gpio_reg = in32(GPIO0_OSRL);
231 out32(GPIO0_OSRL, gpio_reg & 0xfffffbff);
232 gpio_reg = in32(GPIO0_OR);
233 out32(GPIO0_OR, gpio_reg & 0xffdfffff);
236 * # config input (EBC_WAIT)
237 * set GPIO0_ISR1L.G9 = 1
238 * set GPIO0_TCR.G9 = 0
240 gpio_reg = in32(GPIO0_ISR1L);
241 gpio_ISR1L = gpio_reg;
242 out32(GPIO0_ISR1L, gpio_reg | 0x00001000);
243 gpio_reg = in32(GPIO0_TCR);
244 out32(GPIO0_TCR, gpio_reg & 0xffbfffff);
247 * Enable CRE to read Registers
248 * set GPIO0_TCR.21 = 1
249 * set GPIO1_OR.21 = 1
251 gpio_reg = in32(GPIO1_TCR);
252 out32(GPIO1_TCR, gpio_reg | 0x00000400);
254 gpio_reg = in32(GPIO1_OR);
255 out32(GPIO1_OR, gpio_reg | 0x00000400);
260 /* Read Version ID */
261 cram_id = (volatile u32) in32(CRAM_BANK0_BASE+CRAM_DIDR);
264 asm volatile(" sync");
265 asm volatile(" eieio");
267 debug("Cram ID: %X ", cram_id);
270 case MICRON_MT45W8MW16BGX_CRAM_ID:
271 case MICRON_MT45W8MW16BGX_CRAM_ID2:
272 /* supported CRAM vendor/part */
274 case CRAM_DEVID_NOT_SUPPORTED:
276 /* check for DIDR Vendor ID of Micron */
277 if ((cram_id & CRAM_DIDR_VENDOR_ID_MASK) ==
278 MICRON_DIDR_VENDOR_ID)
280 /* supported CRAM vendor */
283 /* this is not CRAM or not supported CRAM vendor/part */
286 * reset the GPIO registers to the values that were
287 * there before this routine
289 out32(GPIO0_TCR, gpio_TCR);
290 out32(GPIO0_OSRL, gpio_OSRL);
291 out32(GPIO0_OR, gpio_OR);
292 out32(GPIO0_ISR1L, gpio_ISR1L);
300 static long int cram_init(u32 already_inited)
302 volatile u32 tmp_reg;
305 if (already_inited == 0) return 0;
308 * If CRAM is initialized already, then don't reinitialize it again.
309 * In the case of NAND boot and SPI boot, CRAM will already be
310 * initialized by the pre-loader
312 if (already_inited != 1)
316 * # - CRAMCRE @reg16 = 1; for CRAM to use
317 * # - CRAMCRE @reg16 = 0; for CRAM to program
319 * # enable CRAM SEL, move from setEPLD.cmd
320 * set EPLD0_MUX_CTL.OECRAM = 0
321 * set EPLD0_MUX_CTL.CRAMCR = 1
322 * set EPLD0_ETHRSTBOOT.SLCRAM = 0
328 * #1. EBC need to program READY, CLK, ADV for ASync mode
334 * set GPIO0_TCR.G8 = 1
335 * set GPIO0_OSRL.G8 = 0
336 * set GPIO0_OR.G8 = 0
338 tmp_reg = in32(GPIO0_TCR);
339 out32(GPIO0_TCR, tmp_reg | 0x00800000);
340 tmp_reg = in32(GPIO0_OSRL);
341 out32(GPIO0_OSRL, tmp_reg & 0xffffbfff);
342 tmp_reg = in32(GPIO0_OR);
343 out32(GPIO0_OR, tmp_reg & 0xff7fffff);
346 * # CRAM Addreaa Valid
347 * set GPIO0_TCR.G10 = 1
348 * set GPIO0_OSRL.G10 = 0
349 * set GPIO0_OR.G10 = 0
351 tmp_reg = in32(GPIO0_TCR);
352 out32(GPIO0_TCR, tmp_reg | 0x00200000);
353 tmp_reg = in32(GPIO0_OSRL);
354 out32(GPIO0_OSRL, tmp_reg & 0xfffffbff);
355 tmp_reg = in32(GPIO0_OR);
356 out32(GPIO0_OR, tmp_reg & 0xffdfffff);
359 * # config input (EBC_WAIT)
360 * set GPIO0_ISR1L.G9 = 1
361 * set GPIO0_TCR.G9 = 0
363 tmp_reg = in32(GPIO0_ISR1L);
364 out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
365 tmp_reg = in32(GPIO0_TCR);
366 out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
369 * # config CS4 from GPIO
370 * set GPIO0_TCR.G0 = 1
371 * set GPIO0_OSRL.G0 = 1
373 tmp_reg = in32(GPIO0_TCR);
374 out32(GPIO0_TCR, tmp_reg | 0x80000000);
375 tmp_reg = in32(GPIO0_OSRL);
376 out32(GPIO0_OSRL, tmp_reg | 0x40000000);
379 * #2. EBC in Async mode
380 * # set EBC0_PB1AP = 0x078f0ec0
381 * set EBC0_PB1AP = 0x078f1ec0
382 * set EBC0_PB2AP = 0x078f1ec0
384 mtebc(pb1ap, 0x078F1EC0);
385 mtebc(pb2ap, 0x078F1EC0);
388 * #set EBC0_PB1CR = 0x000bc000
389 * #enable CS2 for CRAM
390 * set EBC0_PB2CR = 0x020bc000
392 mtebc(pb1cr, 0x000BC000);
393 mtebc(pb2cr, 0x020BC000);
396 * #3. set CRAM in Sync mode
397 * #exec cm_bcr_write.cmd { 0x701f }
398 * #3. set CRAM in Sync mode (full drv strength)
399 * exec cm_bcr_write.cmd { 0x701F }
401 cram_wr_val = 0x7012; /* CRAM burst setting */
402 cram_bcr_write(cram_wr_val);
405 * #4. EBC in Sync mode
406 * #set EBC0_PB1AP = 0x9f800fc0
407 * #set EBC0_PB1AP = 0x900001c0
408 * set EBC0_PB2AP = 0x9C0201c0
409 * set EBC0_PB2AP = 0x9C0201c0
411 mtebc(pb1ap, 0x9C0201C0);
412 mtebc(pb2ap, 0x9C0201C0);
415 * #5. EBC need to program READY, CLK, ADV for Sync mode
417 * set GPIO0_TCR.G8 = 1
418 * set GPIO0_OSRL.G8 = 1
419 * set GPIO0_TCR.G10 = 1
420 * set GPIO0_OSRL.G10 = 1
422 tmp_reg = in32(GPIO0_TCR);
423 out32(GPIO0_TCR, tmp_reg | 0x00800000);
424 tmp_reg = in32(GPIO0_OSRL);
425 out32(GPIO0_OSRL, tmp_reg | 0x00004000);
426 tmp_reg = in32(GPIO0_TCR);
427 out32(GPIO0_TCR, tmp_reg | 0x00200000);
428 tmp_reg = in32(GPIO0_OSRL);
429 out32(GPIO0_OSRL, tmp_reg | 0x00000400);
433 * set GPIO0_ISR1L.G9 = 1
434 * set GPIO0_TCR.G9 = 0
436 tmp_reg = in32(GPIO0_ISR1L);
437 out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
438 tmp_reg = in32(GPIO0_TCR);
439 out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
442 * # config EBC to use RDY
443 * set SDR0_ULTRA0.EBCREN = 1
445 mfsdr(sdrultra0, tmp_reg);
446 mtsdr(sdrultra0, tmp_reg | 0x04000000);
449 * set EPLD0_MUX_CTL.OESPR3 = 0
453 mtspr(SPRG7, LOAK_CRAM); /* "CRAM" */
454 } /* if (already_inited != 1) */
456 return (64 * 1024 * 1024);
460 * return 0 if not PSRAM
461 * return 1 if is PSRAM
463 static int is_psram(u32 addr)
465 u32 test_pattern = 0xdeadbeef;
466 volatile u32 readback;
468 if (addr == CFG_SDRAM_BASE) {
469 /* This is to temp enable OE for PSRAM */
470 out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
474 out32(addr, test_pattern);
475 asm volatile(" sync");
476 asm volatile(" eieio");
478 readback = (volatile u32) in32(addr);
479 asm volatile(" sync");
480 asm volatile(" eieio");
481 if (readback == test_pattern) {
488 static long int psram_init(void)
494 /* This is to temp enable OE for PSRAM */
495 out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
499 * PSRAM bank 1: read then write to address 0x00000000
501 for (i = 0; i < 100; i++) {
502 if (is_psram(CFG_SDRAM_BASE + (i*256)) == 1) {
503 readback = PSRAM_PASS;
505 readback = PSRAM_FAIL;
509 if (readback == PSRAM_PASS) {
510 debug("psram_init(bank0): pass\n");
511 psramsize = (16 * 1024 * 1024);
513 debug("psram_init(bank0): fail\n");
519 * PSRAM bank 1: read then write to address 0x01000000
521 for (i = 0; i < 100; i++) {
522 if (is_psram((1 << 24) + (i*256)) == 1) {
523 readback = PSRAM_PASS;
525 readback = PSRAM_FAIL;
529 if (readback == PSRAM_PASS) {
530 debug("psram_init(bank1): pass\n");
531 psramsize = psramsize + (16 * 1024 * 1024);
535 mtspr(SPRG7, LOAK_PSRAM); /* "PSRA" - PSRAM */
540 long int initdram(int board_type)
545 /* Determine Attached Memory Expansion Card*/
546 cram_inited = is_cram();
547 if (cram_inited != 0) { /* CRAM */
548 debug("CRAM Expansion Card attached\n");
549 sram_size = cram_init(cram_inited);
550 } else if (is_psram(CFG_SDRAM_BASE+4) == 1) { /* PSRAM */
551 debug("PSRAM Expansion Card attached\n");
552 sram_size = psram_init();
553 } else { /* no SRAM */
554 debug("No Memory Card Attached!!\n");