3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <spd_sdram.h>
30 void ext_bus_cntlr_init(void);
31 void configure_ppc440ep_pins(void);
32 int is_nand_selected(void);
34 unsigned char cfg_simulate_spd_eeprom[128];
36 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
38 { /* GPIO Alternate1 Alternate2 Alternate3 */
41 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
42 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
43 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
44 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
45 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
46 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
47 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
48 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
49 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
50 { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
51 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
52 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
53 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
54 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
55 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
56 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
57 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
58 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
59 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
60 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
61 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
62 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
63 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
64 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
65 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
66 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
67 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
68 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
69 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
70 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
71 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
72 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
76 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
77 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
78 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
79 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
80 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
81 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
82 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
83 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
84 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
85 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
86 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
87 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
88 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
89 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
90 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
91 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
92 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
93 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
94 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
95 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
96 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
97 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
98 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
99 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
100 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
101 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
102 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
103 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
104 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
105 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
106 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
107 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
112 /*----------------------------------------------------------------------------+
113 | EBC Devices Characteristics
114 | Peripheral Bank Access Parameters - EBC0_BnAP
115 | Peripheral Bank Configuration Register - EBC0_BnCR
116 +----------------------------------------------------------------------------*/
118 #define EBC0_BNAP_SMALL_FLASH \
119 EBC0_BNAP_BME_DISABLED | \
120 EBC0_BNAP_TWT_ENCODE(6) | \
121 EBC0_BNAP_CSN_ENCODE(0) | \
122 EBC0_BNAP_OEN_ENCODE(1) | \
123 EBC0_BNAP_WBN_ENCODE(1) | \
124 EBC0_BNAP_WBF_ENCODE(3) | \
125 EBC0_BNAP_TH_ENCODE(1) | \
126 EBC0_BNAP_RE_ENABLED | \
127 EBC0_BNAP_SOR_DELAYED | \
128 EBC0_BNAP_BEM_WRITEONLY | \
129 EBC0_BNAP_PEN_DISABLED
131 #define EBC0_BNCR_SMALL_FLASH_CS0 \
132 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
137 #define EBC0_BNCR_SMALL_FLASH_CS4 \
138 EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
143 /* Large Flash or SRAM */
144 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
145 EBC0_BNAP_BME_DISABLED | \
146 EBC0_BNAP_TWT_ENCODE(8) | \
147 EBC0_BNAP_CSN_ENCODE(0) | \
148 EBC0_BNAP_OEN_ENCODE(1) | \
149 EBC0_BNAP_WBN_ENCODE(1) | \
150 EBC0_BNAP_WBF_ENCODE(1) | \
151 EBC0_BNAP_TH_ENCODE(2) | \
152 EBC0_BNAP_SOR_DELAYED | \
154 EBC0_BNAP_PEN_DISABLED
156 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
157 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
163 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
164 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
170 #define EBC0_BNAP_NVRAM_FPGA \
171 EBC0_BNAP_BME_DISABLED | \
172 EBC0_BNAP_TWT_ENCODE(9) | \
173 EBC0_BNAP_CSN_ENCODE(0) | \
174 EBC0_BNAP_OEN_ENCODE(1) | \
175 EBC0_BNAP_WBN_ENCODE(1) | \
176 EBC0_BNAP_WBF_ENCODE(0) | \
177 EBC0_BNAP_TH_ENCODE(2) | \
178 EBC0_BNAP_RE_ENABLED | \
179 EBC0_BNAP_SOR_DELAYED | \
180 EBC0_BNAP_BEM_WRITEONLY | \
181 EBC0_BNAP_PEN_DISABLED
183 #define EBC0_BNCR_NVRAM_FPGA_CS5 \
184 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
190 #define EBC0_BNAP_NAND_FLASH \
191 EBC0_BNAP_BME_DISABLED | \
192 EBC0_BNAP_TWT_ENCODE(3) | \
193 EBC0_BNAP_CSN_ENCODE(0) | \
194 EBC0_BNAP_OEN_ENCODE(0) | \
195 EBC0_BNAP_WBN_ENCODE(0) | \
196 EBC0_BNAP_WBF_ENCODE(0) | \
197 EBC0_BNAP_TH_ENCODE(1) | \
198 EBC0_BNAP_RE_ENABLED | \
199 EBC0_BNAP_SOR_NOT_DELAYED | \
201 EBC0_BNAP_PEN_DISABLED
204 #define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
207 #define EBC0_BNCR_NAND_FLASH_CS1 \
208 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
213 #define EBC0_BNCR_NAND_FLASH_CS2 \
214 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
220 #define EBC0_BNCR_NAND_FLASH_CS3 \
221 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
226 int board_early_init_f(void)
228 ext_bus_cntlr_init();
230 /*--------------------------------------------------------------------
231 * Setup the interrupt controller polarities, triggers, etc.
232 *-------------------------------------------------------------------*/
233 mtdcr(uic0sr, 0xffffffff); /* clear all */
234 mtdcr(uic0er, 0x00000000); /* disable all */
235 mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
236 mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
237 mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
238 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
239 mtdcr(uic0sr, 0xffffffff); /* clear all */
241 mtdcr(uic1sr, 0xffffffff); /* clear all */
242 mtdcr(uic1er, 0x00000000); /* disable all */
243 mtdcr(uic1cr, 0x00000000); /* all non-critical */
244 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
245 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
246 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
247 mtdcr(uic1sr, 0xffffffff); /* clear all */
249 /*--------------------------------------------------------------------
250 * Setup the GPIO pins
251 *-------------------------------------------------------------------*/
252 out32(GPIO0_OSRL, 0x00000400);
253 out32(GPIO0_OSRH, 0x00000000);
254 out32(GPIO0_TSRL, 0x00000400);
255 out32(GPIO0_TSRH, 0x00000000);
256 out32(GPIO0_ISR1L, 0x00000000);
257 out32(GPIO0_ISR1H, 0x00000000);
258 out32(GPIO0_ISR2L, 0x00000000);
259 out32(GPIO0_ISR2H, 0x00000000);
260 out32(GPIO0_ISR3L, 0x00000000);
261 out32(GPIO0_ISR3H, 0x00000000);
263 out32(GPIO1_OSRL, 0x0C380000);
264 out32(GPIO1_OSRH, 0x00000000);
265 out32(GPIO1_TSRL, 0x0C380000);
266 out32(GPIO1_TSRH, 0x00000000);
267 out32(GPIO1_ISR1L, 0x0FC30000);
268 out32(GPIO1_ISR1H, 0x00000000);
269 out32(GPIO1_ISR2L, 0x0C010000);
270 out32(GPIO1_ISR2H, 0x00000000);
271 out32(GPIO1_ISR3L, 0x01400000);
272 out32(GPIO1_ISR3H, 0x00000000);
274 configure_ppc440ep_pins();
279 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
280 #include <linux/mtd/nand_legacy.h>
281 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
283 /*----------------------------------------------------------------------------+
286 | This routine will abort previous cmd
287 +----------------------------------------------------------------------------*/
288 int nand_reset(ulong addr)
292 out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
293 out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
295 while ((stat != 0xc0) && (wait != 0xffff)) {
296 stat = in8(addr + NAND_DATA_REG);
303 printf("NAND Reset timeout.\n");
308 void board_nand_set_device(int cs, ulong addr)
310 /* Set NandFlash Core Configuration Register */
311 out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
318 * K9F1208U0A : 4 addr cyc, 1 col + 3 Row
319 * Set NDF1CR - Enable External CS1 in NAND FLASH controller
321 out32(addr + NAND_CR1_REG, 0x80002222);
328 * K9K2G0B : 5 addr cyc, 2 col + 3 Row
329 * Set NDF2CR : Enable External CS2 in NAND FLASH controller
331 out32(addr + NAND_CR2_REG, 0xC0007777);
335 /* Perform Reset Command */
336 if (nand_reset(addr) != 0)
342 board_nand_set_device(1, CFG_NAND_ADDR);
344 nand_probe(CFG_NAND_ADDR);
345 if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
346 print_size(nand_dev_desc[0].totlen, "\n");
349 #if 0 /* NAND1 not supported yet */
350 board_nand_set_device(2, CFG_NAND2_ADDR);
352 nand_probe(CFG_NAND2_ADDR);
353 if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
354 print_size(nand_dev_desc[0].totlen, "\n");
358 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
362 char *s = getenv("serial#");
364 printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
374 /*************************************************************************
376 * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
378 * Fixed memory is composed of :
379 * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
380 * 13 row add bits, 10 column add bits (but 12 row used only).
381 * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
382 * 12 row add bits, 10 column add bits.
383 * Prepare a subset (only the used ones) of SPD data
385 * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
386 * the corresponding bank is divided by 2 due to number of Row addresses
387 * 12 in the ECC module
389 * Assumes: 64 MB, ECC, non-registered
392 ************************************************************************/
393 static void init_spd_array(void)
395 cfg_simulate_spd_eeprom[8] = 0x04; /* 2.5 Volt */
396 cfg_simulate_spd_eeprom[2] = 0x07; /* DDR ram */
398 #ifdef CONFIG_DDR_ECC
399 cfg_simulate_spd_eeprom[11] = 0x02; /* ECC ON : 02 OFF : 00 */
400 cfg_simulate_spd_eeprom[31] = 0x08; /* bankSizeID: 32MB */
401 cfg_simulate_spd_eeprom[3] = 0x0C; /* num Row Addr: 12 */
403 cfg_simulate_spd_eeprom[11] = 0x00; /* ECC ON : 02 OFF : 00 */
404 cfg_simulate_spd_eeprom[31] = 0x10; /* bankSizeID: 64MB */
405 cfg_simulate_spd_eeprom[3] = 0x0D; /* num Row Addr: 13 */
408 cfg_simulate_spd_eeprom[4] = 0x09; /* numColAddr: 9 */
409 cfg_simulate_spd_eeprom[5] = 0x01; /* numBanks: 1 */
410 cfg_simulate_spd_eeprom[0] = 0x80; /* number of SPD bytes used: 128 */
411 cfg_simulate_spd_eeprom[1] = 0x08; /* total number bytes in SPD device = 256 */
412 cfg_simulate_spd_eeprom[21] = 0x00; /* not registered: 0 registered : 0x02*/
413 cfg_simulate_spd_eeprom[6] = 0x20; /* Module data width: 32 bits */
414 cfg_simulate_spd_eeprom[7] = 0x00; /* Module data width continued: +0 */
415 cfg_simulate_spd_eeprom[15] = 0x01; /* wcsbc = 1 */
416 cfg_simulate_spd_eeprom[27] = 0x50; /* tRpNs = 20 ns */
417 cfg_simulate_spd_eeprom[29] = 0x50; /* tRcdNs = 20 ns */
419 cfg_simulate_spd_eeprom[30] = 45; /* tRasNs */
421 cfg_simulate_spd_eeprom[18] = 0x0C; /* casBit (2,2.5) */
423 cfg_simulate_spd_eeprom[9] = 0x75; /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
424 cfg_simulate_spd_eeprom[23] = 0xA0; /* SDRAM Cycle Time (cas latency 2) = 10 ns */
425 cfg_simulate_spd_eeprom[25] = 0x00; /* SDRAM Cycle Time (cas latency 1.5) = N.A */
426 cfg_simulate_spd_eeprom[12] = 0x82; /* refresh Rate Type: Normal (15.625us) + Self refresh */
429 long int initdram (int board_type)
434 * First write simulated values in eeprom array for onboard bank 0
438 dram_size = spd_sdram (0);
443 #if defined(CFG_DRAM_TEST)
446 unsigned long *mem = (unsigned long *)0;
447 const unsigned long kend = (1024 / sizeof(unsigned long));
452 for (k = 0; k < CFG_KBYTES_SDRAM;
453 ++k, mem += (1024 / sizeof(unsigned long))) {
454 if ((k & 1023) == 0) {
455 printf("%3d MB\r", k / 1024);
458 memset(mem, 0xaaaaaaaa, 1024);
459 for (n = 0; n < kend; ++n) {
460 if (mem[n] != 0xaaaaaaaa) {
461 printf("SDRAM test fails at: %08x\n",
467 memset(mem, 0x55555555, 1024);
468 for (n = 0; n < kend; ++n) {
469 if (mem[n] != 0x55555555) {
470 printf("SDRAM test fails at: %08x\n",
476 printf("SDRAM test passes\n");
481 /*************************************************************************
484 * This routine is called just prior to registering the hose and gives
485 * the board the opportunity to check things. Returning a value of zero
486 * indicates that things are bad & PCI initialization should be aborted.
488 * Different boards may wish to customize the pci controller structure
489 * (add regions, override default access routines, etc) or perform
490 * certain pre-initialization actions.
492 ************************************************************************/
493 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
494 int pci_pre_init(struct pci_controller *hose)
498 /*-------------------------------------------------------------------------+
499 | Set priority for all PLB3 devices to 0.
500 | Set PLB3 arbiter to fair mode.
501 +-------------------------------------------------------------------------*/
502 mfsdr(sdr_amp1, addr);
503 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
504 addr = mfdcr(plb3_acr);
505 mtdcr(plb3_acr, addr | 0x80000000);
507 /*-------------------------------------------------------------------------+
508 | Set priority for all PLB4 devices to 0.
509 +-------------------------------------------------------------------------*/
510 mfsdr(sdr_amp0, addr);
511 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
512 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
513 mtdcr(plb4_acr, addr);
515 /*-------------------------------------------------------------------------+
516 | Set Nebula PLB4 arbiter to fair mode.
517 +-------------------------------------------------------------------------*/
519 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
520 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
521 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
522 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
523 mtdcr(plb0_acr, addr);
526 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
527 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
528 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
529 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
530 mtdcr(plb1_acr, addr);
534 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
536 /*************************************************************************
539 * The bootstrap configuration provides default settings for the pci
540 * inbound map (PIM). But the bootstrap config choices are limited and
541 * may not be sufficient for a given board.
543 ************************************************************************/
544 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
545 void pci_target_init(struct pci_controller *hose)
547 /*--------------------------------------------------------------------------+
548 * Set up Direct MMIO registers
549 *--------------------------------------------------------------------------*/
550 /*--------------------------------------------------------------------------+
551 | PowerPC440 EP PCI Master configuration.
552 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
553 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
554 | Use byte reversed out routines to handle endianess.
555 | Make this region non-prefetchable.
556 +--------------------------------------------------------------------------*/
557 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
558 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
559 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
560 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
561 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
563 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
564 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
565 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
566 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
567 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
569 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
570 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
571 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
572 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
574 /*--------------------------------------------------------------------------+
575 * Set up Configuration registers
576 *--------------------------------------------------------------------------*/
578 /* Program the board's subsystem id/vendor id */
579 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
580 CFG_PCI_SUBSYS_VENDORID);
581 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
583 /* Configure command register as bus master */
584 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
586 /* 240nS PCI clock */
587 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
589 /* No error reporting */
590 pci_write_config_word(0, PCI_ERREN, 0);
592 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
595 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
597 /*************************************************************************
600 ************************************************************************/
601 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
602 void pci_master_init(struct pci_controller *hose)
604 unsigned short temp_short;
606 /*--------------------------------------------------------------------------+
607 | Write the PowerPC440 EP PCI Configuration regs.
608 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
609 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
610 +--------------------------------------------------------------------------*/
611 pci_read_config_word(0, PCI_COMMAND, &temp_short);
612 pci_write_config_word(0, PCI_COMMAND,
613 temp_short | PCI_COMMAND_MASTER |
616 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
618 /*************************************************************************
621 * This routine is called to determine if a pci scan should be
622 * performed. With various hardware environments (especially cPCI and
623 * PPMC) it's insufficient to depend on the state of the arbiter enable
624 * bit in the strap register, or generic host/adapter assumptions.
626 * Rather than hard-code a bad assumption in the general 440 code, the
627 * 440 pci code requires the board to decide at runtime.
629 * Return 0 for adapter mode, non-zero for host (monarch) mode.
632 ************************************************************************/
633 #if defined(CONFIG_PCI)
634 int is_pci_host(struct pci_controller *hose)
636 /* Bamboo is always configured as host. */
639 #endif /* defined(CONFIG_PCI) */
641 /*----------------------------------------------------------------------------+
642 | is_powerpc440ep_pass1.
643 +----------------------------------------------------------------------------*/
644 int is_powerpc440ep_pass1(void)
650 if (pvr == PVR_POWERPC_440EP_PASS1)
652 else if (pvr == PVR_POWERPC_440EP_PASS2)
655 printf("brdutil error 3\n");
663 /*----------------------------------------------------------------------------+
665 +----------------------------------------------------------------------------*/
666 int is_nand_selected(void)
668 #ifdef CONFIG_BAMBOO_NAND
675 /*----------------------------------------------------------------------------+
676 | config_on_ebc_cs4_is_small_flash => from EPLD
677 +----------------------------------------------------------------------------*/
678 unsigned char config_on_ebc_cs4_is_small_flash(void)
680 /* Not implemented yet => returns constant value */
684 /*----------------------------------------------------------------------------+
685 | Ext_bus_cntlr_init.
686 | Initialize the external bus controller
687 +----------------------------------------------------------------------------*/
688 void ext_bus_cntlr_init(void)
690 unsigned long sdr0_pstrp0, sdr0_sdstp1;
691 unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
692 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
693 unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
694 unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
695 unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
696 unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
697 unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
700 /*-------------------------------------------------------------------------+
702 | PART 1 : Initialize EBC Bank 5
703 | ==============================
704 | Bank5 is always associated to the NVRAM/EPLD.
705 | It has to be initialized prior to other banks settings computation since
706 | some board registers values may be needed
708 +-------------------------------------------------------------------------*/
710 mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
711 mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
713 /*-------------------------------------------------------------------------+
715 | PART 2 : Determine which boot device was selected
716 | =========================================
718 | Read Pin Strap Register in PPC440EP
719 | In case of boot from IIC, read Serial Device Strap Register1
721 | Result can either be :
722 | - Boot from EBC 8bits => SMALL FLASH
723 | - Boot from EBC 16bits => Large Flash or SRAM
724 | - Boot from NAND Flash
727 +-------------------------------------------------------------------------*/
728 /* Read Pin Strap Register in PPC440EP */
729 mfsdr(sdr_pstrp0, sdr0_pstrp0);
730 bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
732 /*-------------------------------------------------------------------------+
734 +-------------------------------------------------------------------------*/
735 if (is_powerpc440ep_pass1() == TRUE) {
736 switch(bootstrap_settings) {
737 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
738 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
739 /* Boot from Small Flash */
740 computed_boot_device = BOOT_FROM_SMALL_FLASH;
742 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
743 /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
745 computed_boot_device = BOOT_FROM_PCI;
748 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
749 /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
750 /* Boot from Nand Flash */
751 computed_boot_device = BOOT_FROM_NAND_FLASH0;
754 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
755 /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
756 /* Boot from Small Flash */
757 computed_boot_device = BOOT_FROM_SMALL_FLASH;
760 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
761 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
762 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
763 /* Read Serial Device Strap Register1 in PPC440EP */
764 mfsdr(sdr_sdstp1, sdr0_sdstp1);
765 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
766 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
768 switch(boot_selection) {
769 case SDR0_SDSTP1_BOOT_SEL_EBC:
770 switch(ebc_boot_size) {
771 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
772 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
774 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
775 computed_boot_device = BOOT_FROM_SMALL_FLASH;
780 case SDR0_SDSTP1_BOOT_SEL_PCI:
781 computed_boot_device = BOOT_FROM_PCI;
784 case SDR0_SDSTP1_BOOT_SEL_NDFC:
785 computed_boot_device = BOOT_FROM_NAND_FLASH0;
792 /*-------------------------------------------------------------------------+
794 +-------------------------------------------------------------------------*/
796 switch(bootstrap_settings) {
797 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
798 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
799 /* Boot from Small Flash */
800 computed_boot_device = BOOT_FROM_SMALL_FLASH;
802 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
803 /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
805 computed_boot_device = BOOT_FROM_PCI;
808 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
809 /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
810 /* Boot from Nand Flash */
811 computed_boot_device = BOOT_FROM_NAND_FLASH0;
814 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
815 /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
816 /* Boot from Large Flash or SRAM */
817 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
820 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
821 /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
822 /* Boot from Large Flash or SRAM */
823 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
826 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
827 /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
829 computed_boot_device = BOOT_FROM_PCI;
832 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
833 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
834 /* Default Strap Settings 5-7 */
835 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
836 /* Read Serial Device Strap Register1 in PPC440EP */
837 mfsdr(sdr_sdstp1, sdr0_sdstp1);
838 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
839 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
841 switch(boot_selection) {
842 case SDR0_SDSTP1_BOOT_SEL_EBC:
843 switch(ebc_boot_size) {
844 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
845 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
847 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
848 computed_boot_device = BOOT_FROM_SMALL_FLASH;
853 case SDR0_SDSTP1_BOOT_SEL_PCI:
854 computed_boot_device = BOOT_FROM_PCI;
857 case SDR0_SDSTP1_BOOT_SEL_NDFC:
858 computed_boot_device = BOOT_FROM_NAND_FLASH0;
865 /*-------------------------------------------------------------------------+
867 | PART 3 : Compute EBC settings depending on selected boot device
868 | ====== ======================================================
870 | Resulting EBC init will be among following configurations :
872 | - Boot from EBC 8bits => boot from SMALL FLASH selected
873 | EBC-CS0 = Small Flash
874 | EBC-CS1,2,3 = NAND Flash or
875 | Exp.Slot depending on Soft Config
876 | EBC-CS4 = SRAM/Large Flash or
877 | Large Flash/SRAM depending on jumpers
878 | EBC-CS5 = NVRAM / EPLD
880 | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
881 | EBC-CS0 = SRAM/Large Flash or
882 | Large Flash/SRAM depending on jumpers
883 | EBC-CS1,2,3 = NAND Flash or
884 | Exp.Slot depending on Software Configuration
885 | EBC-CS4 = Small Flash
886 | EBC-CS5 = NVRAM / EPLD
888 | - Boot from NAND Flash
889 | EBC-CS0 = NAND Flash0
890 | EBC-CS1,2,3 = NAND Flash1
891 | EBC-CS4 = SRAM/Large Flash or
892 | Large Flash/SRAM depending on jumpers
893 | EBC-CS5 = NVRAM / EPLD
897 | EBC-CS1,2,3 = NAND Flash or
898 | Exp.Slot depending on Software Configuration
899 | EBC-CS4 = SRAM/Large Flash or
900 | Large Flash/SRAM or
901 | Small Flash depending on jumpers
902 | EBC-CS5 = NVRAM / EPLD
904 +-------------------------------------------------------------------------*/
906 switch(computed_boot_device) {
907 /*------------------------------------------------------------------------- */
908 case BOOT_FROM_SMALL_FLASH:
909 /*------------------------------------------------------------------------- */
910 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
911 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
912 if ((is_nand_selected()) == TRUE) {
914 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
915 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
916 ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
917 ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
918 ebc0_cs3_bnap_value = 0;
919 ebc0_cs3_bncr_value = 0;
922 ebc0_cs1_bnap_value = 0;
923 ebc0_cs1_bncr_value = 0;
924 ebc0_cs2_bnap_value = 0;
925 ebc0_cs2_bncr_value = 0;
926 ebc0_cs3_bnap_value = 0;
927 ebc0_cs3_bncr_value = 0;
929 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
930 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
934 /*------------------------------------------------------------------------- */
935 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
936 /*------------------------------------------------------------------------- */
937 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
938 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
939 if ((is_nand_selected()) == TRUE) {
941 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
942 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
943 ebc0_cs2_bnap_value = 0;
944 ebc0_cs2_bncr_value = 0;
945 ebc0_cs3_bnap_value = 0;
946 ebc0_cs3_bncr_value = 0;
949 ebc0_cs1_bnap_value = 0;
950 ebc0_cs1_bncr_value = 0;
951 ebc0_cs2_bnap_value = 0;
952 ebc0_cs2_bncr_value = 0;
953 ebc0_cs3_bnap_value = 0;
954 ebc0_cs3_bncr_value = 0;
956 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
957 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
961 /*------------------------------------------------------------------------- */
962 case BOOT_FROM_NAND_FLASH0:
963 /*------------------------------------------------------------------------- */
964 ebc0_cs0_bnap_value = 0;
965 ebc0_cs0_bncr_value = 0;
967 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
968 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
969 ebc0_cs2_bnap_value = 0;
970 ebc0_cs2_bncr_value = 0;
971 ebc0_cs3_bnap_value = 0;
972 ebc0_cs3_bncr_value = 0;
974 /* Large Flash or SRAM */
975 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
976 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
980 /*------------------------------------------------------------------------- */
982 /*------------------------------------------------------------------------- */
983 ebc0_cs0_bnap_value = 0;
984 ebc0_cs0_bncr_value = 0;
986 if ((is_nand_selected()) == TRUE) {
988 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
989 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
990 ebc0_cs2_bnap_value = 0;
991 ebc0_cs2_bncr_value = 0;
992 ebc0_cs3_bnap_value = 0;
993 ebc0_cs3_bncr_value = 0;
996 ebc0_cs1_bnap_value = 0;
997 ebc0_cs1_bncr_value = 0;
998 ebc0_cs2_bnap_value = 0;
999 ebc0_cs2_bncr_value = 0;
1000 ebc0_cs3_bnap_value = 0;
1001 ebc0_cs3_bncr_value = 0;
1004 if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
1006 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
1007 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
1009 /* Large Flash or SRAM */
1010 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
1011 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
1016 /*------------------------------------------------------------------------- */
1017 case BOOT_DEVICE_UNKNOWN:
1018 /*------------------------------------------------------------------------- */
1025 /*-------------------------------------------------------------------------+
1026 | Initialize EBC CONFIG
1027 +-------------------------------------------------------------------------*/
1028 mtdcr(ebccfga, xbcfg);
1029 mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
1030 EBC0_CFG_PTD_ENABLED |
1031 EBC0_CFG_RTC_2048PERCLK |
1034 EBC0_CFG_CSTC_DRIVEN |
1035 EBC0_CFG_BPF_ONEDW |
1037 EBC0_CFG_PME_DISABLED |
1038 EBC0_CFG_PMT_ENCODE(0) );
1040 /*-------------------------------------------------------------------------+
1041 | Initialize EBC Bank 0-4
1042 +-------------------------------------------------------------------------*/
1044 mtebc(pb0ap, ebc0_cs0_bnap_value);
1045 mtebc(pb0cr, ebc0_cs0_bncr_value);
1047 mtebc(pb1ap, ebc0_cs1_bnap_value);
1048 mtebc(pb1cr, ebc0_cs1_bncr_value);
1050 mtebc(pb2ap, ebc0_cs2_bnap_value);
1051 mtebc(pb2cr, ebc0_cs2_bncr_value);
1053 mtebc(pb3ap, ebc0_cs3_bnap_value);
1054 mtebc(pb3cr, ebc0_cs3_bncr_value);
1056 mtebc(pb4ap, ebc0_cs4_bnap_value);
1057 mtebc(pb4cr, ebc0_cs4_bncr_value);
1063 /*----------------------------------------------------------------------------+
1064 | get_uart_configuration.
1065 +----------------------------------------------------------------------------*/
1066 uart_config_nb_t get_uart_configuration(void)
1071 /*----------------------------------------------------------------------------+
1072 | set_phy_configuration_through_fpga => to EPLD
1073 +----------------------------------------------------------------------------*/
1074 void set_phy_configuration_through_fpga(zmii_config_t config)
1077 unsigned long fpga_selection_reg;
1079 fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
1083 case ZMII_CONFIGURATION_IS_MII:
1084 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
1086 case ZMII_CONFIGURATION_IS_RMII:
1087 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
1089 case ZMII_CONFIGURATION_IS_SMII:
1090 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
1092 case ZMII_CONFIGURATION_UNKNOWN:
1096 out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
1100 /*----------------------------------------------------------------------------+
1101 | scp_selection_in_fpga.
1102 +----------------------------------------------------------------------------*/
1103 void scp_selection_in_fpga(void)
1105 unsigned long fpga_selection_2_reg;
1107 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1108 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
1109 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1112 /*----------------------------------------------------------------------------+
1113 | iic1_selection_in_fpga.
1114 +----------------------------------------------------------------------------*/
1115 void iic1_selection_in_fpga(void)
1117 unsigned long fpga_selection_2_reg;
1119 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1120 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
1121 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1124 /*----------------------------------------------------------------------------+
1125 | dma_a_b_selection_in_fpga.
1126 +----------------------------------------------------------------------------*/
1127 void dma_a_b_selection_in_fpga(void)
1129 unsigned long fpga_selection_2_reg;
1131 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
1132 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1135 /*----------------------------------------------------------------------------+
1136 | dma_a_b_unselect_in_fpga.
1137 +----------------------------------------------------------------------------*/
1138 void dma_a_b_unselect_in_fpga(void)
1140 unsigned long fpga_selection_2_reg;
1142 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
1143 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1146 /*----------------------------------------------------------------------------+
1147 | dma_c_d_selection_in_fpga.
1148 +----------------------------------------------------------------------------*/
1149 void dma_c_d_selection_in_fpga(void)
1151 unsigned long fpga_selection_2_reg;
1153 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
1154 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1157 /*----------------------------------------------------------------------------+
1158 | dma_c_d_unselect_in_fpga.
1159 +----------------------------------------------------------------------------*/
1160 void dma_c_d_unselect_in_fpga(void)
1162 unsigned long fpga_selection_2_reg;
1164 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
1165 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1168 /*----------------------------------------------------------------------------+
1169 | usb2_device_selection_in_fpga.
1170 +----------------------------------------------------------------------------*/
1171 void usb2_device_selection_in_fpga(void)
1173 unsigned long fpga_selection_1_reg;
1175 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
1176 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1179 /*----------------------------------------------------------------------------+
1180 | usb2_device_reset_through_fpga.
1181 +----------------------------------------------------------------------------*/
1182 void usb2_device_reset_through_fpga(void)
1184 /* Perform soft Reset pulse */
1185 unsigned long fpga_reset_reg;
1188 fpga_reset_reg = in8(FPGA_RESET_REG);
1189 out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1190 for (i=0; i<500; i++)
1192 out8(FPGA_RESET_REG,fpga_reset_reg);
1195 /*----------------------------------------------------------------------------+
1196 | usb2_host_selection_in_fpga.
1197 +----------------------------------------------------------------------------*/
1198 void usb2_host_selection_in_fpga(void)
1200 unsigned long fpga_selection_1_reg;
1202 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1203 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1206 /*----------------------------------------------------------------------------+
1207 | ndfc_selection_in_fpga.
1208 +----------------------------------------------------------------------------*/
1209 void ndfc_selection_in_fpga(void)
1211 unsigned long fpga_selection_1_reg;
1213 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1214 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
1215 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
1216 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1219 /*----------------------------------------------------------------------------+
1220 | uart_selection_in_fpga.
1221 +----------------------------------------------------------------------------*/
1222 void uart_selection_in_fpga(uart_config_nb_t uart_config)
1225 unsigned char fpga_selection_3_reg;
1227 /* Read FPGA Reagister */
1228 fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1230 switch (uart_config)
1233 /* ----------------------------------------------------------------------- */
1234 /* L1 configuration: UART0 = 8 pins */
1235 /* ----------------------------------------------------------------------- */
1236 /* Configure FPGA */
1237 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1238 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
1239 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1244 /* ----------------------------------------------------------------------- */
1245 /* L2 configuration: UART0 = 4 pins */
1246 /* UART1 = 4 pins */
1247 /* ----------------------------------------------------------------------- */
1248 /* Configure FPGA */
1249 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1250 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
1251 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1256 /* ----------------------------------------------------------------------- */
1257 /* L3 configuration: UART0 = 4 pins */
1258 /* UART1 = 2 pins */
1259 /* UART2 = 2 pins */
1260 /* ----------------------------------------------------------------------- */
1261 /* Configure FPGA */
1262 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1263 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
1264 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1268 /* Configure FPGA */
1269 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1270 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
1271 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1276 /* Unsupported UART configuration number */
1285 /*----------------------------------------------------------------------------+
1287 +----------------------------------------------------------------------------*/
1288 void init_default_gpio(void)
1293 for(i=0; i<GPIO_MAX; i++)
1295 gpio_tab[GPIO0][i].add = GPIO0_BASE;
1296 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1297 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1301 for(i=0; i<GPIO_MAX; i++)
1303 gpio_tab[GPIO1][i].add = GPIO1_BASE;
1304 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1305 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1308 /* EBC_CS_N(5) - GPIO0_10 */
1309 gpio_tab[GPIO0][10].in_out = GPIO_OUT;
1310 gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
1312 /* EBC_CS_N(4) - GPIO0_9 */
1313 gpio_tab[GPIO0][9].in_out = GPIO_OUT;
1314 gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
1317 /*----------------------------------------------------------------------------+
1319 +------------------------------------------------------------------------------
1321 | Set UART Configuration in PowerPC440EP
1323 | +---------------------------------------------------------------------+
1324 | | Configuartion | Connector | Nb of pins | Pins | Associated |
1325 | | Number | Port Name | available | naming | CORE |
1326 | +-----------------+---------------+------------+--------+-------------+
1327 | | L1 | Port_A | 8 | UART | UART core 0 |
1328 | +-----------------+---------------+------------+--------+-------------+
1329 | | L2 | Port_A | 4 | UART1 | UART core 0 |
1330 | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
1331 | +-----------------+---------------+------------+--------+-------------+
1332 | | L3 | Port_A | 4 | UART1 | UART core 0 |
1333 | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
1334 | | | Port_C | 2 | UART3 | UART core 2 |
1335 | +-----------------+---------------+------------+--------+-------------+
1336 | | | Port_A | 2 | UART1 | UART core 0 |
1337 | | L4 | Port_B | 2 | UART2 | UART core 1 |
1338 | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
1339 | | | Port_D | 2 | UART4 | UART core 3 |
1340 | +-----------------+---------------+------------+--------+-------------+
1344 | +------------------------------------------------------------------------------+
1345 | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
1346 | +---------+------------------+-----+-----------------+-----+-------------+-----+
1347 | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
1348 | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
1349 | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
1350 | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
1351 | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
1352 | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
1353 | +------------------------------------------------------------------------------+
1356 +----------------------------------------------------------------------------*/
1358 void update_uart_ios(uart_config_nb_t uart_config)
1360 switch (uart_config)
1363 /* ----------------------------------------------------------------------- */
1364 /* L1 configuration: UART0 = 8 pins */
1365 /* ----------------------------------------------------------------------- */
1366 /* Update GPIO Configuration Table */
1367 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1368 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1370 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1371 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1373 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1374 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1376 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1377 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1379 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1380 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1382 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1383 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1388 /* ----------------------------------------------------------------------- */
1389 /* L2 configuration: UART0 = 4 pins */
1390 /* UART1 = 4 pins */
1391 /* ----------------------------------------------------------------------- */
1392 /* Update GPIO Configuration Table */
1393 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1394 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1396 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1397 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1399 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1400 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1402 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1403 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1405 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1406 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1408 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1409 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1414 /* ----------------------------------------------------------------------- */
1415 /* L3 configuration: UART0 = 4 pins */
1416 /* UART1 = 2 pins */
1417 /* UART2 = 2 pins */
1418 /* ----------------------------------------------------------------------- */
1419 /* Update GPIO Configuration Table */
1420 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1421 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1423 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1424 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1426 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1427 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1429 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1430 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1432 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1433 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1435 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1436 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1441 /* ----------------------------------------------------------------------- */
1442 /* L4 configuration: UART0 = 2 pins */
1443 /* UART1 = 2 pins */
1444 /* UART2 = 2 pins */
1445 /* UART3 = 2 pins */
1446 /* ----------------------------------------------------------------------- */
1447 /* Update GPIO Configuration Table */
1448 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1449 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1451 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1452 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1454 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1455 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1457 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1458 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1460 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1461 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1463 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1464 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1469 /* Unsupported UART configuration number */
1470 printf("ERROR - Unsupported UART configuration number.\n\n");
1477 /* Set input Selection Register on Alt_Receive for UART Input Core */
1478 out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1479 out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1480 out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1483 /*----------------------------------------------------------------------------+
1484 | update_ndfc_ios(void).
1485 +----------------------------------------------------------------------------*/
1486 void update_ndfc_ios(void)
1488 /* Update GPIO Configuration Table */
1489 gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
1490 gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
1493 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
1494 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1496 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
1497 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1501 /*----------------------------------------------------------------------------+
1502 | update_zii_ios(void).
1503 +----------------------------------------------------------------------------*/
1504 void update_zii_ios(void)
1506 /* Update GPIO Configuration Table */
1507 gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
1508 gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
1510 gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
1511 gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
1513 gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
1514 gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
1516 gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
1517 gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
1519 gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
1520 gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
1522 gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
1523 gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
1525 gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
1526 gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
1528 gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
1529 gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
1531 gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
1532 gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
1534 gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
1535 gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
1537 gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
1538 gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
1540 gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
1541 gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
1543 gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
1544 gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
1546 gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
1547 gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
1551 /*----------------------------------------------------------------------------+
1552 | update_uic_0_3_irq_ios().
1553 +----------------------------------------------------------------------------*/
1554 void update_uic_0_3_irq_ios(void)
1556 gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
1557 gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1559 gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
1560 gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1562 gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
1563 gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1565 gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
1566 gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1569 /*----------------------------------------------------------------------------+
1570 | update_uic_4_9_irq_ios().
1571 +----------------------------------------------------------------------------*/
1572 void update_uic_4_9_irq_ios(void)
1574 gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
1575 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1577 gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
1578 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1580 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
1581 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1583 gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
1584 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1586 gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
1587 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1590 /*----------------------------------------------------------------------------+
1591 | update_dma_a_b_ios().
1592 +----------------------------------------------------------------------------*/
1593 void update_dma_a_b_ios(void)
1595 gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
1596 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1598 gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
1599 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1601 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
1602 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1604 gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
1605 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1607 gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
1608 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1611 /*----------------------------------------------------------------------------+
1612 | update_dma_c_d_ios().
1613 +----------------------------------------------------------------------------*/
1614 void update_dma_c_d_ios(void)
1616 gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
1617 gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1619 gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
1620 gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1622 gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
1623 gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1625 gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
1626 gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1628 gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
1629 gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1631 gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
1632 gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1636 /*----------------------------------------------------------------------------+
1637 | update_ebc_master_ios().
1638 +----------------------------------------------------------------------------*/
1639 void update_ebc_master_ios(void)
1641 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
1642 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1644 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1645 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1647 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
1648 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1650 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
1651 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1654 /*----------------------------------------------------------------------------+
1655 | update_usb2_device_ios().
1656 +----------------------------------------------------------------------------*/
1657 void update_usb2_device_ios(void)
1659 gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
1660 gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1662 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
1663 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1665 gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
1666 gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1668 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
1669 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1671 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
1672 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1674 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
1675 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1677 gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
1678 gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1680 gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
1681 gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1685 /*----------------------------------------------------------------------------+
1686 | update_pci_patch_ios().
1687 +----------------------------------------------------------------------------*/
1688 void update_pci_patch_ios(void)
1690 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1691 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1694 /*----------------------------------------------------------------------------+
1695 | set_chip_gpio_configuration(unsigned char gpio_core)
1696 | Put the core impacted by clock modification and sharing in reset.
1697 | Config the select registers to resolve the sharing depending of the config.
1698 | Configure the GPIO registers.
1700 +----------------------------------------------------------------------------*/
1701 void set_chip_gpio_configuration(unsigned char gpio_core)
1703 unsigned char i=0, j=0, reg_offset = 0;
1704 unsigned long gpio_reg, gpio_core_add;
1706 /* GPIO config of the GPIOs 0 to 31 */
1707 for (i=0; i<GPIO_MAX; i++, j++)
1709 if (i == GPIO_MAX/2)
1715 gpio_core_add = gpio_tab[gpio_core][i].add;
1717 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1718 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1720 switch (gpio_tab[gpio_core][i].alt_nb)
1726 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1727 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1728 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1732 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1733 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1734 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1738 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1739 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1740 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1744 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1745 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1748 switch (gpio_tab[gpio_core][i].alt_nb)
1753 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1754 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1755 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1756 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1757 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1758 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1761 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1762 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1763 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1764 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1765 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1766 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1769 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1770 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1771 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1772 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1773 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1774 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1781 /*----------------------------------------------------------------------------+
1782 | force_bup_core_selection.
1783 +----------------------------------------------------------------------------*/
1784 void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1786 /* Pointer invalid */
1787 if (core_select_P == NULL)
1789 printf("Configuration invalid pointer 1\n");
1795 *(core_select_P+UART_CORE0) = CORE_SELECTED;
1796 *(core_select_P+UART_CORE1) = CORE_SELECTED;
1797 *(core_select_P+UART_CORE2) = CORE_SELECTED;
1798 *(core_select_P+UART_CORE3) = CORE_SELECTED;
1800 /* RMII Selection */
1801 *(core_select_P+RMII_SEL) = CORE_SELECTED;
1803 /* External Interrupt 0-9 selection */
1804 *(core_select_P+UIC_0_3) = CORE_SELECTED;
1805 *(core_select_P+UIC_4_9) = CORE_SELECTED;
1807 *(core_select_P+SCP_CORE) = CORE_SELECTED;
1808 *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
1809 *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
1810 *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
1812 if (is_nand_selected()) {
1813 *(core_select_P+NAND_FLASH) = CORE_SELECTED;
1816 *config_val_P = CONFIG_IS_VALID;
1820 /*----------------------------------------------------------------------------+
1821 | configure_ppc440ep_pins.
1822 +----------------------------------------------------------------------------*/
1823 void configure_ppc440ep_pins(void)
1825 uart_config_nb_t uart_configuration;
1826 config_validity_t config_val = CONFIG_IS_INVALID;
1828 /* Create Core Selection Table */
1829 core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1831 CORE_NOT_SELECTED, /* IIC_CORE, */
1832 CORE_NOT_SELECTED, /* SPC_CORE, */
1833 CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
1834 CORE_NOT_SELECTED, /* UIC_4_9, */
1835 CORE_NOT_SELECTED, /* USB2_HOST, */
1836 CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
1837 CORE_NOT_SELECTED, /* USB2_DEVICE, */
1838 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
1839 CORE_NOT_SELECTED, /* USB1_DEVICE, */
1840 CORE_NOT_SELECTED, /* EBC_MASTER, */
1841 CORE_NOT_SELECTED, /* NAND_FLASH, */
1842 CORE_NOT_SELECTED, /* UART_CORE0, */
1843 CORE_NOT_SELECTED, /* UART_CORE1, */
1844 CORE_NOT_SELECTED, /* UART_CORE2, */
1845 CORE_NOT_SELECTED, /* UART_CORE3, */
1846 CORE_NOT_SELECTED, /* MII_SEL, */
1847 CORE_NOT_SELECTED, /* RMII_SEL, */
1848 CORE_NOT_SELECTED, /* SMII_SEL, */
1849 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
1850 CORE_NOT_SELECTED, /* UIC_0_3 */
1851 CORE_NOT_SELECTED, /* USB1_HOST */
1852 CORE_NOT_SELECTED /* PCI_PATCH */
1856 /* Table Default Initialisation + FPGA Access */
1857 init_default_gpio();
1858 set_chip_gpio_configuration(GPIO0);
1859 set_chip_gpio_configuration(GPIO1);
1862 force_bup_core_selection(ppc440ep_core_selection, &config_val);
1863 #if 0 /* test-only */
1864 /* If we are running PIBS 1, force known configuration */
1865 update_core_selection_table(ppc440ep_core_selection, &config_val);
1868 /*----------------------------------------------------------------------------+
1869 | SDR + ios table update + fpga initialization
1870 +----------------------------------------------------------------------------*/
1871 unsigned long sdr0_pfc1 = 0;
1872 unsigned long sdr0_usb0 = 0;
1873 unsigned long sdr0_mfr = 0;
1875 /* PCI Always selected */
1878 if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1880 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1881 iic1_selection_in_fpga();
1885 if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1887 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1888 scp_selection_in_fpga();
1891 /* UIC 0:3 Selection */
1892 if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1894 update_uic_0_3_irq_ios();
1895 dma_a_b_unselect_in_fpga();
1898 /* UIC 4:9 Selection */
1899 if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1901 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
1902 update_uic_4_9_irq_ios();
1905 /* DMA AB Selection */
1906 if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1908 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
1909 update_dma_a_b_ios();
1910 dma_a_b_selection_in_fpga();
1913 /* DMA CD Selection */
1914 if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1916 update_dma_c_d_ios();
1917 dma_c_d_selection_in_fpga();
1920 /* EBC Master Selection */
1921 if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1923 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1924 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1925 update_ebc_master_ios();
1928 /* PCI Patch Enable */
1929 if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1931 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1932 update_pci_patch_ios();
1935 /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1936 if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1938 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1939 printf("Invalid configuration => USB2 Host selected\n");
1942 /*usb2_host_selection_in_fpga(); */
1945 /* USB2.0 Device Selection */
1946 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1948 update_usb2_device_ios();
1949 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1950 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1952 mfsdr(sdr_usb0, sdr0_usb0);
1953 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1954 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
1955 mtsdr(sdr_usb0, sdr0_usb0);
1957 usb2_device_selection_in_fpga();
1960 /* USB1.1 Device Selection */
1961 if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1963 mfsdr(sdr_usb0, sdr0_usb0);
1964 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1965 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
1966 mtsdr(sdr_usb0, sdr0_usb0);
1969 /* USB1.1 Host Selection */
1970 if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1972 mfsdr(sdr_usb0, sdr0_usb0);
1973 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1974 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
1975 mtsdr(sdr_usb0, sdr0_usb0);
1978 /* NAND Flash Selection */
1979 if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
1983 mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
1984 SDR0_CUST0_NDFC_ENABLE |
1985 SDR0_CUST0_NDFC_BW_8_BIT |
1986 SDR0_CUST0_NDFC_ARE_MASK |
1987 SDR0_CUST0_CHIPSELGAT_EN1 |
1988 SDR0_CUST0_CHIPSELGAT_EN2);
1990 ndfc_selection_in_fpga();
1994 /* Set Mux on EMAC */
1995 mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
1999 if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
2002 mfsdr(sdr_mfr, sdr0_mfr);
2003 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
2004 mtsdr(sdr_mfr, sdr0_mfr);
2006 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
2009 /* RMII Selection */
2010 if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
2013 mfsdr(sdr_mfr, sdr0_mfr);
2014 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
2015 mtsdr(sdr_mfr, sdr0_mfr);
2017 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
2020 /* SMII Selection */
2021 if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
2024 mfsdr(sdr_mfr, sdr0_mfr);
2025 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
2026 mtsdr(sdr_mfr, sdr0_mfr);
2028 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
2031 /* UART Selection */
2032 uart_configuration = get_uart_configuration();
2033 switch (uart_configuration)
2035 case L1: /* L1 Selection */
2036 /* UART0 8 pins Only */
2037 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
2038 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
2039 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
2041 case L2: /* L2 Selection */
2042 /* UART0 and UART1 4 pins */
2043 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2044 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2045 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2047 case L3: /* L3 Selection */
2048 /* UART0 4 pins, UART1 and UART2 2 pins */
2049 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2050 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2051 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2053 case L4: /* L4 Selection */
2054 /* UART0, UART1, UART2 and UART3 2 pins */
2055 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
2056 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2057 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2060 update_uart_ios(uart_configuration);
2062 /* UART Selection in all cases */
2063 uart_selection_in_fpga(uart_configuration);
2065 /* Packet Reject Function Available */
2066 if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
2068 /* Set UPR Bit in SDR0_PFC1 Register */
2069 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
2072 /* Packet Reject Function Enable */
2073 if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
2075 mfsdr(sdr_mfr, sdr0_mfr);
2076 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
2077 mtsdr(sdr_mfr, sdr0_mfr);
2080 /* Perform effective access to hardware */
2081 mtsdr(sdr_pfc1, sdr0_pfc1);
2082 set_chip_gpio_configuration(GPIO0);
2083 set_chip_gpio_configuration(GPIO1);
2085 /* USB2.0 Device Reset must be done after GPIO setting */
2086 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
2087 usb2_device_reset_through_fpga();