2 * (C) Copyright 2005-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
27 #include <spd_sdram.h>
31 void ext_bus_cntlr_init(void);
32 void configure_ppc440ep_pins(void);
33 int is_nand_selected(void);
35 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
36 /*************************************************************************
38 * Bamboo has one bank onboard sdram (plus DIMM)
40 * Fixed memory is composed of :
41 * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
42 * 13 row add bits, 10 column add bits (but 12 row used only).
43 * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
44 * 12 row add bits, 10 column add bits.
45 * Prepare a subset (only the used ones) of SPD data
47 * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
48 * the corresponding bank is divided by 2 due to number of Row addresses
49 * 12 in the ECC module
51 * Assumes: 64 MB, ECC, non-registered
54 ************************************************************************/
55 const unsigned char cfg_simulate_spd_eeprom[128] = {
56 0x80, /* number of SPD bytes used: 128 */
57 0x08, /* total number bytes in SPD device = 256 */
60 0x0C, /* num Row Addr: 12 */
62 0x0D, /* num Row Addr: 13 */
64 0x09, /* numColAddr: 9 */
65 0x01, /* numBanks: 1 */
66 0x20, /* Module data width: 32 bits */
67 0x00, /* Module data width continued: +0 */
69 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
70 0x00, /* SDRAM Access from clock */
72 0x02, /* ECC ON : 02 OFF : 00 */
74 0x00, /* ECC ON : 02 OFF : 00 */
76 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
82 0x0C, /* casBit (2,2.5) */
85 0x00, /* not registered: 0 registered : 0x02*/
87 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
89 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
91 0x50, /* tRpNs = 20 ns */
93 0x50, /* tRcdNs = 20 ns */
96 0x08, /* bankSizeID: 32MB */
98 0x10, /* bankSizeID: 64MB */
200 { /* GPIO Alternate1 Alternate2 Alternate3 */
203 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
204 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
205 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
206 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
207 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
208 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
209 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
210 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
211 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
212 { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
213 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
214 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
215 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
216 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
217 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
218 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
219 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
220 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
221 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
222 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
223 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
224 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
225 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
226 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
227 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
228 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
229 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
230 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
231 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
232 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
233 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
234 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
238 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
239 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
240 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
241 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
242 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
243 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
244 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
245 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
246 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
247 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
248 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
249 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
250 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
251 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
252 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
253 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
254 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
255 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
256 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
257 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
258 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
259 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
260 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
261 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
262 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
263 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
264 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
265 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
266 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
267 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
268 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
269 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
274 /*----------------------------------------------------------------------------+
275 | EBC Devices Characteristics
276 | Peripheral Bank Access Parameters - EBC0_BnAP
277 | Peripheral Bank Configuration Register - EBC0_BnCR
278 +----------------------------------------------------------------------------*/
280 #define EBC0_BNAP_SMALL_FLASH \
281 EBC0_BNAP_BME_DISABLED | \
282 EBC0_BNAP_TWT_ENCODE(6) | \
283 EBC0_BNAP_CSN_ENCODE(0) | \
284 EBC0_BNAP_OEN_ENCODE(1) | \
285 EBC0_BNAP_WBN_ENCODE(1) | \
286 EBC0_BNAP_WBF_ENCODE(3) | \
287 EBC0_BNAP_TH_ENCODE(1) | \
288 EBC0_BNAP_RE_ENABLED | \
289 EBC0_BNAP_SOR_DELAYED | \
290 EBC0_BNAP_BEM_WRITEONLY | \
291 EBC0_BNAP_PEN_DISABLED
293 #define EBC0_BNCR_SMALL_FLASH_CS0 \
294 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
299 #define EBC0_BNCR_SMALL_FLASH_CS4 \
300 EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
305 /* Large Flash or SRAM */
306 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
307 EBC0_BNAP_BME_DISABLED | \
308 EBC0_BNAP_TWT_ENCODE(8) | \
309 EBC0_BNAP_CSN_ENCODE(0) | \
310 EBC0_BNAP_OEN_ENCODE(1) | \
311 EBC0_BNAP_WBN_ENCODE(1) | \
312 EBC0_BNAP_WBF_ENCODE(1) | \
313 EBC0_BNAP_TH_ENCODE(2) | \
314 EBC0_BNAP_SOR_DELAYED | \
316 EBC0_BNAP_PEN_DISABLED
318 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
319 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
325 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
326 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
332 #define EBC0_BNAP_NVRAM_FPGA \
333 EBC0_BNAP_BME_DISABLED | \
334 EBC0_BNAP_TWT_ENCODE(9) | \
335 EBC0_BNAP_CSN_ENCODE(0) | \
336 EBC0_BNAP_OEN_ENCODE(1) | \
337 EBC0_BNAP_WBN_ENCODE(1) | \
338 EBC0_BNAP_WBF_ENCODE(0) | \
339 EBC0_BNAP_TH_ENCODE(2) | \
340 EBC0_BNAP_RE_ENABLED | \
341 EBC0_BNAP_SOR_DELAYED | \
342 EBC0_BNAP_BEM_WRITEONLY | \
343 EBC0_BNAP_PEN_DISABLED
345 #define EBC0_BNCR_NVRAM_FPGA_CS5 \
346 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
352 #define EBC0_BNAP_NAND_FLASH \
353 EBC0_BNAP_BME_DISABLED | \
354 EBC0_BNAP_TWT_ENCODE(3) | \
355 EBC0_BNAP_CSN_ENCODE(0) | \
356 EBC0_BNAP_OEN_ENCODE(0) | \
357 EBC0_BNAP_WBN_ENCODE(0) | \
358 EBC0_BNAP_WBF_ENCODE(0) | \
359 EBC0_BNAP_TH_ENCODE(1) | \
360 EBC0_BNAP_RE_ENABLED | \
361 EBC0_BNAP_SOR_NOT_DELAYED | \
363 EBC0_BNAP_PEN_DISABLED
366 #define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
369 #define EBC0_BNCR_NAND_FLASH_CS1 \
370 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
375 #define EBC0_BNCR_NAND_FLASH_CS2 \
376 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
382 #define EBC0_BNCR_NAND_FLASH_CS3 \
383 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
388 int board_early_init_f(void)
390 ext_bus_cntlr_init();
392 /*--------------------------------------------------------------------
393 * Setup the interrupt controller polarities, triggers, etc.
394 *-------------------------------------------------------------------*/
395 mtdcr(UIC0SR, 0xffffffff); /* clear all */
396 mtdcr(UIC0ER, 0x00000000); /* disable all */
397 mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
398 mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
399 mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
400 mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
401 mtdcr(UIC0SR, 0xffffffff); /* clear all */
403 mtdcr(UIC1SR, 0xffffffff); /* clear all */
404 mtdcr(UIC1ER, 0x00000000); /* disable all */
405 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
406 mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
407 mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
408 mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
409 mtdcr(UIC1SR, 0xffffffff); /* clear all */
411 /*--------------------------------------------------------------------
412 * Setup the GPIO pins
413 *-------------------------------------------------------------------*/
414 out32(GPIO0_OSRL, 0x00000400);
415 out32(GPIO0_OSRH, 0x00000000);
416 out32(GPIO0_TSRL, 0x00000400);
417 out32(GPIO0_TSRH, 0x00000000);
418 out32(GPIO0_ISR1L, 0x00000000);
419 out32(GPIO0_ISR1H, 0x00000000);
420 out32(GPIO0_ISR2L, 0x00000000);
421 out32(GPIO0_ISR2H, 0x00000000);
422 out32(GPIO0_ISR3L, 0x00000000);
423 out32(GPIO0_ISR3H, 0x00000000);
425 out32(GPIO1_OSRL, 0x0C380000);
426 out32(GPIO1_OSRH, 0x00000000);
427 out32(GPIO1_TSRL, 0x0C380000);
428 out32(GPIO1_TSRH, 0x00000000);
429 out32(GPIO1_ISR1L, 0x0FC30000);
430 out32(GPIO1_ISR1H, 0x00000000);
431 out32(GPIO1_ISR2L, 0x0C010000);
432 out32(GPIO1_ISR2H, 0x00000000);
433 out32(GPIO1_ISR3L, 0x01400000);
434 out32(GPIO1_ISR3H, 0x00000000);
436 configure_ppc440ep_pins();
443 char *s = getenv("serial#");
445 printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
456 phys_size_t initdram (int board_type)
458 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
461 dram_size = spd_sdram();
465 return CONFIG_SYS_MBYTES_SDRAM << 20;
469 /*************************************************************************
472 * This routine is called just prior to registering the hose and gives
473 * the board the opportunity to check things. Returning a value of zero
474 * indicates that things are bad & PCI initialization should be aborted.
476 * Different boards may wish to customize the pci controller structure
477 * (add regions, override default access routines, etc) or perform
478 * certain pre-initialization actions.
480 ************************************************************************/
481 #if defined(CONFIG_PCI)
482 int pci_pre_init(struct pci_controller *hose)
486 /*-------------------------------------------------------------------------+
487 | Set priority for all PLB3 devices to 0.
488 | Set PLB3 arbiter to fair mode.
489 +-------------------------------------------------------------------------*/
490 mfsdr(SD0_AMP1, addr);
491 mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
492 addr = mfdcr(PLB3_ACR);
493 mtdcr(PLB3_ACR, addr | 0x80000000);
495 /*-------------------------------------------------------------------------+
496 | Set priority for all PLB4 devices to 0.
497 +-------------------------------------------------------------------------*/
498 mfsdr(SD0_AMP0, addr);
499 mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
500 addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
501 mtdcr(PLB4_ACR, addr);
503 /*-------------------------------------------------------------------------+
504 | Set Nebula PLB4 arbiter to fair mode.
505 +-------------------------------------------------------------------------*/
507 addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
508 addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
509 addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
510 addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
511 mtdcr(PLB0_ACR, addr);
514 addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
515 addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
516 addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
517 addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
518 mtdcr(PLB1_ACR, addr);
522 #endif /* defined(CONFIG_PCI) */
524 /*************************************************************************
527 ************************************************************************/
528 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
529 void pci_master_init(struct pci_controller *hose)
531 unsigned short temp_short;
533 /*--------------------------------------------------------------------------+
534 | Write the PowerPC440 EP PCI Configuration regs.
535 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
536 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
537 +--------------------------------------------------------------------------*/
538 pci_read_config_word(0, PCI_COMMAND, &temp_short);
539 pci_write_config_word(0, PCI_COMMAND,
540 temp_short | PCI_COMMAND_MASTER |
543 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
545 /*----------------------------------------------------------------------------+
546 | is_powerpc440ep_pass1.
547 +----------------------------------------------------------------------------*/
548 int is_powerpc440ep_pass1(void)
554 if (pvr == PVR_POWERPC_440EP_PASS1)
556 else if (pvr == PVR_POWERPC_440EP_PASS2)
559 printf("brdutil error 3\n");
567 /*----------------------------------------------------------------------------+
569 +----------------------------------------------------------------------------*/
570 int is_nand_selected(void)
572 #ifdef CONFIG_BAMBOO_NAND
579 /*----------------------------------------------------------------------------+
580 | config_on_ebc_cs4_is_small_flash => from EPLD
581 +----------------------------------------------------------------------------*/
582 unsigned char config_on_ebc_cs4_is_small_flash(void)
584 /* Not implemented yet => returns constant value */
588 /*----------------------------------------------------------------------------+
589 | Ext_bus_cntlr_init.
590 | Initialize the external bus controller
591 +----------------------------------------------------------------------------*/
592 void ext_bus_cntlr_init(void)
594 unsigned long sdr0_pstrp0, sdr0_sdstp1;
595 unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
596 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
597 unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
598 unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
599 unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
600 unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
601 unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
604 /*-------------------------------------------------------------------------+
606 | PART 1 : Initialize EBC Bank 5
607 | ==============================
608 | Bank5 is always associated to the NVRAM/EPLD.
609 | It has to be initialized prior to other banks settings computation since
610 | some board registers values may be needed
612 +-------------------------------------------------------------------------*/
614 mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA);
615 mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5);
617 /*-------------------------------------------------------------------------+
619 | PART 2 : Determine which boot device was selected
620 | =========================================
622 | Read Pin Strap Register in PPC440EP
623 | In case of boot from IIC, read Serial Device Strap Register1
625 | Result can either be :
626 | - Boot from EBC 8bits => SMALL FLASH
627 | - Boot from EBC 16bits => Large Flash or SRAM
628 | - Boot from NAND Flash
631 +-------------------------------------------------------------------------*/
632 /* Read Pin Strap Register in PPC440EP */
633 mfsdr(sdr_pstrp0, sdr0_pstrp0);
634 bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
636 /*-------------------------------------------------------------------------+
638 +-------------------------------------------------------------------------*/
639 if (is_powerpc440ep_pass1() == TRUE) {
640 switch(bootstrap_settings) {
641 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
642 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
643 /* Boot from Small Flash */
644 computed_boot_device = BOOT_FROM_SMALL_FLASH;
646 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
647 /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
649 computed_boot_device = BOOT_FROM_PCI;
652 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
653 /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
654 /* Boot from Nand Flash */
655 computed_boot_device = BOOT_FROM_NAND_FLASH0;
658 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
659 /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
660 /* Boot from Small Flash */
661 computed_boot_device = BOOT_FROM_SMALL_FLASH;
664 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
665 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
666 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
667 /* Read Serial Device Strap Register1 in PPC440EP */
668 mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
669 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
670 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
672 switch(boot_selection) {
673 case SDR0_SDSTP1_BOOT_SEL_EBC:
674 switch(ebc_boot_size) {
675 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
676 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
678 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
679 computed_boot_device = BOOT_FROM_SMALL_FLASH;
684 case SDR0_SDSTP1_BOOT_SEL_PCI:
685 computed_boot_device = BOOT_FROM_PCI;
688 case SDR0_SDSTP1_BOOT_SEL_NDFC:
689 computed_boot_device = BOOT_FROM_NAND_FLASH0;
696 /*-------------------------------------------------------------------------+
698 +-------------------------------------------------------------------------*/
700 switch(bootstrap_settings) {
701 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
702 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
703 /* Boot from Small Flash */
704 computed_boot_device = BOOT_FROM_SMALL_FLASH;
706 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
707 /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
709 computed_boot_device = BOOT_FROM_PCI;
712 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
713 /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
714 /* Boot from Nand Flash */
715 computed_boot_device = BOOT_FROM_NAND_FLASH0;
718 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
719 /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
720 /* Boot from Large Flash or SRAM */
721 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
724 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
725 /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
726 /* Boot from Large Flash or SRAM */
727 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
730 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
731 /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
733 computed_boot_device = BOOT_FROM_PCI;
736 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
737 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
738 /* Default Strap Settings 5-7 */
739 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
740 /* Read Serial Device Strap Register1 in PPC440EP */
741 mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
742 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
743 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
745 switch(boot_selection) {
746 case SDR0_SDSTP1_BOOT_SEL_EBC:
747 switch(ebc_boot_size) {
748 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
749 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
751 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
752 computed_boot_device = BOOT_FROM_SMALL_FLASH;
757 case SDR0_SDSTP1_BOOT_SEL_PCI:
758 computed_boot_device = BOOT_FROM_PCI;
761 case SDR0_SDSTP1_BOOT_SEL_NDFC:
762 computed_boot_device = BOOT_FROM_NAND_FLASH0;
769 /*-------------------------------------------------------------------------+
771 | PART 3 : Compute EBC settings depending on selected boot device
772 | ====== ======================================================
774 | Resulting EBC init will be among following configurations :
776 | - Boot from EBC 8bits => boot from SMALL FLASH selected
777 | EBC-CS0 = Small Flash
778 | EBC-CS1,2,3 = NAND Flash or
779 | Exp.Slot depending on Soft Config
780 | EBC-CS4 = SRAM/Large Flash or
781 | Large Flash/SRAM depending on jumpers
782 | EBC-CS5 = NVRAM / EPLD
784 | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
785 | EBC-CS0 = SRAM/Large Flash or
786 | Large Flash/SRAM depending on jumpers
787 | EBC-CS1,2,3 = NAND Flash or
788 | Exp.Slot depending on Software Configuration
789 | EBC-CS4 = Small Flash
790 | EBC-CS5 = NVRAM / EPLD
792 | - Boot from NAND Flash
793 | EBC-CS0 = NAND Flash0
794 | EBC-CS1,2,3 = NAND Flash1
795 | EBC-CS4 = SRAM/Large Flash or
796 | Large Flash/SRAM depending on jumpers
797 | EBC-CS5 = NVRAM / EPLD
801 | EBC-CS1,2,3 = NAND Flash or
802 | Exp.Slot depending on Software Configuration
803 | EBC-CS4 = SRAM/Large Flash or
804 | Large Flash/SRAM or
805 | Small Flash depending on jumpers
806 | EBC-CS5 = NVRAM / EPLD
808 +-------------------------------------------------------------------------*/
810 switch(computed_boot_device) {
811 /*------------------------------------------------------------------------- */
812 case BOOT_FROM_SMALL_FLASH:
813 /*------------------------------------------------------------------------- */
814 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
815 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
816 if ((is_nand_selected()) == TRUE) {
818 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
819 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
820 ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
821 ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
822 ebc0_cs3_bnap_value = 0;
823 ebc0_cs3_bncr_value = 0;
826 ebc0_cs1_bnap_value = 0;
827 ebc0_cs1_bncr_value = 0;
828 ebc0_cs2_bnap_value = 0;
829 ebc0_cs2_bncr_value = 0;
830 ebc0_cs3_bnap_value = 0;
831 ebc0_cs3_bncr_value = 0;
833 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
834 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
838 /*------------------------------------------------------------------------- */
839 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
840 /*------------------------------------------------------------------------- */
841 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
842 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
843 if ((is_nand_selected()) == TRUE) {
845 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
846 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
847 ebc0_cs2_bnap_value = 0;
848 ebc0_cs2_bncr_value = 0;
849 ebc0_cs3_bnap_value = 0;
850 ebc0_cs3_bncr_value = 0;
853 ebc0_cs1_bnap_value = 0;
854 ebc0_cs1_bncr_value = 0;
855 ebc0_cs2_bnap_value = 0;
856 ebc0_cs2_bncr_value = 0;
857 ebc0_cs3_bnap_value = 0;
858 ebc0_cs3_bncr_value = 0;
860 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
861 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
865 /*------------------------------------------------------------------------- */
866 case BOOT_FROM_NAND_FLASH0:
867 /*------------------------------------------------------------------------- */
868 ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
869 ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
871 ebc0_cs1_bnap_value = 0;
872 ebc0_cs1_bncr_value = 0;
873 ebc0_cs2_bnap_value = 0;
874 ebc0_cs2_bncr_value = 0;
875 ebc0_cs3_bnap_value = 0;
876 ebc0_cs3_bncr_value = 0;
878 /* Large Flash or SRAM */
879 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
880 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
884 /*------------------------------------------------------------------------- */
886 /*------------------------------------------------------------------------- */
887 ebc0_cs0_bnap_value = 0;
888 ebc0_cs0_bncr_value = 0;
890 if ((is_nand_selected()) == TRUE) {
892 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
893 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
894 ebc0_cs2_bnap_value = 0;
895 ebc0_cs2_bncr_value = 0;
896 ebc0_cs3_bnap_value = 0;
897 ebc0_cs3_bncr_value = 0;
900 ebc0_cs1_bnap_value = 0;
901 ebc0_cs1_bncr_value = 0;
902 ebc0_cs2_bnap_value = 0;
903 ebc0_cs2_bncr_value = 0;
904 ebc0_cs3_bnap_value = 0;
905 ebc0_cs3_bncr_value = 0;
908 if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
910 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
911 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
913 /* Large Flash or SRAM */
914 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
915 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
920 /*------------------------------------------------------------------------- */
921 case BOOT_DEVICE_UNKNOWN:
922 /*------------------------------------------------------------------------- */
929 /*-------------------------------------------------------------------------+
930 | Initialize EBC CONFIG
931 +-------------------------------------------------------------------------*/
932 mtdcr(EBC0_CFGADDR, EBC0_CFG);
933 mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN |
934 EBC0_CFG_PTD_ENABLED |
935 EBC0_CFG_RTC_2048PERCLK |
938 EBC0_CFG_CSTC_DRIVEN |
941 EBC0_CFG_PME_DISABLED |
942 EBC0_CFG_PMT_ENCODE(0) );
944 /*-------------------------------------------------------------------------+
945 | Initialize EBC Bank 0-4
946 +-------------------------------------------------------------------------*/
948 mtebc(PB0AP, ebc0_cs0_bnap_value);
949 mtebc(PB0CR, ebc0_cs0_bncr_value);
951 mtebc(PB1AP, ebc0_cs1_bnap_value);
952 mtebc(PB1CR, ebc0_cs1_bncr_value);
954 mtebc(PB2AP, ebc0_cs2_bnap_value);
955 mtebc(PB2CR, ebc0_cs2_bncr_value);
957 mtebc(PB3AP, ebc0_cs3_bnap_value);
958 mtebc(PB3CR, ebc0_cs3_bncr_value);
960 mtebc(PB4AP, ebc0_cs4_bnap_value);
961 mtebc(PB4CR, ebc0_cs4_bncr_value);
967 /*----------------------------------------------------------------------------+
968 | get_uart_configuration.
969 +----------------------------------------------------------------------------*/
970 uart_config_nb_t get_uart_configuration(void)
975 /*----------------------------------------------------------------------------+
976 | set_phy_configuration_through_fpga => to EPLD
977 +----------------------------------------------------------------------------*/
978 void set_phy_configuration_through_fpga(zmii_config_t config)
981 unsigned long fpga_selection_reg;
983 fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
987 case ZMII_CONFIGURATION_IS_MII:
988 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
990 case ZMII_CONFIGURATION_IS_RMII:
991 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
993 case ZMII_CONFIGURATION_IS_SMII:
994 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
996 case ZMII_CONFIGURATION_UNKNOWN:
1000 out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
1004 /*----------------------------------------------------------------------------+
1005 | scp_selection_in_fpga.
1006 +----------------------------------------------------------------------------*/
1007 void scp_selection_in_fpga(void)
1009 unsigned long fpga_selection_2_reg;
1011 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1012 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
1013 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1016 /*----------------------------------------------------------------------------+
1017 | iic1_selection_in_fpga.
1018 +----------------------------------------------------------------------------*/
1019 void iic1_selection_in_fpga(void)
1021 unsigned long fpga_selection_2_reg;
1023 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1024 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
1025 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1028 /*----------------------------------------------------------------------------+
1029 | dma_a_b_selection_in_fpga.
1030 +----------------------------------------------------------------------------*/
1031 void dma_a_b_selection_in_fpga(void)
1033 unsigned long fpga_selection_2_reg;
1035 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
1036 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1039 /*----------------------------------------------------------------------------+
1040 | dma_a_b_unselect_in_fpga.
1041 +----------------------------------------------------------------------------*/
1042 void dma_a_b_unselect_in_fpga(void)
1044 unsigned long fpga_selection_2_reg;
1046 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
1047 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1050 /*----------------------------------------------------------------------------+
1051 | dma_c_d_selection_in_fpga.
1052 +----------------------------------------------------------------------------*/
1053 void dma_c_d_selection_in_fpga(void)
1055 unsigned long fpga_selection_2_reg;
1057 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
1058 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1061 /*----------------------------------------------------------------------------+
1062 | dma_c_d_unselect_in_fpga.
1063 +----------------------------------------------------------------------------*/
1064 void dma_c_d_unselect_in_fpga(void)
1066 unsigned long fpga_selection_2_reg;
1068 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
1069 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1072 /*----------------------------------------------------------------------------+
1073 | usb2_device_selection_in_fpga.
1074 +----------------------------------------------------------------------------*/
1075 void usb2_device_selection_in_fpga(void)
1077 unsigned long fpga_selection_1_reg;
1079 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
1080 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1083 /*----------------------------------------------------------------------------+
1084 | usb2_device_reset_through_fpga.
1085 +----------------------------------------------------------------------------*/
1086 void usb2_device_reset_through_fpga(void)
1088 /* Perform soft Reset pulse */
1089 unsigned long fpga_reset_reg;
1092 fpga_reset_reg = in8(FPGA_RESET_REG);
1093 out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1094 for (i=0; i<500; i++)
1096 out8(FPGA_RESET_REG,fpga_reset_reg);
1099 /*----------------------------------------------------------------------------+
1100 | usb2_host_selection_in_fpga.
1101 +----------------------------------------------------------------------------*/
1102 void usb2_host_selection_in_fpga(void)
1104 unsigned long fpga_selection_1_reg;
1106 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1107 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1110 /*----------------------------------------------------------------------------+
1111 | ndfc_selection_in_fpga.
1112 +----------------------------------------------------------------------------*/
1113 void ndfc_selection_in_fpga(void)
1115 unsigned long fpga_selection_1_reg;
1117 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1118 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
1119 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
1120 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1123 /*----------------------------------------------------------------------------+
1124 | uart_selection_in_fpga.
1125 +----------------------------------------------------------------------------*/
1126 void uart_selection_in_fpga(uart_config_nb_t uart_config)
1129 unsigned char fpga_selection_3_reg;
1131 /* Read FPGA Reagister */
1132 fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1134 switch (uart_config)
1137 /* ----------------------------------------------------------------------- */
1138 /* L1 configuration: UART0 = 8 pins */
1139 /* ----------------------------------------------------------------------- */
1140 /* Configure FPGA */
1141 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1142 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
1143 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1148 /* ----------------------------------------------------------------------- */
1149 /* L2 configuration: UART0 = 4 pins */
1150 /* UART1 = 4 pins */
1151 /* ----------------------------------------------------------------------- */
1152 /* Configure FPGA */
1153 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1154 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
1155 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1160 /* ----------------------------------------------------------------------- */
1161 /* L3 configuration: UART0 = 4 pins */
1162 /* UART1 = 2 pins */
1163 /* UART2 = 2 pins */
1164 /* ----------------------------------------------------------------------- */
1165 /* Configure FPGA */
1166 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1167 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
1168 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1172 /* Configure FPGA */
1173 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1174 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
1175 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1180 /* Unsupported UART configuration number */
1189 /*----------------------------------------------------------------------------+
1191 +----------------------------------------------------------------------------*/
1192 void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
1197 for(i=0; i<GPIO_MAX; i++)
1199 gpio_tab[GPIO0][i].add = GPIO0_BASE;
1200 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1201 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1205 for(i=0; i<GPIO_MAX; i++)
1207 gpio_tab[GPIO1][i].add = GPIO1_BASE;
1208 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1209 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1212 /* EBC_CS_N(5) - GPIO0_10 */
1213 gpio_tab[GPIO0][10].in_out = GPIO_OUT;
1214 gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
1216 /* EBC_CS_N(4) - GPIO0_9 */
1217 gpio_tab[GPIO0][9].in_out = GPIO_OUT;
1218 gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
1221 /*----------------------------------------------------------------------------+
1223 +------------------------------------------------------------------------------
1225 | Set UART Configuration in PowerPC440EP
1227 | +---------------------------------------------------------------------+
1228 | | Configuartion | Connector | Nb of pins | Pins | Associated |
1229 | | Number | Port Name | available | naming | CORE |
1230 | +-----------------+---------------+------------+--------+-------------+
1231 | | L1 | Port_A | 8 | UART | UART core 0 |
1232 | +-----------------+---------------+------------+--------+-------------+
1233 | | L2 | Port_A | 4 | UART1 | UART core 0 |
1234 | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
1235 | +-----------------+---------------+------------+--------+-------------+
1236 | | L3 | Port_A | 4 | UART1 | UART core 0 |
1237 | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
1238 | | | Port_C | 2 | UART3 | UART core 2 |
1239 | +-----------------+---------------+------------+--------+-------------+
1240 | | | Port_A | 2 | UART1 | UART core 0 |
1241 | | L4 | Port_B | 2 | UART2 | UART core 1 |
1242 | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
1243 | | | Port_D | 2 | UART4 | UART core 3 |
1244 | +-----------------+---------------+------------+--------+-------------+
1248 | +------------------------------------------------------------------------------+
1249 | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
1250 | +---------+------------------+-----+-----------------+-----+-------------+-----+
1251 | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
1252 | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
1253 | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
1254 | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
1255 | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
1256 | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
1257 | +------------------------------------------------------------------------------+
1260 +----------------------------------------------------------------------------*/
1262 void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
1264 switch (uart_config)
1267 /* ----------------------------------------------------------------------- */
1268 /* L1 configuration: UART0 = 8 pins */
1269 /* ----------------------------------------------------------------------- */
1270 /* Update GPIO Configuration Table */
1271 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1272 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1274 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1275 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1277 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1278 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1280 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1281 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1283 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1284 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1286 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1287 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1292 /* ----------------------------------------------------------------------- */
1293 /* L2 configuration: UART0 = 4 pins */
1294 /* UART1 = 4 pins */
1295 /* ----------------------------------------------------------------------- */
1296 /* Update GPIO Configuration Table */
1297 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1298 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1300 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1301 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1303 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1304 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1306 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1307 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1309 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1310 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1312 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1313 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1318 /* ----------------------------------------------------------------------- */
1319 /* L3 configuration: UART0 = 4 pins */
1320 /* UART1 = 2 pins */
1321 /* UART2 = 2 pins */
1322 /* ----------------------------------------------------------------------- */
1323 /* Update GPIO Configuration Table */
1324 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1325 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1327 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1328 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1330 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1331 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1333 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1334 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1336 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1337 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1339 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1340 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1345 /* ----------------------------------------------------------------------- */
1346 /* L4 configuration: UART0 = 2 pins */
1347 /* UART1 = 2 pins */
1348 /* UART2 = 2 pins */
1349 /* UART3 = 2 pins */
1350 /* ----------------------------------------------------------------------- */
1351 /* Update GPIO Configuration Table */
1352 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1353 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1355 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1356 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1358 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1359 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1361 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1362 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1364 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1365 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1367 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1368 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1373 /* Unsupported UART configuration number */
1374 printf("ERROR - Unsupported UART configuration number.\n\n");
1381 /* Set input Selection Register on Alt_Receive for UART Input Core */
1382 out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1383 out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1384 out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1387 /*----------------------------------------------------------------------------+
1388 | update_ndfc_ios(void).
1389 +----------------------------------------------------------------------------*/
1390 void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1392 /* Update GPIO Configuration Table */
1393 gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
1394 gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
1396 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
1397 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1400 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
1401 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1405 /*----------------------------------------------------------------------------+
1406 | update_zii_ios(void).
1407 +----------------------------------------------------------------------------*/
1408 void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1410 /* Update GPIO Configuration Table */
1411 gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
1412 gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
1414 gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
1415 gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
1417 gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
1418 gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
1420 gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
1421 gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
1423 gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
1424 gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
1426 gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
1427 gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
1429 gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
1430 gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
1432 gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
1433 gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
1435 gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
1436 gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
1438 gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
1439 gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
1441 gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
1442 gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
1444 gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
1445 gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
1447 gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
1448 gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
1450 gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
1451 gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
1455 /*----------------------------------------------------------------------------+
1456 | update_uic_0_3_irq_ios().
1457 +----------------------------------------------------------------------------*/
1458 void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1460 gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
1461 gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1463 gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
1464 gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1466 gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
1467 gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1469 gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
1470 gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1473 /*----------------------------------------------------------------------------+
1474 | update_uic_4_9_irq_ios().
1475 +----------------------------------------------------------------------------*/
1476 void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1478 gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
1479 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1481 gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
1482 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1484 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
1485 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1487 gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
1488 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1490 gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
1491 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1494 /*----------------------------------------------------------------------------+
1495 | update_dma_a_b_ios().
1496 +----------------------------------------------------------------------------*/
1497 void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1499 gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
1500 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1502 gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
1503 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1505 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
1506 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1508 gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
1509 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1511 gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
1512 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1515 /*----------------------------------------------------------------------------+
1516 | update_dma_c_d_ios().
1517 +----------------------------------------------------------------------------*/
1518 void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1520 gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
1521 gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1523 gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
1524 gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1526 gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
1527 gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1529 gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
1530 gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1532 gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
1533 gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1535 gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
1536 gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1540 /*----------------------------------------------------------------------------+
1541 | update_ebc_master_ios().
1542 +----------------------------------------------------------------------------*/
1543 void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1545 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
1546 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1548 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1549 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1551 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
1552 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1554 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
1555 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1558 /*----------------------------------------------------------------------------+
1559 | update_usb2_device_ios().
1560 +----------------------------------------------------------------------------*/
1561 void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1563 gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
1564 gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1566 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
1567 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1569 gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
1570 gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1572 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
1573 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1575 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
1576 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1578 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
1579 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1581 gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
1582 gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1584 gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
1585 gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1589 /*----------------------------------------------------------------------------+
1590 | update_pci_patch_ios().
1591 +----------------------------------------------------------------------------*/
1592 void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1594 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1595 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1598 /*----------------------------------------------------------------------------+
1599 | set_chip_gpio_configuration(unsigned char gpio_core,
1600 | gpio_param_s (*gpio_tab)[GPIO_MAX])
1601 | Put the core impacted by clock modification and sharing in reset.
1602 | Config the select registers to resolve the sharing depending of the config.
1603 | Configure the GPIO registers.
1605 +----------------------------------------------------------------------------*/
1606 void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
1608 unsigned char i=0, j=0, reg_offset = 0;
1609 unsigned long gpio_reg, gpio_core_add;
1611 /* GPIO config of the GPIOs 0 to 31 */
1612 for (i=0; i<GPIO_MAX; i++, j++)
1614 if (i == GPIO_MAX/2)
1620 gpio_core_add = gpio_tab[gpio_core][i].add;
1622 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1623 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1625 switch (gpio_tab[gpio_core][i].alt_nb)
1631 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1632 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1633 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1637 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1638 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1639 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1643 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1644 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1645 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1649 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1650 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1653 switch (gpio_tab[gpio_core][i].alt_nb)
1658 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1659 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1660 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1661 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1662 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1663 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1666 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1667 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1668 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1669 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1670 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1671 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1674 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1675 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1676 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1677 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1678 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1679 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1686 /*----------------------------------------------------------------------------+
1687 | force_bup_core_selection.
1688 +----------------------------------------------------------------------------*/
1689 void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1691 /* Pointer invalid */
1692 if (core_select_P == NULL)
1694 printf("Configuration invalid pointer 1\n");
1700 *(core_select_P+UART_CORE0) = CORE_SELECTED;
1701 *(core_select_P+UART_CORE1) = CORE_SELECTED;
1702 *(core_select_P+UART_CORE2) = CORE_SELECTED;
1703 *(core_select_P+UART_CORE3) = CORE_SELECTED;
1705 /* RMII Selection */
1706 *(core_select_P+RMII_SEL) = CORE_SELECTED;
1708 /* External Interrupt 0-9 selection */
1709 *(core_select_P+UIC_0_3) = CORE_SELECTED;
1710 *(core_select_P+UIC_4_9) = CORE_SELECTED;
1712 *(core_select_P+SCP_CORE) = CORE_SELECTED;
1713 *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
1714 *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
1715 *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
1717 if (is_nand_selected()) {
1718 *(core_select_P+NAND_FLASH) = CORE_SELECTED;
1721 *config_val_P = CONFIG_IS_VALID;
1725 /*----------------------------------------------------------------------------+
1726 | configure_ppc440ep_pins.
1727 +----------------------------------------------------------------------------*/
1728 void configure_ppc440ep_pins(void)
1730 uart_config_nb_t uart_configuration;
1731 config_validity_t config_val = CONFIG_IS_INVALID;
1733 /* Create Core Selection Table */
1734 core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1736 CORE_NOT_SELECTED, /* IIC_CORE, */
1737 CORE_NOT_SELECTED, /* SPC_CORE, */
1738 CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
1739 CORE_NOT_SELECTED, /* UIC_4_9, */
1740 CORE_NOT_SELECTED, /* USB2_HOST, */
1741 CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
1742 CORE_NOT_SELECTED, /* USB2_DEVICE, */
1743 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
1744 CORE_NOT_SELECTED, /* USB1_DEVICE, */
1745 CORE_NOT_SELECTED, /* EBC_MASTER, */
1746 CORE_NOT_SELECTED, /* NAND_FLASH, */
1747 CORE_NOT_SELECTED, /* UART_CORE0, */
1748 CORE_NOT_SELECTED, /* UART_CORE1, */
1749 CORE_NOT_SELECTED, /* UART_CORE2, */
1750 CORE_NOT_SELECTED, /* UART_CORE3, */
1751 CORE_NOT_SELECTED, /* MII_SEL, */
1752 CORE_NOT_SELECTED, /* RMII_SEL, */
1753 CORE_NOT_SELECTED, /* SMII_SEL, */
1754 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
1755 CORE_NOT_SELECTED, /* UIC_0_3 */
1756 CORE_NOT_SELECTED, /* USB1_HOST */
1757 CORE_NOT_SELECTED /* PCI_PATCH */
1760 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
1762 /* Table Default Initialisation + FPGA Access */
1763 init_default_gpio(gpio_tab);
1764 set_chip_gpio_configuration(GPIO0, gpio_tab);
1765 set_chip_gpio_configuration(GPIO1, gpio_tab);
1768 force_bup_core_selection(ppc440ep_core_selection, &config_val);
1769 #if 0 /* test-only */
1770 /* If we are running PIBS 1, force known configuration */
1771 update_core_selection_table(ppc440ep_core_selection, &config_val);
1774 /*----------------------------------------------------------------------------+
1775 | SDR + ios table update + fpga initialization
1776 +----------------------------------------------------------------------------*/
1777 unsigned long sdr0_pfc1 = 0;
1778 unsigned long sdr0_usb0 = 0;
1779 unsigned long sdr0_mfr = 0;
1781 /* PCI Always selected */
1784 if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1786 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1787 iic1_selection_in_fpga();
1791 if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1793 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1794 scp_selection_in_fpga();
1797 /* UIC 0:3 Selection */
1798 if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1800 update_uic_0_3_irq_ios(gpio_tab);
1801 dma_a_b_unselect_in_fpga();
1804 /* UIC 4:9 Selection */
1805 if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1807 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
1808 update_uic_4_9_irq_ios(gpio_tab);
1811 /* DMA AB Selection */
1812 if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1814 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
1815 update_dma_a_b_ios(gpio_tab);
1816 dma_a_b_selection_in_fpga();
1819 /* DMA CD Selection */
1820 if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1822 update_dma_c_d_ios(gpio_tab);
1823 dma_c_d_selection_in_fpga();
1826 /* EBC Master Selection */
1827 if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1829 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1830 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1831 update_ebc_master_ios(gpio_tab);
1834 /* PCI Patch Enable */
1835 if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1837 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1838 update_pci_patch_ios(gpio_tab);
1841 /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1842 if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1844 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1845 printf("Invalid configuration => USB2 Host selected\n");
1848 /*usb2_host_selection_in_fpga(); */
1851 /* USB2.0 Device Selection */
1852 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1854 update_usb2_device_ios(gpio_tab);
1855 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1856 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1858 mfsdr(SDR0_USB0, sdr0_usb0);
1859 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1860 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
1861 mtsdr(SDR0_USB0, sdr0_usb0);
1863 usb2_device_selection_in_fpga();
1866 /* USB1.1 Device Selection */
1867 if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1869 mfsdr(SDR0_USB0, sdr0_usb0);
1870 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1871 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
1872 mtsdr(SDR0_USB0, sdr0_usb0);
1875 /* USB1.1 Host Selection */
1876 if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1878 mfsdr(SDR0_USB0, sdr0_usb0);
1879 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1880 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
1881 mtsdr(SDR0_USB0, sdr0_usb0);
1884 /* NAND Flash Selection */
1885 if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
1887 update_ndfc_ios(gpio_tab);
1889 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
1890 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
1891 SDR0_CUST0_NDFC_ENABLE |
1892 SDR0_CUST0_NDFC_BW_8_BIT |
1893 SDR0_CUST0_NDFC_ARE_MASK |
1894 SDR0_CUST0_CHIPSELGAT_EN1 |
1895 SDR0_CUST0_CHIPSELGAT_EN2);
1897 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
1898 SDR0_CUST0_NDFC_ENABLE |
1899 SDR0_CUST0_NDFC_BW_8_BIT |
1900 SDR0_CUST0_NDFC_ARE_MASK |
1901 SDR0_CUST0_CHIPSELGAT_EN0 |
1902 SDR0_CUST0_CHIPSELGAT_EN2);
1905 ndfc_selection_in_fpga();
1909 /* Set Mux on EMAC */
1910 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL);
1914 if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
1916 update_zii_ios(gpio_tab);
1917 mfsdr(SDR0_MFR, sdr0_mfr);
1918 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
1919 mtsdr(SDR0_MFR, sdr0_mfr);
1921 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
1924 /* RMII Selection */
1925 if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
1927 update_zii_ios(gpio_tab);
1928 mfsdr(SDR0_MFR, sdr0_mfr);
1929 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
1930 mtsdr(SDR0_MFR, sdr0_mfr);
1932 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
1935 /* SMII Selection */
1936 if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
1938 update_zii_ios(gpio_tab);
1939 mfsdr(SDR0_MFR, sdr0_mfr);
1940 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
1941 mtsdr(SDR0_MFR, sdr0_mfr);
1943 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
1946 /* UART Selection */
1947 uart_configuration = get_uart_configuration();
1948 switch (uart_configuration)
1950 case L1: /* L1 Selection */
1951 /* UART0 8 pins Only */
1952 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
1953 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
1954 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
1956 case L2: /* L2 Selection */
1957 /* UART0 and UART1 4 pins */
1958 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1959 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1960 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1962 case L3: /* L3 Selection */
1963 /* UART0 4 pins, UART1 and UART2 2 pins */
1964 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1965 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1966 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1968 case L4: /* L4 Selection */
1969 /* UART0, UART1, UART2 and UART3 2 pins */
1970 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
1971 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1972 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1975 update_uart_ios(uart_configuration, gpio_tab);
1977 /* UART Selection in all cases */
1978 uart_selection_in_fpga(uart_configuration);
1980 /* Packet Reject Function Available */
1981 if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
1983 /* Set UPR Bit in SDR0_PFC1 Register */
1984 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
1987 /* Packet Reject Function Enable */
1988 if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
1990 mfsdr(SDR0_MFR, sdr0_mfr);
1991 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
1992 mtsdr(SDR0_MFR, sdr0_mfr);
1995 /* Perform effective access to hardware */
1996 mtsdr(SDR0_PFC1, sdr0_pfc1);
1997 set_chip_gpio_configuration(GPIO0, gpio_tab);
1998 set_chip_gpio_configuration(GPIO1, gpio_tab);
2000 /* USB2.0 Device Reset must be done after GPIO setting */
2001 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
2002 usb2_device_reset_through_fpga();