3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <spd_sdram.h>
30 void ext_bus_cntlr_init(void);
31 void configure_ppc440ep_pins(void);
32 int is_nand_selected(void);
34 unsigned char cfg_simulate_spd_eeprom[128];
36 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
38 { /* GPIO Alternate1 Alternate2 Alternate3 */
41 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
42 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
43 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
44 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
45 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
46 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
47 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
48 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
49 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
50 { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
51 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
52 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
53 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
54 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
55 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
56 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
57 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
58 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
59 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
60 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
61 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
62 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
63 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
64 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
65 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
66 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
67 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
68 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
69 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
70 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
71 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
72 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
76 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
77 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
78 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
79 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
80 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
81 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
82 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
83 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
84 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
85 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
86 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
87 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
88 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
89 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
90 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
91 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
92 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
93 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
94 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
95 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
96 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
97 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
98 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
99 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
100 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
101 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
102 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
103 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
104 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
105 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
106 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
107 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
112 /*----------------------------------------------------------------------------+
113 | EBC Devices Characteristics
114 | Peripheral Bank Access Parameters - EBC0_BnAP
115 | Peripheral Bank Configuration Register - EBC0_BnCR
116 +----------------------------------------------------------------------------*/
118 #define EBC0_BNAP_SMALL_FLASH \
119 EBC0_BNAP_BME_DISABLED | \
120 EBC0_BNAP_TWT_ENCODE(6) | \
121 EBC0_BNAP_CSN_ENCODE(0) | \
122 EBC0_BNAP_OEN_ENCODE(1) | \
123 EBC0_BNAP_WBN_ENCODE(1) | \
124 EBC0_BNAP_WBF_ENCODE(3) | \
125 EBC0_BNAP_TH_ENCODE(1) | \
126 EBC0_BNAP_RE_ENABLED | \
127 EBC0_BNAP_SOR_DELAYED | \
128 EBC0_BNAP_BEM_WRITEONLY | \
129 EBC0_BNAP_PEN_DISABLED
131 #define EBC0_BNCR_SMALL_FLASH_CS0 \
132 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
137 #define EBC0_BNCR_SMALL_FLASH_CS4 \
138 EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
143 /* Large Flash or SRAM */
144 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
145 EBC0_BNAP_BME_DISABLED | \
146 EBC0_BNAP_TWT_ENCODE(8) | \
147 EBC0_BNAP_CSN_ENCODE(0) | \
148 EBC0_BNAP_OEN_ENCODE(1) | \
149 EBC0_BNAP_WBN_ENCODE(1) | \
150 EBC0_BNAP_WBF_ENCODE(1) | \
151 EBC0_BNAP_TH_ENCODE(2) | \
152 EBC0_BNAP_SOR_DELAYED | \
154 EBC0_BNAP_PEN_DISABLED
156 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
157 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
163 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
164 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
170 #define EBC0_BNAP_NVRAM_FPGA \
171 EBC0_BNAP_BME_DISABLED | \
172 EBC0_BNAP_TWT_ENCODE(9) | \
173 EBC0_BNAP_CSN_ENCODE(0) | \
174 EBC0_BNAP_OEN_ENCODE(1) | \
175 EBC0_BNAP_WBN_ENCODE(1) | \
176 EBC0_BNAP_WBF_ENCODE(0) | \
177 EBC0_BNAP_TH_ENCODE(2) | \
178 EBC0_BNAP_RE_ENABLED | \
179 EBC0_BNAP_SOR_DELAYED | \
180 EBC0_BNAP_BEM_WRITEONLY | \
181 EBC0_BNAP_PEN_DISABLED
183 #define EBC0_BNCR_NVRAM_FPGA_CS5 \
184 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
190 #define EBC0_BNAP_NAND_FLASH \
191 EBC0_BNAP_BME_DISABLED | \
192 EBC0_BNAP_TWT_ENCODE(3) | \
193 EBC0_BNAP_CSN_ENCODE(0) | \
194 EBC0_BNAP_OEN_ENCODE(0) | \
195 EBC0_BNAP_WBN_ENCODE(0) | \
196 EBC0_BNAP_WBF_ENCODE(0) | \
197 EBC0_BNAP_TH_ENCODE(1) | \
198 EBC0_BNAP_RE_ENABLED | \
199 EBC0_BNAP_SOR_NOT_DELAYED | \
201 EBC0_BNAP_PEN_DISABLED
204 #define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
207 #define EBC0_BNCR_NAND_FLASH_CS1 \
208 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
213 #define EBC0_BNCR_NAND_FLASH_CS2 \
214 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
220 #define EBC0_BNCR_NAND_FLASH_CS3 \
221 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
226 int board_early_init_f(void)
228 ext_bus_cntlr_init();
230 /*--------------------------------------------------------------------
231 * Setup the interrupt controller polarities, triggers, etc.
232 *-------------------------------------------------------------------*/
233 mtdcr(uic0sr, 0xffffffff); /* clear all */
234 mtdcr(uic0er, 0x00000000); /* disable all */
235 mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
236 mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
237 mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
238 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
239 mtdcr(uic0sr, 0xffffffff); /* clear all */
241 mtdcr(uic1sr, 0xffffffff); /* clear all */
242 mtdcr(uic1er, 0x00000000); /* disable all */
243 mtdcr(uic1cr, 0x00000000); /* all non-critical */
244 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
245 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
246 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
247 mtdcr(uic1sr, 0xffffffff); /* clear all */
249 /*--------------------------------------------------------------------
250 * Setup the GPIO pins
251 *-------------------------------------------------------------------*/
252 out32(GPIO0_OSRL, 0x00000400);
253 out32(GPIO0_OSRH, 0x00000000);
254 out32(GPIO0_TSRL, 0x00000400);
255 out32(GPIO0_TSRH, 0x00000000);
256 out32(GPIO0_ISR1L, 0x00000000);
257 out32(GPIO0_ISR1H, 0x00000000);
258 out32(GPIO0_ISR2L, 0x00000000);
259 out32(GPIO0_ISR2H, 0x00000000);
260 out32(GPIO0_ISR3L, 0x00000000);
261 out32(GPIO0_ISR3H, 0x00000000);
263 out32(GPIO1_OSRL, 0x0C380000);
264 out32(GPIO1_OSRH, 0x00000000);
265 out32(GPIO1_TSRL, 0x0C380000);
266 out32(GPIO1_TSRH, 0x00000000);
267 out32(GPIO1_ISR1L, 0x0FC30000);
268 out32(GPIO1_ISR1H, 0x00000000);
269 out32(GPIO1_ISR2L, 0x0C010000);
270 out32(GPIO1_ISR2H, 0x00000000);
271 out32(GPIO1_ISR3L, 0x01400000);
272 out32(GPIO1_ISR3H, 0x00000000);
274 configure_ppc440ep_pins();
279 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
280 #include <linux/mtd/nand.h>
281 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
283 /*----------------------------------------------------------------------------+
286 | This routine will abort previous cmd
287 +----------------------------------------------------------------------------*/
288 int nand_reset(ulong addr)
292 out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
293 out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
295 while ((stat != 0xc0) && (wait != 0xffff)) {
296 stat = in8(addr + NAND_DATA_REG);
303 printf("NAND Reset timeout.\n");
308 void board_nand_set_device(int cs, ulong addr)
310 /* Set NandFlash Core Configuration Register */
311 out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
318 * K9F1208U0A : 4 addr cyc, 1 col + 3 Row
319 * Set NDF1CR - Enable External CS1 in NAND FLASH controller
321 out32(addr + NAND_CR1_REG, 0x80002222);
328 * K9K2G0B : 5 addr cyc, 2 col + 3 Row
329 * Set NDF2CR : Enable External CS2 in NAND FLASH controller
331 out32(addr + NAND_CR2_REG, 0xC0007777);
335 /* Perform Reset Command */
336 if (nand_reset(addr) != 0)
342 board_nand_set_device(1, CFG_NAND_ADDR);
344 nand_probe(CFG_NAND_ADDR);
345 if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
346 print_size(nand_dev_desc[0].totlen, "\n");
349 #if 0 /* NAND1 not supported yet */
350 board_nand_set_device(2, CFG_NAND2_ADDR);
352 nand_probe(CFG_NAND2_ADDR);
353 if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
354 print_size(nand_dev_desc[0].totlen, "\n");
358 #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
362 char *s = getenv("serial#");
364 printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
374 /*************************************************************************
376 * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
378 * Fixed memory is composed of :
379 * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
380 * 13 row add bits, 10 column add bits (but 12 row used only).
381 * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
382 * 12 row add bits, 10 column add bits.
383 * Prepare a subset (only the used ones) of SPD data
385 * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
386 * the corresponding bank is divided by 2 due to number of Row addresses
387 * 12 in the ECC module
389 * Assumes: 64 MB, ECC, non-registered
392 ************************************************************************/
393 static void init_spd_array(void)
395 cfg_simulate_spd_eeprom[8] = 0x04; /* 2.5 Volt */
396 cfg_simulate_spd_eeprom[2] = 0x07; /* DDR ram */
398 #ifdef CONFIG_DDR_ECC
399 cfg_simulate_spd_eeprom[11] = 0x02; /* ECC ON : 02 OFF : 00 */
400 cfg_simulate_spd_eeprom[31] = 0x08; /* bankSizeID: 32MB */
401 cfg_simulate_spd_eeprom[3] = 0x0C; /* num Row Addr: 12 */
403 cfg_simulate_spd_eeprom[11] = 0x00; /* ECC ON : 02 OFF : 00 */
404 cfg_simulate_spd_eeprom[31] = 0x10; /* bankSizeID: 64MB */
405 cfg_simulate_spd_eeprom[3] = 0x0D; /* num Row Addr: 13 */
408 cfg_simulate_spd_eeprom[4] = 0x09; /* numColAddr: 9 */
409 cfg_simulate_spd_eeprom[5] = 0x01; /* numBanks: 1 */
410 cfg_simulate_spd_eeprom[0] = 0x80; /* number of SPD bytes used: 128 */
411 cfg_simulate_spd_eeprom[1] = 0x08; /* total number bytes in SPD device = 256 */
412 cfg_simulate_spd_eeprom[21] = 0x00; /* not registered: 0 registered : 0x02*/
413 cfg_simulate_spd_eeprom[6] = 0x20; /* Module data width: 32 bits */
414 cfg_simulate_spd_eeprom[7] = 0x00; /* Module data width continued: +0 */
415 cfg_simulate_spd_eeprom[15] = 0x01; /* wcsbc = 1 */
416 cfg_simulate_spd_eeprom[27] = 0x50; /* tRpNs = 20 ns */
417 cfg_simulate_spd_eeprom[29] = 0x50; /* tRcdNs = 20 ns */
419 cfg_simulate_spd_eeprom[30] = 45; /* tRasNs */
421 cfg_simulate_spd_eeprom[18] = 0x0C; /* casBit (2,2.5) */
423 cfg_simulate_spd_eeprom[9] = 0x75; /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
424 cfg_simulate_spd_eeprom[23] = 0xA0; /* SDRAM Cycle Time (cas latency 2) = 10 ns */
425 cfg_simulate_spd_eeprom[25] = 0x00; /* SDRAM Cycle Time (cas latency 1.5) = N.A */
426 cfg_simulate_spd_eeprom[12] = 0x82; /* refresh Rate Type: Normal (15.625us) + Self refresh */
429 long int initdram (int board_type)
434 * First write simulated values in eeprom array for onboard bank 0
438 dram_size = spd_sdram (0);
443 #if defined(CFG_DRAM_TEST)
446 unsigned long *mem = (unsigned long *)0;
447 const unsigned long kend = (1024 / sizeof(unsigned long));
452 for (k = 0; k < CFG_KBYTES_SDRAM;
453 ++k, mem += (1024 / sizeof(unsigned long))) {
454 if ((k & 1023) == 0) {
455 printf("%3d MB\r", k / 1024);
458 memset(mem, 0xaaaaaaaa, 1024);
459 for (n = 0; n < kend; ++n) {
460 if (mem[n] != 0xaaaaaaaa) {
461 printf("SDRAM test fails at: %08x\n",
467 memset(mem, 0x55555555, 1024);
468 for (n = 0; n < kend; ++n) {
469 if (mem[n] != 0x55555555) {
470 printf("SDRAM test fails at: %08x\n",
476 printf("SDRAM test passes\n");
481 /*************************************************************************
484 * This routine is called just prior to registering the hose and gives
485 * the board the opportunity to check things. Returning a value of zero
486 * indicates that things are bad & PCI initialization should be aborted.
488 * Different boards may wish to customize the pci controller structure
489 * (add regions, override default access routines, etc) or perform
490 * certain pre-initialization actions.
492 ************************************************************************/
493 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
494 int pci_pre_init(struct pci_controller *hose)
499 /*--------------------------------------------------------------------------+
500 * Bamboo is always configured as the host & requires the
501 * PCI arbiter to be enabled.
502 *--------------------------------------------------------------------------*/
503 mfsdr(sdr_sdstp1, strap);
504 if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
505 printf("PCI: SDR0_STRP1[PAE] not set.\n");
506 printf("PCI: Configuration aborted.\n");
510 /*-------------------------------------------------------------------------+
511 | Set priority for all PLB3 devices to 0.
512 | Set PLB3 arbiter to fair mode.
513 +-------------------------------------------------------------------------*/
514 mfsdr(sdr_amp1, addr);
515 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
516 addr = mfdcr(plb3_acr);
517 mtdcr(plb3_acr, addr | 0x80000000);
519 /*-------------------------------------------------------------------------+
520 | Set priority for all PLB4 devices to 0.
521 +-------------------------------------------------------------------------*/
522 mfsdr(sdr_amp0, addr);
523 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
524 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
525 mtdcr(plb4_acr, addr);
527 /*-------------------------------------------------------------------------+
528 | Set Nebula PLB4 arbiter to fair mode.
529 +-------------------------------------------------------------------------*/
531 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
532 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
533 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
534 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
535 mtdcr(plb0_acr, addr);
538 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
539 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
540 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
541 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
542 mtdcr(plb1_acr, addr);
546 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
548 /*************************************************************************
551 * The bootstrap configuration provides default settings for the pci
552 * inbound map (PIM). But the bootstrap config choices are limited and
553 * may not be sufficient for a given board.
555 ************************************************************************/
556 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
557 void pci_target_init(struct pci_controller *hose)
559 /*--------------------------------------------------------------------------+
560 * Set up Direct MMIO registers
561 *--------------------------------------------------------------------------*/
562 /*--------------------------------------------------------------------------+
563 | PowerPC440 EP PCI Master configuration.
564 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
565 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
566 | Use byte reversed out routines to handle endianess.
567 | Make this region non-prefetchable.
568 +--------------------------------------------------------------------------*/
569 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
570 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
571 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
572 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
573 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
575 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
576 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
577 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
578 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
579 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
581 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
582 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
583 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
584 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
586 /*--------------------------------------------------------------------------+
587 * Set up Configuration registers
588 *--------------------------------------------------------------------------*/
590 /* Program the board's subsystem id/vendor id */
591 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
592 CFG_PCI_SUBSYS_VENDORID);
593 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
595 /* Configure command register as bus master */
596 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
598 /* 240nS PCI clock */
599 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
601 /* No error reporting */
602 pci_write_config_word(0, PCI_ERREN, 0);
604 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
607 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
609 /*************************************************************************
612 ************************************************************************/
613 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
614 void pci_master_init(struct pci_controller *hose)
616 unsigned short temp_short;
618 /*--------------------------------------------------------------------------+
619 | Write the PowerPC440 EP PCI Configuration regs.
620 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
621 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
622 +--------------------------------------------------------------------------*/
623 pci_read_config_word(0, PCI_COMMAND, &temp_short);
624 pci_write_config_word(0, PCI_COMMAND,
625 temp_short | PCI_COMMAND_MASTER |
628 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
630 /*************************************************************************
633 * This routine is called to determine if a pci scan should be
634 * performed. With various hardware environments (especially cPCI and
635 * PPMC) it's insufficient to depend on the state of the arbiter enable
636 * bit in the strap register, or generic host/adapter assumptions.
638 * Rather than hard-code a bad assumption in the general 440 code, the
639 * 440 pci code requires the board to decide at runtime.
641 * Return 0 for adapter mode, non-zero for host (monarch) mode.
644 ************************************************************************/
645 #if defined(CONFIG_PCI)
646 int is_pci_host(struct pci_controller *hose)
648 /* Bamboo is always configured as host. */
651 #endif /* defined(CONFIG_PCI) */
653 /*----------------------------------------------------------------------------+
654 | is_powerpc440ep_pass1.
655 +----------------------------------------------------------------------------*/
656 int is_powerpc440ep_pass1(void)
662 if (pvr == PVR_POWERPC_440EP_PASS1)
664 else if (pvr == PVR_POWERPC_440EP_PASS2)
667 printf("brdutil error 3\n");
675 /*----------------------------------------------------------------------------+
677 +----------------------------------------------------------------------------*/
678 int is_nand_selected(void)
680 #ifdef CONFIG_BAMBOO_NAND
687 /*----------------------------------------------------------------------------+
688 | config_on_ebc_cs4_is_small_flash => from EPLD
689 +----------------------------------------------------------------------------*/
690 unsigned char config_on_ebc_cs4_is_small_flash(void)
692 /* Not implemented yet => returns constant value */
696 /*----------------------------------------------------------------------------+
697 | Ext_bus_cntlr_init.
698 | Initialize the external bus controller
699 +----------------------------------------------------------------------------*/
700 void ext_bus_cntlr_init(void)
702 unsigned long sdr0_pstrp0, sdr0_sdstp1;
703 unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
704 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
705 unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
706 unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
707 unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
708 unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
709 unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
712 /*-------------------------------------------------------------------------+
714 | PART 1 : Initialize EBC Bank 5
715 | ==============================
716 | Bank5 is always associated to the NVRAM/EPLD.
717 | It has to be initialized prior to other banks settings computation since
718 | some board registers values may be needed
720 +-------------------------------------------------------------------------*/
722 mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
723 mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
725 /*-------------------------------------------------------------------------+
727 | PART 2 : Determine which boot device was selected
728 | =========================================
730 | Read Pin Strap Register in PPC440EP
731 | In case of boot from IIC, read Serial Device Strap Register1
733 | Result can either be :
734 | - Boot from EBC 8bits => SMALL FLASH
735 | - Boot from EBC 16bits => Large Flash or SRAM
736 | - Boot from NAND Flash
739 +-------------------------------------------------------------------------*/
740 /* Read Pin Strap Register in PPC440EP */
741 mfsdr(sdr_pstrp0, sdr0_pstrp0);
742 bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
744 /*-------------------------------------------------------------------------+
746 +-------------------------------------------------------------------------*/
747 if (is_powerpc440ep_pass1() == TRUE) {
748 switch(bootstrap_settings) {
749 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
750 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
751 /* Boot from Small Flash */
752 computed_boot_device = BOOT_FROM_SMALL_FLASH;
754 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
755 /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
757 computed_boot_device = BOOT_FROM_PCI;
760 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
761 /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
762 /* Boot from Nand Flash */
763 computed_boot_device = BOOT_FROM_NAND_FLASH0;
766 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
767 /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
768 /* Boot from Small Flash */
769 computed_boot_device = BOOT_FROM_SMALL_FLASH;
772 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
773 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
774 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
775 /* Read Serial Device Strap Register1 in PPC440EP */
776 mfsdr(sdr_sdstp1, sdr0_sdstp1);
777 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
778 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
780 switch(boot_selection) {
781 case SDR0_SDSTP1_BOOT_SEL_EBC:
782 switch(ebc_boot_size) {
783 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
784 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
786 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
787 computed_boot_device = BOOT_FROM_SMALL_FLASH;
792 case SDR0_SDSTP1_BOOT_SEL_PCI:
793 computed_boot_device = BOOT_FROM_PCI;
796 case SDR0_SDSTP1_BOOT_SEL_NDFC:
797 computed_boot_device = BOOT_FROM_NAND_FLASH0;
804 /*-------------------------------------------------------------------------+
806 +-------------------------------------------------------------------------*/
808 switch(bootstrap_settings) {
809 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
810 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
811 /* Boot from Small Flash */
812 computed_boot_device = BOOT_FROM_SMALL_FLASH;
814 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
815 /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
817 computed_boot_device = BOOT_FROM_PCI;
820 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
821 /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
822 /* Boot from Nand Flash */
823 computed_boot_device = BOOT_FROM_NAND_FLASH0;
826 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
827 /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
828 /* Boot from Large Flash or SRAM */
829 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
832 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
833 /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
834 /* Boot from Large Flash or SRAM */
835 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
838 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
839 /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
841 computed_boot_device = BOOT_FROM_PCI;
844 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
845 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
846 /* Default Strap Settings 5-7 */
847 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
848 /* Read Serial Device Strap Register1 in PPC440EP */
849 mfsdr(sdr_sdstp1, sdr0_sdstp1);
850 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
851 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
853 switch(boot_selection) {
854 case SDR0_SDSTP1_BOOT_SEL_EBC:
855 switch(ebc_boot_size) {
856 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
857 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
859 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
860 computed_boot_device = BOOT_FROM_SMALL_FLASH;
865 case SDR0_SDSTP1_BOOT_SEL_PCI:
866 computed_boot_device = BOOT_FROM_PCI;
869 case SDR0_SDSTP1_BOOT_SEL_NDFC:
870 computed_boot_device = BOOT_FROM_NAND_FLASH0;
877 /*-------------------------------------------------------------------------+
879 | PART 3 : Compute EBC settings depending on selected boot device
880 | ====== ======================================================
882 | Resulting EBC init will be among following configurations :
884 | - Boot from EBC 8bits => boot from SMALL FLASH selected
885 | EBC-CS0 = Small Flash
886 | EBC-CS1,2,3 = NAND Flash or
887 | Exp.Slot depending on Soft Config
888 | EBC-CS4 = SRAM/Large Flash or
889 | Large Flash/SRAM depending on jumpers
890 | EBC-CS5 = NVRAM / EPLD
892 | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
893 | EBC-CS0 = SRAM/Large Flash or
894 | Large Flash/SRAM depending on jumpers
895 | EBC-CS1,2,3 = NAND Flash or
896 | Exp.Slot depending on Software Configuration
897 | EBC-CS4 = Small Flash
898 | EBC-CS5 = NVRAM / EPLD
900 | - Boot from NAND Flash
901 | EBC-CS0 = NAND Flash0
902 | EBC-CS1,2,3 = NAND Flash1
903 | EBC-CS4 = SRAM/Large Flash or
904 | Large Flash/SRAM depending on jumpers
905 | EBC-CS5 = NVRAM / EPLD
909 | EBC-CS1,2,3 = NAND Flash or
910 | Exp.Slot depending on Software Configuration
911 | EBC-CS4 = SRAM/Large Flash or
912 | Large Flash/SRAM or
913 | Small Flash depending on jumpers
914 | EBC-CS5 = NVRAM / EPLD
916 +-------------------------------------------------------------------------*/
918 switch(computed_boot_device) {
919 /*------------------------------------------------------------------------- */
920 case BOOT_FROM_SMALL_FLASH:
921 /*------------------------------------------------------------------------- */
922 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
923 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
924 if ((is_nand_selected()) == TRUE) {
926 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
927 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
928 ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
929 ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
930 ebc0_cs3_bnap_value = 0;
931 ebc0_cs3_bncr_value = 0;
934 ebc0_cs1_bnap_value = 0;
935 ebc0_cs1_bncr_value = 0;
936 ebc0_cs2_bnap_value = 0;
937 ebc0_cs2_bncr_value = 0;
938 ebc0_cs3_bnap_value = 0;
939 ebc0_cs3_bncr_value = 0;
941 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
942 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
946 /*------------------------------------------------------------------------- */
947 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
948 /*------------------------------------------------------------------------- */
949 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
950 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
951 if ((is_nand_selected()) == TRUE) {
953 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
954 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
955 ebc0_cs2_bnap_value = 0;
956 ebc0_cs2_bncr_value = 0;
957 ebc0_cs3_bnap_value = 0;
958 ebc0_cs3_bncr_value = 0;
961 ebc0_cs1_bnap_value = 0;
962 ebc0_cs1_bncr_value = 0;
963 ebc0_cs2_bnap_value = 0;
964 ebc0_cs2_bncr_value = 0;
965 ebc0_cs3_bnap_value = 0;
966 ebc0_cs3_bncr_value = 0;
968 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
969 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
973 /*------------------------------------------------------------------------- */
974 case BOOT_FROM_NAND_FLASH0:
975 /*------------------------------------------------------------------------- */
976 ebc0_cs0_bnap_value = 0;
977 ebc0_cs0_bncr_value = 0;
979 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
980 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
981 ebc0_cs2_bnap_value = 0;
982 ebc0_cs2_bncr_value = 0;
983 ebc0_cs3_bnap_value = 0;
984 ebc0_cs3_bncr_value = 0;
986 /* Large Flash or SRAM */
987 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
988 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
992 /*------------------------------------------------------------------------- */
994 /*------------------------------------------------------------------------- */
995 ebc0_cs0_bnap_value = 0;
996 ebc0_cs0_bncr_value = 0;
998 if ((is_nand_selected()) == TRUE) {
1000 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
1001 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
1002 ebc0_cs2_bnap_value = 0;
1003 ebc0_cs2_bncr_value = 0;
1004 ebc0_cs3_bnap_value = 0;
1005 ebc0_cs3_bncr_value = 0;
1007 /* Expansion Slot */
1008 ebc0_cs1_bnap_value = 0;
1009 ebc0_cs1_bncr_value = 0;
1010 ebc0_cs2_bnap_value = 0;
1011 ebc0_cs2_bncr_value = 0;
1012 ebc0_cs3_bnap_value = 0;
1013 ebc0_cs3_bncr_value = 0;
1016 if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
1018 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
1019 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
1021 /* Large Flash or SRAM */
1022 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
1023 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
1028 /*------------------------------------------------------------------------- */
1029 case BOOT_DEVICE_UNKNOWN:
1030 /*------------------------------------------------------------------------- */
1037 /*-------------------------------------------------------------------------+
1038 | Initialize EBC CONFIG
1039 +-------------------------------------------------------------------------*/
1040 mtdcr(ebccfga, xbcfg);
1041 mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
1042 EBC0_CFG_PTD_ENABLED |
1043 EBC0_CFG_RTC_2048PERCLK |
1046 EBC0_CFG_CSTC_DRIVEN |
1047 EBC0_CFG_BPF_ONEDW |
1049 EBC0_CFG_PME_DISABLED |
1050 EBC0_CFG_PMT_ENCODE(0) );
1052 /*-------------------------------------------------------------------------+
1053 | Initialize EBC Bank 0-4
1054 +-------------------------------------------------------------------------*/
1056 mtebc(pb0ap, ebc0_cs0_bnap_value);
1057 mtebc(pb0cr, ebc0_cs0_bncr_value);
1059 mtebc(pb1ap, ebc0_cs1_bnap_value);
1060 mtebc(pb1cr, ebc0_cs1_bncr_value);
1062 mtebc(pb2ap, ebc0_cs2_bnap_value);
1063 mtebc(pb2cr, ebc0_cs2_bncr_value);
1065 mtebc(pb3ap, ebc0_cs3_bnap_value);
1066 mtebc(pb3cr, ebc0_cs3_bncr_value);
1068 mtebc(pb4ap, ebc0_cs4_bnap_value);
1069 mtebc(pb4cr, ebc0_cs4_bncr_value);
1075 /*----------------------------------------------------------------------------+
1076 | get_uart_configuration.
1077 +----------------------------------------------------------------------------*/
1078 uart_config_nb_t get_uart_configuration(void)
1083 /*----------------------------------------------------------------------------+
1084 | set_phy_configuration_through_fpga => to EPLD
1085 +----------------------------------------------------------------------------*/
1086 void set_phy_configuration_through_fpga(zmii_config_t config)
1089 unsigned long fpga_selection_reg;
1091 fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
1095 case ZMII_CONFIGURATION_IS_MII:
1096 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
1098 case ZMII_CONFIGURATION_IS_RMII:
1099 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
1101 case ZMII_CONFIGURATION_IS_SMII:
1102 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
1104 case ZMII_CONFIGURATION_UNKNOWN:
1108 out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
1112 /*----------------------------------------------------------------------------+
1113 | scp_selection_in_fpga.
1114 +----------------------------------------------------------------------------*/
1115 void scp_selection_in_fpga(void)
1117 unsigned long fpga_selection_2_reg;
1119 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1120 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
1121 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1124 /*----------------------------------------------------------------------------+
1125 | iic1_selection_in_fpga.
1126 +----------------------------------------------------------------------------*/
1127 void iic1_selection_in_fpga(void)
1129 unsigned long fpga_selection_2_reg;
1131 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1132 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
1133 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1136 /*----------------------------------------------------------------------------+
1137 | dma_a_b_selection_in_fpga.
1138 +----------------------------------------------------------------------------*/
1139 void dma_a_b_selection_in_fpga(void)
1141 unsigned long fpga_selection_2_reg;
1143 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
1144 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1147 /*----------------------------------------------------------------------------+
1148 | dma_a_b_unselect_in_fpga.
1149 +----------------------------------------------------------------------------*/
1150 void dma_a_b_unselect_in_fpga(void)
1152 unsigned long fpga_selection_2_reg;
1154 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
1155 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1158 /*----------------------------------------------------------------------------+
1159 | dma_c_d_selection_in_fpga.
1160 +----------------------------------------------------------------------------*/
1161 void dma_c_d_selection_in_fpga(void)
1163 unsigned long fpga_selection_2_reg;
1165 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
1166 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1169 /*----------------------------------------------------------------------------+
1170 | dma_c_d_unselect_in_fpga.
1171 +----------------------------------------------------------------------------*/
1172 void dma_c_d_unselect_in_fpga(void)
1174 unsigned long fpga_selection_2_reg;
1176 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
1177 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1180 /*----------------------------------------------------------------------------+
1181 | usb2_device_selection_in_fpga.
1182 +----------------------------------------------------------------------------*/
1183 void usb2_device_selection_in_fpga(void)
1185 unsigned long fpga_selection_1_reg;
1187 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
1188 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1191 /*----------------------------------------------------------------------------+
1192 | usb2_device_reset_through_fpga.
1193 +----------------------------------------------------------------------------*/
1194 void usb2_device_reset_through_fpga(void)
1196 /* Perform soft Reset pulse */
1197 unsigned long fpga_reset_reg;
1200 fpga_reset_reg = in8(FPGA_RESET_REG);
1201 out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1202 for (i=0; i<500; i++)
1204 out8(FPGA_RESET_REG,fpga_reset_reg);
1207 /*----------------------------------------------------------------------------+
1208 | usb2_host_selection_in_fpga.
1209 +----------------------------------------------------------------------------*/
1210 void usb2_host_selection_in_fpga(void)
1212 unsigned long fpga_selection_1_reg;
1214 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1215 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1218 /*----------------------------------------------------------------------------+
1219 | ndfc_selection_in_fpga.
1220 +----------------------------------------------------------------------------*/
1221 void ndfc_selection_in_fpga(void)
1223 unsigned long fpga_selection_1_reg;
1225 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1226 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
1227 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
1228 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1231 /*----------------------------------------------------------------------------+
1232 | uart_selection_in_fpga.
1233 +----------------------------------------------------------------------------*/
1234 void uart_selection_in_fpga(uart_config_nb_t uart_config)
1237 unsigned char fpga_selection_3_reg;
1239 /* Read FPGA Reagister */
1240 fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1242 switch (uart_config)
1245 /* ----------------------------------------------------------------------- */
1246 /* L1 configuration: UART0 = 8 pins */
1247 /* ----------------------------------------------------------------------- */
1248 /* Configure FPGA */
1249 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1250 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
1251 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1256 /* ----------------------------------------------------------------------- */
1257 /* L2 configuration: UART0 = 4 pins */
1258 /* UART1 = 4 pins */
1259 /* ----------------------------------------------------------------------- */
1260 /* Configure FPGA */
1261 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1262 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
1263 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1268 /* ----------------------------------------------------------------------- */
1269 /* L3 configuration: UART0 = 4 pins */
1270 /* UART1 = 2 pins */
1271 /* UART2 = 2 pins */
1272 /* ----------------------------------------------------------------------- */
1273 /* Configure FPGA */
1274 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1275 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
1276 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1280 /* Configure FPGA */
1281 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1282 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
1283 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1288 /* Unsupported UART configuration number */
1297 /*----------------------------------------------------------------------------+
1299 +----------------------------------------------------------------------------*/
1300 void init_default_gpio(void)
1305 for(i=0; i<GPIO_MAX; i++)
1307 gpio_tab[GPIO0][i].add = GPIO0_BASE;
1308 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1309 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1313 for(i=0; i<GPIO_MAX; i++)
1315 gpio_tab[GPIO1][i].add = GPIO1_BASE;
1316 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1317 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1320 /* EBC_CS_N(5) - GPIO0_10 */
1321 gpio_tab[GPIO0][10].in_out = GPIO_OUT;
1322 gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
1324 /* EBC_CS_N(4) - GPIO0_9 */
1325 gpio_tab[GPIO0][9].in_out = GPIO_OUT;
1326 gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
1329 /*----------------------------------------------------------------------------+
1331 +------------------------------------------------------------------------------
1333 | Set UART Configuration in PowerPC440EP
1335 | +---------------------------------------------------------------------+
1336 | | Configuartion | Connector | Nb of pins | Pins | Associated |
1337 | | Number | Port Name | available | naming | CORE |
1338 | +-----------------+---------------+------------+--------+-------------+
1339 | | L1 | Port_A | 8 | UART | UART core 0 |
1340 | +-----------------+---------------+------------+--------+-------------+
1341 | | L2 | Port_A | 4 | UART1 | UART core 0 |
1342 | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
1343 | +-----------------+---------------+------------+--------+-------------+
1344 | | L3 | Port_A | 4 | UART1 | UART core 0 |
1345 | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
1346 | | | Port_C | 2 | UART3 | UART core 2 |
1347 | +-----------------+---------------+------------+--------+-------------+
1348 | | | Port_A | 2 | UART1 | UART core 0 |
1349 | | L4 | Port_B | 2 | UART2 | UART core 1 |
1350 | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
1351 | | | Port_D | 2 | UART4 | UART core 3 |
1352 | +-----------------+---------------+------------+--------+-------------+
1356 | +------------------------------------------------------------------------------+
1357 | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
1358 | +---------+------------------+-----+-----------------+-----+-------------+-----+
1359 | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
1360 | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
1361 | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
1362 | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
1363 | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
1364 | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
1365 | +------------------------------------------------------------------------------+
1368 +----------------------------------------------------------------------------*/
1370 void update_uart_ios(uart_config_nb_t uart_config)
1372 switch (uart_config)
1375 /* ----------------------------------------------------------------------- */
1376 /* L1 configuration: UART0 = 8 pins */
1377 /* ----------------------------------------------------------------------- */
1378 /* Update GPIO Configuration Table */
1379 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1380 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1382 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1383 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1385 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1386 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1388 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1389 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1391 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1392 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1394 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1395 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1400 /* ----------------------------------------------------------------------- */
1401 /* L2 configuration: UART0 = 4 pins */
1402 /* UART1 = 4 pins */
1403 /* ----------------------------------------------------------------------- */
1404 /* Update GPIO Configuration Table */
1405 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1406 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1408 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1409 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1411 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1412 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1414 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1415 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1417 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1418 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1420 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1421 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1426 /* ----------------------------------------------------------------------- */
1427 /* L3 configuration: UART0 = 4 pins */
1428 /* UART1 = 2 pins */
1429 /* UART2 = 2 pins */
1430 /* ----------------------------------------------------------------------- */
1431 /* Update GPIO Configuration Table */
1432 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1433 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1435 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1436 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1438 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1439 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1441 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1442 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1444 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1445 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1447 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1448 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1453 /* ----------------------------------------------------------------------- */
1454 /* L4 configuration: UART0 = 2 pins */
1455 /* UART1 = 2 pins */
1456 /* UART2 = 2 pins */
1457 /* UART3 = 2 pins */
1458 /* ----------------------------------------------------------------------- */
1459 /* Update GPIO Configuration Table */
1460 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1461 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1463 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1464 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1466 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1467 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1469 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1470 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1472 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1473 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1475 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1476 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1481 /* Unsupported UART configuration number */
1482 printf("ERROR - Unsupported UART configuration number.\n\n");
1489 /* Set input Selection Register on Alt_Receive for UART Input Core */
1490 out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1491 out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1492 out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1495 /*----------------------------------------------------------------------------+
1496 | update_ndfc_ios(void).
1497 +----------------------------------------------------------------------------*/
1498 void update_ndfc_ios(void)
1500 /* Update GPIO Configuration Table */
1501 gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
1502 gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
1505 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
1506 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1508 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
1509 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1513 /*----------------------------------------------------------------------------+
1514 | update_zii_ios(void).
1515 +----------------------------------------------------------------------------*/
1516 void update_zii_ios(void)
1518 /* Update GPIO Configuration Table */
1519 gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
1520 gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
1522 gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
1523 gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
1525 gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
1526 gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
1528 gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
1529 gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
1531 gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
1532 gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
1534 gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
1535 gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
1537 gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
1538 gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
1540 gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
1541 gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
1543 gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
1544 gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
1546 gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
1547 gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
1549 gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
1550 gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
1552 gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
1553 gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
1555 gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
1556 gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
1558 gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
1559 gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
1563 /*----------------------------------------------------------------------------+
1564 | update_uic_0_3_irq_ios().
1565 +----------------------------------------------------------------------------*/
1566 void update_uic_0_3_irq_ios(void)
1568 gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
1569 gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1571 gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
1572 gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1574 gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
1575 gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1577 gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
1578 gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1581 /*----------------------------------------------------------------------------+
1582 | update_uic_4_9_irq_ios().
1583 +----------------------------------------------------------------------------*/
1584 void update_uic_4_9_irq_ios(void)
1586 gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
1587 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1589 gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
1590 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1592 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
1593 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1595 gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
1596 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1598 gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
1599 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1602 /*----------------------------------------------------------------------------+
1603 | update_dma_a_b_ios().
1604 +----------------------------------------------------------------------------*/
1605 void update_dma_a_b_ios(void)
1607 gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
1608 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1610 gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
1611 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1613 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
1614 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1616 gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
1617 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1619 gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
1620 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1623 /*----------------------------------------------------------------------------+
1624 | update_dma_c_d_ios().
1625 +----------------------------------------------------------------------------*/
1626 void update_dma_c_d_ios(void)
1628 gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
1629 gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1631 gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
1632 gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1634 gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
1635 gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1637 gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
1638 gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1640 gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
1641 gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1643 gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
1644 gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1648 /*----------------------------------------------------------------------------+
1649 | update_ebc_master_ios().
1650 +----------------------------------------------------------------------------*/
1651 void update_ebc_master_ios(void)
1653 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
1654 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1656 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1657 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1659 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
1660 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1662 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
1663 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1666 /*----------------------------------------------------------------------------+
1667 | update_usb2_device_ios().
1668 +----------------------------------------------------------------------------*/
1669 void update_usb2_device_ios(void)
1671 gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
1672 gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1674 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
1675 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1677 gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
1678 gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1680 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
1681 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1683 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
1684 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1686 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
1687 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1689 gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
1690 gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1692 gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
1693 gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1697 /*----------------------------------------------------------------------------+
1698 | update_pci_patch_ios().
1699 +----------------------------------------------------------------------------*/
1700 void update_pci_patch_ios(void)
1702 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1703 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1706 /*----------------------------------------------------------------------------+
1707 | set_chip_gpio_configuration(unsigned char gpio_core)
1708 | Put the core impacted by clock modification and sharing in reset.
1709 | Config the select registers to resolve the sharing depending of the config.
1710 | Configure the GPIO registers.
1712 +----------------------------------------------------------------------------*/
1713 void set_chip_gpio_configuration(unsigned char gpio_core)
1715 unsigned char i=0, j=0, reg_offset = 0;
1716 unsigned long gpio_reg, gpio_core_add;
1718 /* GPIO config of the GPIOs 0 to 31 */
1719 for (i=0; i<GPIO_MAX; i++, j++)
1721 if (i == GPIO_MAX/2)
1727 gpio_core_add = gpio_tab[gpio_core][i].add;
1729 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1730 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1732 switch (gpio_tab[gpio_core][i].alt_nb)
1738 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1739 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1740 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1744 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1745 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1746 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1750 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1751 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1752 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1756 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1757 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1760 switch (gpio_tab[gpio_core][i].alt_nb)
1765 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1766 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1767 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1768 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1769 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1770 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1773 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1774 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1775 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1776 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1777 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1778 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1781 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1782 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1783 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1784 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1785 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1786 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1793 /*----------------------------------------------------------------------------+
1794 | force_bup_core_selection.
1795 +----------------------------------------------------------------------------*/
1796 void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1798 /* Pointer invalid */
1799 if (core_select_P == NULL)
1801 printf("Configuration invalid pointer 1\n");
1807 *(core_select_P+UART_CORE0) = CORE_SELECTED;
1808 *(core_select_P+UART_CORE1) = CORE_SELECTED;
1809 *(core_select_P+UART_CORE2) = CORE_SELECTED;
1810 *(core_select_P+UART_CORE3) = CORE_SELECTED;
1812 /* RMII Selection */
1813 *(core_select_P+RMII_SEL) = CORE_SELECTED;
1815 /* External Interrupt 0-9 selection */
1816 *(core_select_P+UIC_0_3) = CORE_SELECTED;
1817 *(core_select_P+UIC_4_9) = CORE_SELECTED;
1819 *(core_select_P+SCP_CORE) = CORE_SELECTED;
1820 *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
1821 *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
1822 *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
1824 if (is_nand_selected()) {
1825 *(core_select_P+NAND_FLASH) = CORE_SELECTED;
1828 *config_val_P = CONFIG_IS_VALID;
1832 /*----------------------------------------------------------------------------+
1833 | configure_ppc440ep_pins.
1834 +----------------------------------------------------------------------------*/
1835 void configure_ppc440ep_pins(void)
1837 uart_config_nb_t uart_configuration;
1838 config_validity_t config_val = CONFIG_IS_INVALID;
1840 /* Create Core Selection Table */
1841 core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1843 CORE_NOT_SELECTED, /* IIC_CORE, */
1844 CORE_NOT_SELECTED, /* SPC_CORE, */
1845 CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
1846 CORE_NOT_SELECTED, /* UIC_4_9, */
1847 CORE_NOT_SELECTED, /* USB2_HOST, */
1848 CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
1849 CORE_NOT_SELECTED, /* USB2_DEVICE, */
1850 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
1851 CORE_NOT_SELECTED, /* USB1_DEVICE, */
1852 CORE_NOT_SELECTED, /* EBC_MASTER, */
1853 CORE_NOT_SELECTED, /* NAND_FLASH, */
1854 CORE_NOT_SELECTED, /* UART_CORE0, */
1855 CORE_NOT_SELECTED, /* UART_CORE1, */
1856 CORE_NOT_SELECTED, /* UART_CORE2, */
1857 CORE_NOT_SELECTED, /* UART_CORE3, */
1858 CORE_NOT_SELECTED, /* MII_SEL, */
1859 CORE_NOT_SELECTED, /* RMII_SEL, */
1860 CORE_NOT_SELECTED, /* SMII_SEL, */
1861 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
1862 CORE_NOT_SELECTED, /* UIC_0_3 */
1863 CORE_NOT_SELECTED, /* USB1_HOST */
1864 CORE_NOT_SELECTED /* PCI_PATCH */
1868 /* Table Default Initialisation + FPGA Access */
1869 init_default_gpio();
1870 set_chip_gpio_configuration(GPIO0);
1871 set_chip_gpio_configuration(GPIO1);
1874 force_bup_core_selection(ppc440ep_core_selection, &config_val);
1875 #if 0 /* test-only */
1876 /* If we are running PIBS 1, force known configuration */
1877 update_core_selection_table(ppc440ep_core_selection, &config_val);
1880 /*----------------------------------------------------------------------------+
1881 | SDR + ios table update + fpga initialization
1882 +----------------------------------------------------------------------------*/
1883 unsigned long sdr0_pfc1 = 0;
1884 unsigned long sdr0_usb0 = 0;
1885 unsigned long sdr0_mfr = 0;
1887 /* PCI Always selected */
1890 if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1892 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1893 iic1_selection_in_fpga();
1897 if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1899 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1900 scp_selection_in_fpga();
1903 /* UIC 0:3 Selection */
1904 if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1906 update_uic_0_3_irq_ios();
1907 dma_a_b_unselect_in_fpga();
1910 /* UIC 4:9 Selection */
1911 if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1913 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
1914 update_uic_4_9_irq_ios();
1917 /* DMA AB Selection */
1918 if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1920 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
1921 update_dma_a_b_ios();
1922 dma_a_b_selection_in_fpga();
1925 /* DMA CD Selection */
1926 if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1928 update_dma_c_d_ios();
1929 dma_c_d_selection_in_fpga();
1932 /* EBC Master Selection */
1933 if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1935 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1936 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1937 update_ebc_master_ios();
1940 /* PCI Patch Enable */
1941 if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1943 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1944 update_pci_patch_ios();
1947 /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1948 if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1950 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1951 printf("Invalid configuration => USB2 Host selected\n");
1954 /*usb2_host_selection_in_fpga(); */
1957 /* USB2.0 Device Selection */
1958 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1960 update_usb2_device_ios();
1961 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1962 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1964 mfsdr(sdr_usb0, sdr0_usb0);
1965 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1966 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
1967 mtsdr(sdr_usb0, sdr0_usb0);
1969 usb2_device_selection_in_fpga();
1972 /* USB1.1 Device Selection */
1973 if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1975 mfsdr(sdr_usb0, sdr0_usb0);
1976 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1977 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
1978 mtsdr(sdr_usb0, sdr0_usb0);
1981 /* USB1.1 Host Selection */
1982 if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1984 mfsdr(sdr_usb0, sdr0_usb0);
1985 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1986 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
1987 mtsdr(sdr_usb0, sdr0_usb0);
1990 /* NAND Flash Selection */
1991 if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
1995 mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
1996 SDR0_CUST0_NDFC_ENABLE |
1997 SDR0_CUST0_NDFC_BW_8_BIT |
1998 SDR0_CUST0_NDFC_ARE_MASK |
1999 SDR0_CUST0_CHIPSELGAT_EN1 |
2000 SDR0_CUST0_CHIPSELGAT_EN2);
2002 ndfc_selection_in_fpga();
2006 /* Set Mux on EMAC */
2007 mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
2011 if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
2014 mfsdr(sdr_mfr, sdr0_mfr);
2015 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
2016 mtsdr(sdr_mfr, sdr0_mfr);
2018 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
2021 /* RMII Selection */
2022 if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
2025 mfsdr(sdr_mfr, sdr0_mfr);
2026 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
2027 mtsdr(sdr_mfr, sdr0_mfr);
2029 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
2032 /* SMII Selection */
2033 if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
2036 mfsdr(sdr_mfr, sdr0_mfr);
2037 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
2038 mtsdr(sdr_mfr, sdr0_mfr);
2040 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
2043 /* UART Selection */
2044 uart_configuration = get_uart_configuration();
2045 switch (uart_configuration)
2047 case L1: /* L1 Selection */
2048 /* UART0 8 pins Only */
2049 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
2050 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
2051 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
2053 case L2: /* L2 Selection */
2054 /* UART0 and UART1 4 pins */
2055 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2056 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2057 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2059 case L3: /* L3 Selection */
2060 /* UART0 4 pins, UART1 and UART2 2 pins */
2061 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2062 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2063 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2065 case L4: /* L4 Selection */
2066 /* UART0, UART1, UART2 and UART3 2 pins */
2067 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
2068 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
2069 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
2072 update_uart_ios(uart_configuration);
2074 /* UART Selection in all cases */
2075 uart_selection_in_fpga(uart_configuration);
2077 /* Packet Reject Function Available */
2078 if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
2080 /* Set UPR Bit in SDR0_PFC1 Register */
2081 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
2084 /* Packet Reject Function Enable */
2085 if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
2087 mfsdr(sdr_mfr, sdr0_mfr);
2088 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
2089 mtsdr(sdr_mfr, sdr0_mfr);
2092 /* Perform effective access to hardware */
2093 mtsdr(sdr_pfc1, sdr0_pfc1);
2094 set_chip_gpio_configuration(GPIO0);
2095 set_chip_gpio_configuration(GPIO1);
2097 /* USB2.0 Device Reset must be done after GPIO setting */
2098 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
2099 usb2_device_reset_through_fpga();