3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <spd_sdram.h>
28 int board_early_init_f(void)
32 /*--------------------------------------------------------------------
33 * Setup the external bus controller/chip selects
34 *-------------------------------------------------------------------*/
35 mtdcr(ebccfga, xbcfg);
37 mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
40 mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
41 mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
43 mtebc(pb1ap, 0x00000000);
44 mtebc(pb1cr, 0x00000000);
46 mtebc(pb2ap, 0x04814500);
47 /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
49 mtebc(pb0ap, 0x04055200); /* FLASH/SRAM */
50 mtebc(pb0cr, 0xfff18000); /* BAS=0xfe0 1MB r/w 8-bit */
53 mtebc(pb3ap, 0x00000000);
54 mtebc(pb3cr, 0x00000000);
56 mtebc(pb4ap, 0x00000000);
57 mtebc(pb4cr, 0x00000000);
59 mtebc(pb5ap, 0x00000000);
60 mtebc(pb5cr, 0x00000000);
62 /*--------------------------------------------------------------------
63 * Setup the interrupt controller polarities, triggers, etc.
64 *-------------------------------------------------------------------*/
65 mtdcr(uic0sr, 0xffffffff); /* clear all */
66 mtdcr(uic0er, 0x00000000); /* disable all */
67 mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
68 mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
69 mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
70 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
71 mtdcr(uic0sr, 0xffffffff); /* clear all */
73 mtdcr(uic1sr, 0xffffffff); /* clear all */
74 mtdcr(uic1er, 0x00000000); /* disable all */
75 mtdcr(uic1cr, 0x00000000); /* all non-critical */
76 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
77 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
78 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
79 mtdcr(uic1sr, 0xffffffff); /* clear all */
81 /*--------------------------------------------------------------------
83 *-------------------------------------------------------------------*/
85 /*setup Address lines for flash sizes larger than 16Meg. */
86 out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
87 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
88 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
91 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
92 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
93 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
94 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
95 out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
98 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
99 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
100 out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
103 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
104 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
105 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
106 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
107 out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
109 /*--------------------------------------------------------------------
110 * Setup other serial configuration
111 *-------------------------------------------------------------------*/
112 mfsdr(sdr_pci0, reg);
113 mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
114 mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
115 mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
117 #if 0 /* test-only */
118 /*clear tmrclk divisor */
119 *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
122 *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
124 /*enable usb 1.1 fs device and remove usb 2.0 reset */
125 *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
127 /*get rid of flash write protect */
128 *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
137 unsigned char *s = getenv("serial#");
139 get_sys_info(&sysinfo);
141 printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
148 printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
149 printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
150 printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
151 printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
152 printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
156 /*************************************************************************
157 * sdram_init -- doesn't use serial presence detect.
159 * Assumes: 256 MB, ECC, non-registered
162 ************************************************************************/
163 void sdram_init(void)
167 /*--------------------------------------------------------------------
169 *------------------------------------------------------------------*/
170 mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
171 mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
172 mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
173 mtsdram(mem_clktr, 0x40000000); /* ?? */
174 mtsdram(mem_wddctr, 0x40000000); /* ?? */
176 /*clear this first, if the DDR is enabled by a debugger
177 then you can not make changes. */
178 mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
180 /*--------------------------------------------------------------------
181 * Setup for board-specific specific mem
182 *------------------------------------------------------------------*/
184 * Following for CAS Latency = 2.5 @ 133 MHz PLB
186 mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
187 mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
189 mtsdram(mem_tr0, 0x410a4012); /* ?? */
190 mtsdram(mem_tr1, 0x8080080b); /* ?? */
191 mtsdram(mem_rtr, 0x04080000); /* ?? */
192 mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
193 mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
194 udelay(400); /* Delay 200 usecs (min) */
196 /*--------------------------------------------------------------------
197 * Enable the controller, then wait for DCEN to complete
198 *------------------------------------------------------------------*/
199 mtsdram(mem_cfg0, 0x84000000); /* Enable */
202 mfsdram(mem_mcsts, reg);
203 if (reg & 0x80000000)
208 /*************************************************************************
211 ************************************************************************/
212 long int initdram(int board)
215 return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
218 #if defined(CFG_DRAM_TEST)
221 unsigned long *mem = (unsigned long *)0;
222 const unsigned long kend = (1024 / sizeof(unsigned long));
227 for (k = 0; k < CFG_KBYTES_SDRAM;
228 ++k, mem += (1024 / sizeof(unsigned long))) {
229 if ((k & 1023) == 0) {
230 printf("%3d MB\r", k / 1024);
233 memset(mem, 0xaaaaaaaa, 1024);
234 for (n = 0; n < kend; ++n) {
235 if (mem[n] != 0xaaaaaaaa) {
236 printf("SDRAM test fails at: %08x\n",
242 memset(mem, 0x55555555, 1024);
243 for (n = 0; n < kend; ++n) {
244 if (mem[n] != 0x55555555) {
245 printf("SDRAM test fails at: %08x\n",
251 printf("SDRAM test passes\n");
256 /*************************************************************************
259 * This routine is called just prior to registering the hose and gives
260 * the board the opportunity to check things. Returning a value of zero
261 * indicates that things are bad & PCI initialization should be aborted.
263 * Different boards may wish to customize the pci controller structure
264 * (add regions, override default access routines, etc) or perform
265 * certain pre-initialization actions.
267 ************************************************************************/
268 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
269 int pci_pre_init(struct pci_controller *hose)
274 /*--------------------------------------------------------------------------+
275 * Bamboo is always configured as the host & requires the
276 * PCI arbiter to be enabled.
277 *--------------------------------------------------------------------------*/
278 mfsdr(sdr_sdstp1, strap);
279 if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
280 printf("PCI: SDR0_STRP1[PAE] not set.\n");
281 printf("PCI: Configuration aborted.\n");
285 /*-------------------------------------------------------------------------+
286 | Set priority for all PLB3 devices to 0.
287 | Set PLB3 arbiter to fair mode.
288 +-------------------------------------------------------------------------*/
289 mfsdr(sdr_amp1, addr);
290 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
291 addr = mfdcr(plb3_acr);
292 mtdcr(plb3_acr, addr | 0x80000000);
294 /*-------------------------------------------------------------------------+
295 | Set priority for all PLB4 devices to 0.
296 +-------------------------------------------------------------------------*/
297 mfsdr(sdr_amp0, addr);
298 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
299 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
300 mtdcr(plb4_acr, addr);
302 /*-------------------------------------------------------------------------+
303 | Set Nebula PLB4 arbiter to fair mode.
304 +-------------------------------------------------------------------------*/
306 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
307 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
308 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
309 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
310 mtdcr(plb0_acr, addr);
313 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
314 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
315 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
316 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
317 mtdcr(plb1_acr, addr);
321 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
323 /*************************************************************************
326 * The bootstrap configuration provides default settings for the pci
327 * inbound map (PIM). But the bootstrap config choices are limited and
328 * may not be sufficient for a given board.
330 ************************************************************************/
331 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
332 void pci_target_init(struct pci_controller *hose)
334 /*--------------------------------------------------------------------------+
335 * Set up Direct MMIO registers
336 *--------------------------------------------------------------------------*/
337 /*--------------------------------------------------------------------------+
338 | PowerPC440 EP PCI Master configuration.
339 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
340 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
341 | Use byte reversed out routines to handle endianess.
342 | Make this region non-prefetchable.
343 +--------------------------------------------------------------------------*/
344 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
345 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
346 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
347 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
348 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
350 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
351 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
352 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
353 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
354 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
356 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
357 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
358 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
359 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
361 /*--------------------------------------------------------------------------+
362 * Set up Configuration registers
363 *--------------------------------------------------------------------------*/
365 /* Program the board's subsystem id/vendor id */
366 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
367 CFG_PCI_SUBSYS_VENDORID);
368 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
370 /* Configure command register as bus master */
371 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
373 /* 240nS PCI clock */
374 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
376 /* No error reporting */
377 pci_write_config_word(0, PCI_ERREN, 0);
379 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
382 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
384 /*************************************************************************
387 ************************************************************************/
388 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
389 void pci_master_init(struct pci_controller *hose)
391 unsigned short temp_short;
393 /*--------------------------------------------------------------------------+
394 | Write the PowerPC440 EP PCI Configuration regs.
395 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
396 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
397 +--------------------------------------------------------------------------*/
398 pci_read_config_word(0, PCI_COMMAND, &temp_short);
399 pci_write_config_word(0, PCI_COMMAND,
400 temp_short | PCI_COMMAND_MASTER |
403 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
405 /*************************************************************************
408 * This routine is called to determine if a pci scan should be
409 * performed. With various hardware environments (especially cPCI and
410 * PPMC) it's insufficient to depend on the state of the arbiter enable
411 * bit in the strap register, or generic host/adapter assumptions.
413 * Rather than hard-code a bad assumption in the general 440 code, the
414 * 440 pci code requires the board to decide at runtime.
416 * Return 0 for adapter mode, non-zero for host (monarch) mode.
419 ************************************************************************/
420 #if defined(CONFIG_PCI)
421 int is_pci_host(struct pci_controller *hose)
423 /* Bamboo is always configured as host. */
426 #endif /* defined(CONFIG_PCI) */
428 /*************************************************************************
431 * This routine is called to reset (keep alive) the watchdog timer
433 ************************************************************************/
434 #if defined(CONFIG_HW_WATCHDOG)
435 void hw_watchdog_reset(void)