2 * (C) Copyright 2005-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/processor.h>
10 #include <asm/ppc4xx-gpio.h>
11 #include <spd_sdram.h>
12 #include <asm/ppc440.h>
15 void ext_bus_cntlr_init(void);
16 void configure_ppc440ep_pins(void);
17 int is_nand_selected(void);
19 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
20 /*************************************************************************
22 * Bamboo has one bank onboard sdram (plus DIMM)
24 * Fixed memory is composed of :
25 * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
26 * 13 row add bits, 10 column add bits (but 12 row used only).
27 * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
28 * 12 row add bits, 10 column add bits.
29 * Prepare a subset (only the used ones) of SPD data
31 * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
32 * the corresponding bank is divided by 2 due to number of Row addresses
33 * 12 in the ECC module
35 * Assumes: 64 MB, ECC, non-registered
38 ************************************************************************/
39 const unsigned char cfg_simulate_spd_eeprom[128] = {
40 0x80, /* number of SPD bytes used: 128 */
41 0x08, /* total number bytes in SPD device = 256 */
44 0x0C, /* num Row Addr: 12 */
46 0x0D, /* num Row Addr: 13 */
48 0x09, /* numColAddr: 9 */
49 0x01, /* numBanks: 1 */
50 0x20, /* Module data width: 32 bits */
51 0x00, /* Module data width continued: +0 */
53 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
54 0x00, /* SDRAM Access from clock */
56 0x02, /* ECC ON : 02 OFF : 00 */
58 0x00, /* ECC ON : 02 OFF : 00 */
60 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */
66 0x0C, /* casBit (2,2.5) */
69 0x00, /* not registered: 0 registered : 0x02*/
71 0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
73 0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
75 0x50, /* tRpNs = 20 ns */
77 0x50, /* tRcdNs = 20 ns */
80 0x08, /* bankSizeID: 32MB */
82 0x10, /* bankSizeID: 64MB */
184 { /* GPIO Alternate1 Alternate2 Alternate3 */
187 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
188 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
189 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
190 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
191 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
192 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
193 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
194 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
195 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
196 { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
197 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
198 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
199 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
200 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
201 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
202 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
203 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
204 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
205 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
206 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
207 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
208 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
209 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
210 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
211 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
212 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
213 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
214 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
215 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
216 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
217 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
218 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
222 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
223 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
224 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
225 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
226 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
227 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
228 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
229 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
230 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
231 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
232 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
233 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
234 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
235 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
236 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
237 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
238 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
239 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
240 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
241 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
242 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
243 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
244 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
245 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
246 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
247 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
248 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
249 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
250 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
251 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
252 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
253 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
258 /*----------------------------------------------------------------------------+
259 | EBC Devices Characteristics
260 | Peripheral Bank Access Parameters - EBC0_BnAP
261 | Peripheral Bank Configuration Register - EBC0_BnCR
262 +----------------------------------------------------------------------------*/
264 #define EBC0_BNAP_SMALL_FLASH \
265 EBC0_BNAP_BME_DISABLED | \
266 EBC0_BNAP_TWT_ENCODE(6) | \
267 EBC0_BNAP_CSN_ENCODE(0) | \
268 EBC0_BNAP_OEN_ENCODE(1) | \
269 EBC0_BNAP_WBN_ENCODE(1) | \
270 EBC0_BNAP_WBF_ENCODE(3) | \
271 EBC0_BNAP_TH_ENCODE(1) | \
272 EBC0_BNAP_RE_ENABLED | \
273 EBC0_BNAP_SOR_DELAYED | \
274 EBC0_BNAP_BEM_WRITEONLY | \
275 EBC0_BNAP_PEN_DISABLED
277 #define EBC0_BNCR_SMALL_FLASH_CS0 \
278 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
283 #define EBC0_BNCR_SMALL_FLASH_CS4 \
284 EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
289 /* Large Flash or SRAM */
290 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
291 EBC0_BNAP_BME_DISABLED | \
292 EBC0_BNAP_TWT_ENCODE(8) | \
293 EBC0_BNAP_CSN_ENCODE(0) | \
294 EBC0_BNAP_OEN_ENCODE(1) | \
295 EBC0_BNAP_WBN_ENCODE(1) | \
296 EBC0_BNAP_WBF_ENCODE(1) | \
297 EBC0_BNAP_TH_ENCODE(2) | \
298 EBC0_BNAP_SOR_DELAYED | \
300 EBC0_BNAP_PEN_DISABLED
302 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
303 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
309 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
310 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
316 #define EBC0_BNAP_NVRAM_FPGA \
317 EBC0_BNAP_BME_DISABLED | \
318 EBC0_BNAP_TWT_ENCODE(9) | \
319 EBC0_BNAP_CSN_ENCODE(0) | \
320 EBC0_BNAP_OEN_ENCODE(1) | \
321 EBC0_BNAP_WBN_ENCODE(1) | \
322 EBC0_BNAP_WBF_ENCODE(0) | \
323 EBC0_BNAP_TH_ENCODE(2) | \
324 EBC0_BNAP_RE_ENABLED | \
325 EBC0_BNAP_SOR_DELAYED | \
326 EBC0_BNAP_BEM_WRITEONLY | \
327 EBC0_BNAP_PEN_DISABLED
329 #define EBC0_BNCR_NVRAM_FPGA_CS5 \
330 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
336 #define EBC0_BNAP_NAND_FLASH \
337 EBC0_BNAP_BME_DISABLED | \
338 EBC0_BNAP_TWT_ENCODE(3) | \
339 EBC0_BNAP_CSN_ENCODE(0) | \
340 EBC0_BNAP_OEN_ENCODE(0) | \
341 EBC0_BNAP_WBN_ENCODE(0) | \
342 EBC0_BNAP_WBF_ENCODE(0) | \
343 EBC0_BNAP_TH_ENCODE(1) | \
344 EBC0_BNAP_RE_ENABLED | \
345 EBC0_BNAP_SOR_NOT_DELAYED | \
347 EBC0_BNAP_PEN_DISABLED
350 #define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
353 #define EBC0_BNCR_NAND_FLASH_CS1 \
354 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
359 #define EBC0_BNCR_NAND_FLASH_CS2 \
360 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
366 #define EBC0_BNCR_NAND_FLASH_CS3 \
367 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
372 int board_early_init_f(void)
374 ext_bus_cntlr_init();
376 /*--------------------------------------------------------------------
377 * Setup the interrupt controller polarities, triggers, etc.
378 *-------------------------------------------------------------------*/
379 mtdcr(UIC0SR, 0xffffffff); /* clear all */
380 mtdcr(UIC0ER, 0x00000000); /* disable all */
381 mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
382 mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
383 mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
384 mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
385 mtdcr(UIC0SR, 0xffffffff); /* clear all */
387 mtdcr(UIC1SR, 0xffffffff); /* clear all */
388 mtdcr(UIC1ER, 0x00000000); /* disable all */
389 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
390 mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
391 mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
392 mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
393 mtdcr(UIC1SR, 0xffffffff); /* clear all */
395 /*--------------------------------------------------------------------
396 * Setup the GPIO pins
397 *-------------------------------------------------------------------*/
398 out32(GPIO0_OSRL, 0x00000400);
399 out32(GPIO0_OSRH, 0x00000000);
400 out32(GPIO0_TSRL, 0x00000400);
401 out32(GPIO0_TSRH, 0x00000000);
402 out32(GPIO0_ISR1L, 0x00000000);
403 out32(GPIO0_ISR1H, 0x00000000);
404 out32(GPIO0_ISR2L, 0x00000000);
405 out32(GPIO0_ISR2H, 0x00000000);
406 out32(GPIO0_ISR3L, 0x00000000);
407 out32(GPIO0_ISR3H, 0x00000000);
409 out32(GPIO1_OSRL, 0x0C380000);
410 out32(GPIO1_OSRH, 0x00000000);
411 out32(GPIO1_TSRL, 0x0C380000);
412 out32(GPIO1_TSRH, 0x00000000);
413 out32(GPIO1_ISR1L, 0x0FC30000);
414 out32(GPIO1_ISR1H, 0x00000000);
415 out32(GPIO1_ISR2L, 0x0C010000);
416 out32(GPIO1_ISR2H, 0x00000000);
417 out32(GPIO1_ISR3L, 0x01400000);
418 out32(GPIO1_ISR3H, 0x00000000);
420 configure_ppc440ep_pins();
428 int i = getenv_f("serial#", buf, sizeof(buf));
430 printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
441 phys_size_t initdram (int board_type)
443 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
446 dram_size = spd_sdram();
450 return CONFIG_SYS_MBYTES_SDRAM << 20;
454 /*----------------------------------------------------------------------------+
455 | is_powerpc440ep_pass1.
456 +----------------------------------------------------------------------------*/
457 int is_powerpc440ep_pass1(void)
463 if (pvr == PVR_POWERPC_440EP_PASS1)
465 else if (pvr == PVR_POWERPC_440EP_PASS2)
468 printf("brdutil error 3\n");
476 /*----------------------------------------------------------------------------+
478 +----------------------------------------------------------------------------*/
479 int is_nand_selected(void)
481 #ifdef CONFIG_BAMBOO_NAND
488 /*----------------------------------------------------------------------------+
489 | config_on_ebc_cs4_is_small_flash => from EPLD
490 +----------------------------------------------------------------------------*/
491 unsigned char config_on_ebc_cs4_is_small_flash(void)
493 /* Not implemented yet => returns constant value */
497 /*----------------------------------------------------------------------------+
498 | Ext_bus_cntlr_init.
499 | Initialize the external bus controller
500 +----------------------------------------------------------------------------*/
501 void ext_bus_cntlr_init(void)
503 unsigned long sdr0_pstrp0, sdr0_sdstp1;
504 unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
505 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
506 unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
507 unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
508 unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
509 unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
510 unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
513 /*-------------------------------------------------------------------------+
515 | PART 1 : Initialize EBC Bank 5
516 | ==============================
517 | Bank5 is always associated to the NVRAM/EPLD.
518 | It has to be initialized prior to other banks settings computation since
519 | some board registers values may be needed
521 +-------------------------------------------------------------------------*/
523 mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA);
524 mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5);
526 /*-------------------------------------------------------------------------+
528 | PART 2 : Determine which boot device was selected
529 | =========================================
531 | Read Pin Strap Register in PPC440EP
532 | In case of boot from IIC, read Serial Device Strap Register1
534 | Result can either be :
535 | - Boot from EBC 8bits => SMALL FLASH
536 | - Boot from EBC 16bits => Large Flash or SRAM
537 | - Boot from NAND Flash
540 +-------------------------------------------------------------------------*/
541 /* Read Pin Strap Register in PPC440EP */
542 mfsdr(SDR0_PINSTP, sdr0_pstrp0);
543 bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
545 /*-------------------------------------------------------------------------+
547 +-------------------------------------------------------------------------*/
548 if (is_powerpc440ep_pass1() == true) {
549 switch(bootstrap_settings) {
550 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
551 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
552 /* Boot from Small Flash */
553 computed_boot_device = BOOT_FROM_SMALL_FLASH;
555 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
556 /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
558 computed_boot_device = BOOT_FROM_PCI;
561 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
562 /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
563 /* Boot from Nand Flash */
564 computed_boot_device = BOOT_FROM_NAND_FLASH0;
567 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
568 /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
569 /* Boot from Small Flash */
570 computed_boot_device = BOOT_FROM_SMALL_FLASH;
573 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
574 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
575 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
576 /* Read Serial Device Strap Register1 in PPC440EP */
577 mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
578 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
579 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
581 switch(boot_selection) {
582 case SDR0_SDSTP1_BOOT_SEL_EBC:
583 switch(ebc_boot_size) {
584 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
585 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
587 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
588 computed_boot_device = BOOT_FROM_SMALL_FLASH;
593 case SDR0_SDSTP1_BOOT_SEL_PCI:
594 computed_boot_device = BOOT_FROM_PCI;
597 case SDR0_SDSTP1_BOOT_SEL_NDFC:
598 computed_boot_device = BOOT_FROM_NAND_FLASH0;
605 /*-------------------------------------------------------------------------+
607 +-------------------------------------------------------------------------*/
609 switch(bootstrap_settings) {
610 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
611 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
612 /* Boot from Small Flash */
613 computed_boot_device = BOOT_FROM_SMALL_FLASH;
615 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
616 /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
618 computed_boot_device = BOOT_FROM_PCI;
621 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
622 /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
623 /* Boot from Nand Flash */
624 computed_boot_device = BOOT_FROM_NAND_FLASH0;
627 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
628 /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
629 /* Boot from Large Flash or SRAM */
630 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
633 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
634 /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
635 /* Boot from Large Flash or SRAM */
636 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
639 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
640 /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
642 computed_boot_device = BOOT_FROM_PCI;
645 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
646 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
647 /* Default Strap Settings 5-7 */
648 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
649 /* Read Serial Device Strap Register1 in PPC440EP */
650 mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
651 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
652 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
654 switch(boot_selection) {
655 case SDR0_SDSTP1_BOOT_SEL_EBC:
656 switch(ebc_boot_size) {
657 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
658 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
660 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
661 computed_boot_device = BOOT_FROM_SMALL_FLASH;
666 case SDR0_SDSTP1_BOOT_SEL_PCI:
667 computed_boot_device = BOOT_FROM_PCI;
670 case SDR0_SDSTP1_BOOT_SEL_NDFC:
671 computed_boot_device = BOOT_FROM_NAND_FLASH0;
678 /*-------------------------------------------------------------------------+
680 | PART 3 : Compute EBC settings depending on selected boot device
681 | ====== ======================================================
683 | Resulting EBC init will be among following configurations :
685 | - Boot from EBC 8bits => boot from SMALL FLASH selected
686 | EBC-CS0 = Small Flash
687 | EBC-CS1,2,3 = NAND Flash or
688 | Exp.Slot depending on Soft Config
689 | EBC-CS4 = SRAM/Large Flash or
690 | Large Flash/SRAM depending on jumpers
691 | EBC-CS5 = NVRAM / EPLD
693 | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
694 | EBC-CS0 = SRAM/Large Flash or
695 | Large Flash/SRAM depending on jumpers
696 | EBC-CS1,2,3 = NAND Flash or
697 | Exp.Slot depending on Software Configuration
698 | EBC-CS4 = Small Flash
699 | EBC-CS5 = NVRAM / EPLD
701 | - Boot from NAND Flash
702 | EBC-CS0 = NAND Flash0
703 | EBC-CS1,2,3 = NAND Flash1
704 | EBC-CS4 = SRAM/Large Flash or
705 | Large Flash/SRAM depending on jumpers
706 | EBC-CS5 = NVRAM / EPLD
710 | EBC-CS1,2,3 = NAND Flash or
711 | Exp.Slot depending on Software Configuration
712 | EBC-CS4 = SRAM/Large Flash or
713 | Large Flash/SRAM or
714 | Small Flash depending on jumpers
715 | EBC-CS5 = NVRAM / EPLD
717 +-------------------------------------------------------------------------*/
719 switch(computed_boot_device) {
720 /*------------------------------------------------------------------------- */
721 case BOOT_FROM_SMALL_FLASH:
722 /*------------------------------------------------------------------------- */
723 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
724 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
725 if ((is_nand_selected()) == true) {
727 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
728 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
729 ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
730 ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
731 ebc0_cs3_bnap_value = 0;
732 ebc0_cs3_bncr_value = 0;
735 ebc0_cs1_bnap_value = 0;
736 ebc0_cs1_bncr_value = 0;
737 ebc0_cs2_bnap_value = 0;
738 ebc0_cs2_bncr_value = 0;
739 ebc0_cs3_bnap_value = 0;
740 ebc0_cs3_bncr_value = 0;
742 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
743 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
747 /*------------------------------------------------------------------------- */
748 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
749 /*------------------------------------------------------------------------- */
750 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
751 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
752 if ((is_nand_selected()) == true) {
754 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
755 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
756 ebc0_cs2_bnap_value = 0;
757 ebc0_cs2_bncr_value = 0;
758 ebc0_cs3_bnap_value = 0;
759 ebc0_cs3_bncr_value = 0;
762 ebc0_cs1_bnap_value = 0;
763 ebc0_cs1_bncr_value = 0;
764 ebc0_cs2_bnap_value = 0;
765 ebc0_cs2_bncr_value = 0;
766 ebc0_cs3_bnap_value = 0;
767 ebc0_cs3_bncr_value = 0;
769 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
770 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
774 /*------------------------------------------------------------------------- */
775 case BOOT_FROM_NAND_FLASH0:
776 /*------------------------------------------------------------------------- */
777 ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
778 ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
780 ebc0_cs1_bnap_value = 0;
781 ebc0_cs1_bncr_value = 0;
782 ebc0_cs2_bnap_value = 0;
783 ebc0_cs2_bncr_value = 0;
784 ebc0_cs3_bnap_value = 0;
785 ebc0_cs3_bncr_value = 0;
787 /* Large Flash or SRAM */
788 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
789 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
793 /*------------------------------------------------------------------------- */
795 /*------------------------------------------------------------------------- */
796 ebc0_cs0_bnap_value = 0;
797 ebc0_cs0_bncr_value = 0;
799 if ((is_nand_selected()) == true) {
801 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
802 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
803 ebc0_cs2_bnap_value = 0;
804 ebc0_cs2_bncr_value = 0;
805 ebc0_cs3_bnap_value = 0;
806 ebc0_cs3_bncr_value = 0;
809 ebc0_cs1_bnap_value = 0;
810 ebc0_cs1_bncr_value = 0;
811 ebc0_cs2_bnap_value = 0;
812 ebc0_cs2_bncr_value = 0;
813 ebc0_cs3_bnap_value = 0;
814 ebc0_cs3_bncr_value = 0;
817 if ((config_on_ebc_cs4_is_small_flash()) == true) {
819 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
820 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
822 /* Large Flash or SRAM */
823 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
824 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
829 /*------------------------------------------------------------------------- */
830 case BOOT_DEVICE_UNKNOWN:
831 /*------------------------------------------------------------------------- */
838 /*-------------------------------------------------------------------------+
839 | Initialize EBC CONFIG
840 +-------------------------------------------------------------------------*/
841 mtdcr(EBC0_CFGADDR, EBC0_CFG);
842 mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN |
843 EBC0_CFG_PTD_ENABLED |
844 EBC0_CFG_RTC_2048PERCLK |
847 EBC0_CFG_CSTC_DRIVEN |
850 EBC0_CFG_PME_DISABLED |
851 EBC0_CFG_PMT_ENCODE(0) );
853 /*-------------------------------------------------------------------------+
854 | Initialize EBC Bank 0-4
855 +-------------------------------------------------------------------------*/
857 mtebc(PB0AP, ebc0_cs0_bnap_value);
858 mtebc(PB0CR, ebc0_cs0_bncr_value);
860 mtebc(PB1AP, ebc0_cs1_bnap_value);
861 mtebc(PB1CR, ebc0_cs1_bncr_value);
863 mtebc(PB2AP, ebc0_cs2_bnap_value);
864 mtebc(PB2CR, ebc0_cs2_bncr_value);
866 mtebc(PB3AP, ebc0_cs3_bnap_value);
867 mtebc(PB3CR, ebc0_cs3_bncr_value);
869 mtebc(PB4AP, ebc0_cs4_bnap_value);
870 mtebc(PB4CR, ebc0_cs4_bncr_value);
876 /*----------------------------------------------------------------------------+
877 | get_uart_configuration.
878 +----------------------------------------------------------------------------*/
879 uart_config_nb_t get_uart_configuration(void)
884 /*----------------------------------------------------------------------------+
885 | set_phy_configuration_through_fpga => to EPLD
886 +----------------------------------------------------------------------------*/
887 void set_phy_configuration_through_fpga(zmii_config_t config)
890 unsigned long fpga_selection_reg;
892 fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
896 case ZMII_CONFIGURATION_IS_MII:
897 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
899 case ZMII_CONFIGURATION_IS_RMII:
900 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
902 case ZMII_CONFIGURATION_IS_SMII:
903 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
905 case ZMII_CONFIGURATION_UNKNOWN:
909 out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
913 /*----------------------------------------------------------------------------+
914 | scp_selection_in_fpga.
915 +----------------------------------------------------------------------------*/
916 void scp_selection_in_fpga(void)
918 unsigned long fpga_selection_2_reg;
920 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
921 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
922 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
925 /*----------------------------------------------------------------------------+
926 | iic1_selection_in_fpga.
927 +----------------------------------------------------------------------------*/
928 void iic1_selection_in_fpga(void)
930 unsigned long fpga_selection_2_reg;
932 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
933 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
934 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
937 /*----------------------------------------------------------------------------+
938 | dma_a_b_selection_in_fpga.
939 +----------------------------------------------------------------------------*/
940 void dma_a_b_selection_in_fpga(void)
942 unsigned long fpga_selection_2_reg;
944 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
945 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
948 /*----------------------------------------------------------------------------+
949 | dma_a_b_unselect_in_fpga.
950 +----------------------------------------------------------------------------*/
951 void dma_a_b_unselect_in_fpga(void)
953 unsigned long fpga_selection_2_reg;
955 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
956 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
959 /*----------------------------------------------------------------------------+
960 | dma_c_d_selection_in_fpga.
961 +----------------------------------------------------------------------------*/
962 void dma_c_d_selection_in_fpga(void)
964 unsigned long fpga_selection_2_reg;
966 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
967 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
970 /*----------------------------------------------------------------------------+
971 | dma_c_d_unselect_in_fpga.
972 +----------------------------------------------------------------------------*/
973 void dma_c_d_unselect_in_fpga(void)
975 unsigned long fpga_selection_2_reg;
977 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
978 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
981 /*----------------------------------------------------------------------------+
982 | usb2_device_selection_in_fpga.
983 +----------------------------------------------------------------------------*/
984 void usb2_device_selection_in_fpga(void)
986 unsigned long fpga_selection_1_reg;
988 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
989 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
992 /*----------------------------------------------------------------------------+
993 | usb2_device_reset_through_fpga.
994 +----------------------------------------------------------------------------*/
995 void usb2_device_reset_through_fpga(void)
997 /* Perform soft Reset pulse */
998 unsigned long fpga_reset_reg;
1001 fpga_reset_reg = in8(FPGA_RESET_REG);
1002 out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1003 for (i=0; i<500; i++)
1005 out8(FPGA_RESET_REG,fpga_reset_reg);
1008 /*----------------------------------------------------------------------------+
1009 | usb2_host_selection_in_fpga.
1010 +----------------------------------------------------------------------------*/
1011 void usb2_host_selection_in_fpga(void)
1013 unsigned long fpga_selection_1_reg;
1015 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1016 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1019 /*----------------------------------------------------------------------------+
1020 | ndfc_selection_in_fpga.
1021 +----------------------------------------------------------------------------*/
1022 void ndfc_selection_in_fpga(void)
1024 unsigned long fpga_selection_1_reg;
1026 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1027 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
1028 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
1029 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1032 /*----------------------------------------------------------------------------+
1033 | uart_selection_in_fpga.
1034 +----------------------------------------------------------------------------*/
1035 void uart_selection_in_fpga(uart_config_nb_t uart_config)
1038 unsigned char fpga_selection_3_reg;
1040 /* Read FPGA Reagister */
1041 fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1043 switch (uart_config)
1046 /* ----------------------------------------------------------------------- */
1047 /* L1 configuration: UART0 = 8 pins */
1048 /* ----------------------------------------------------------------------- */
1049 /* Configure FPGA */
1050 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1051 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
1052 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1057 /* ----------------------------------------------------------------------- */
1058 /* L2 configuration: UART0 = 4 pins */
1059 /* UART1 = 4 pins */
1060 /* ----------------------------------------------------------------------- */
1061 /* Configure FPGA */
1062 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1063 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
1064 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1069 /* ----------------------------------------------------------------------- */
1070 /* L3 configuration: UART0 = 4 pins */
1071 /* UART1 = 2 pins */
1072 /* UART2 = 2 pins */
1073 /* ----------------------------------------------------------------------- */
1074 /* Configure FPGA */
1075 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1076 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
1077 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1081 /* Configure FPGA */
1082 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1083 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
1084 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1089 /* Unsupported UART configuration number */
1098 /*----------------------------------------------------------------------------+
1100 +----------------------------------------------------------------------------*/
1101 void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
1106 for(i=0; i<GPIO_MAX; i++)
1108 gpio_tab[GPIO0][i].add = GPIO0_BASE;
1109 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1110 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1114 for(i=0; i<GPIO_MAX; i++)
1116 gpio_tab[GPIO1][i].add = GPIO1_BASE;
1117 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1118 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1121 /* EBC_CS_N(5) - GPIO0_10 */
1122 gpio_tab[GPIO0][10].in_out = GPIO_OUT;
1123 gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
1125 /* EBC_CS_N(4) - GPIO0_9 */
1126 gpio_tab[GPIO0][9].in_out = GPIO_OUT;
1127 gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
1130 /*----------------------------------------------------------------------------+
1132 +------------------------------------------------------------------------------
1134 | Set UART Configuration in PowerPC440EP
1136 | +---------------------------------------------------------------------+
1137 | | Configuartion | Connector | Nb of pins | Pins | Associated |
1138 | | Number | Port Name | available | naming | CORE |
1139 | +-----------------+---------------+------------+--------+-------------+
1140 | | L1 | Port_A | 8 | UART | UART core 0 |
1141 | +-----------------+---------------+------------+--------+-------------+
1142 | | L2 | Port_A | 4 | UART1 | UART core 0 |
1143 | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
1144 | +-----------------+---------------+------------+--------+-------------+
1145 | | L3 | Port_A | 4 | UART1 | UART core 0 |
1146 | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
1147 | | | Port_C | 2 | UART3 | UART core 2 |
1148 | +-----------------+---------------+------------+--------+-------------+
1149 | | | Port_A | 2 | UART1 | UART core 0 |
1150 | | L4 | Port_B | 2 | UART2 | UART core 1 |
1151 | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
1152 | | | Port_D | 2 | UART4 | UART core 3 |
1153 | +-----------------+---------------+------------+--------+-------------+
1157 | +------------------------------------------------------------------------------+
1158 | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
1159 | +---------+------------------+-----+-----------------+-----+-------------+-----+
1160 | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
1161 | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
1162 | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
1163 | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
1164 | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
1165 | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
1166 | +------------------------------------------------------------------------------+
1169 +----------------------------------------------------------------------------*/
1171 void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
1173 switch (uart_config)
1176 /* ----------------------------------------------------------------------- */
1177 /* L1 configuration: UART0 = 8 pins */
1178 /* ----------------------------------------------------------------------- */
1179 /* Update GPIO Configuration Table */
1180 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1181 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1183 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1184 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1186 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1187 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1189 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1190 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1192 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1193 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1195 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1196 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1201 /* ----------------------------------------------------------------------- */
1202 /* L2 configuration: UART0 = 4 pins */
1203 /* UART1 = 4 pins */
1204 /* ----------------------------------------------------------------------- */
1205 /* Update GPIO Configuration Table */
1206 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1207 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1209 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1210 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1212 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1213 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1215 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1216 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1218 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1219 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1221 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1222 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1227 /* ----------------------------------------------------------------------- */
1228 /* L3 configuration: UART0 = 4 pins */
1229 /* UART1 = 2 pins */
1230 /* UART2 = 2 pins */
1231 /* ----------------------------------------------------------------------- */
1232 /* Update GPIO Configuration Table */
1233 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1234 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1236 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1237 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1239 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1240 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1242 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1243 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1245 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1246 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1248 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1249 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1254 /* ----------------------------------------------------------------------- */
1255 /* L4 configuration: UART0 = 2 pins */
1256 /* UART1 = 2 pins */
1257 /* UART2 = 2 pins */
1258 /* UART3 = 2 pins */
1259 /* ----------------------------------------------------------------------- */
1260 /* Update GPIO Configuration Table */
1261 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1262 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1264 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1265 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1267 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1268 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1270 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1271 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1273 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1274 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1276 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1277 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1282 /* Unsupported UART configuration number */
1283 printf("ERROR - Unsupported UART configuration number.\n\n");
1290 /* Set input Selection Register on Alt_Receive for UART Input Core */
1291 out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1292 out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1293 out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1296 /*----------------------------------------------------------------------------+
1297 | update_ndfc_ios(void).
1298 +----------------------------------------------------------------------------*/
1299 void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1301 /* Update GPIO Configuration Table */
1302 gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
1303 gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
1305 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
1306 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1309 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
1310 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1314 /*----------------------------------------------------------------------------+
1315 | update_zii_ios(void).
1316 +----------------------------------------------------------------------------*/
1317 void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1319 /* Update GPIO Configuration Table */
1320 gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
1321 gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
1323 gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
1324 gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
1326 gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
1327 gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
1329 gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
1330 gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
1332 gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
1333 gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
1335 gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
1336 gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
1338 gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
1339 gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
1341 gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
1342 gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
1344 gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
1345 gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
1347 gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
1348 gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
1350 gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
1351 gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
1353 gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
1354 gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
1356 gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
1357 gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
1359 gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
1360 gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
1364 /*----------------------------------------------------------------------------+
1365 | update_uic_0_3_irq_ios().
1366 +----------------------------------------------------------------------------*/
1367 void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1369 gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
1370 gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1372 gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
1373 gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1375 gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
1376 gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1378 gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
1379 gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1382 /*----------------------------------------------------------------------------+
1383 | update_uic_4_9_irq_ios().
1384 +----------------------------------------------------------------------------*/
1385 void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1387 gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
1388 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1390 gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
1391 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1393 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
1394 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1396 gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
1397 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1399 gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
1400 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1403 /*----------------------------------------------------------------------------+
1404 | update_dma_a_b_ios().
1405 +----------------------------------------------------------------------------*/
1406 void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1408 gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
1409 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1411 gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
1412 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1414 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
1415 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1417 gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
1418 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1420 gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
1421 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1424 /*----------------------------------------------------------------------------+
1425 | update_dma_c_d_ios().
1426 +----------------------------------------------------------------------------*/
1427 void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1429 gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
1430 gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1432 gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
1433 gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1435 gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
1436 gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1438 gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
1439 gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1441 gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
1442 gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1444 gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
1445 gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1449 /*----------------------------------------------------------------------------+
1450 | update_ebc_master_ios().
1451 +----------------------------------------------------------------------------*/
1452 void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1454 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
1455 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1457 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1458 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1460 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
1461 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1463 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
1464 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1467 /*----------------------------------------------------------------------------+
1468 | update_usb2_device_ios().
1469 +----------------------------------------------------------------------------*/
1470 void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1472 gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
1473 gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1475 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
1476 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1478 gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
1479 gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1481 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
1482 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1484 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
1485 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1487 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
1488 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1490 gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
1491 gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1493 gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
1494 gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1498 /*----------------------------------------------------------------------------+
1499 | update_pci_patch_ios().
1500 +----------------------------------------------------------------------------*/
1501 void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
1503 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1504 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1507 /*----------------------------------------------------------------------------+
1508 | set_chip_gpio_configuration(unsigned char gpio_core,
1509 | gpio_param_s (*gpio_tab)[GPIO_MAX])
1510 | Put the core impacted by clock modification and sharing in reset.
1511 | Config the select registers to resolve the sharing depending of the config.
1512 | Configure the GPIO registers.
1514 +----------------------------------------------------------------------------*/
1515 void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
1517 unsigned char i=0, j=0, reg_offset = 0;
1518 unsigned long gpio_reg, gpio_core_add;
1520 /* GPIO config of the GPIOs 0 to 31 */
1521 for (i=0; i<GPIO_MAX; i++, j++)
1523 if (i == GPIO_MAX/2)
1529 gpio_core_add = gpio_tab[gpio_core][i].add;
1531 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1532 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1534 switch (gpio_tab[gpio_core][i].alt_nb)
1540 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1541 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1542 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1546 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1547 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1548 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1552 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1553 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1554 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1558 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1559 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1562 switch (gpio_tab[gpio_core][i].alt_nb)
1567 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1568 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1569 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1570 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1571 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1572 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1575 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1576 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1577 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1578 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1579 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1580 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1583 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1584 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1585 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1586 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1587 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1588 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1595 /*----------------------------------------------------------------------------+
1596 | force_bup_core_selection.
1597 +----------------------------------------------------------------------------*/
1598 void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1600 /* Pointer invalid */
1601 if (core_select_P == NULL)
1603 printf("Configuration invalid pointer 1\n");
1609 *(core_select_P+UART_CORE0) = CORE_SELECTED;
1610 *(core_select_P+UART_CORE1) = CORE_SELECTED;
1611 *(core_select_P+UART_CORE2) = CORE_SELECTED;
1612 *(core_select_P+UART_CORE3) = CORE_SELECTED;
1614 /* RMII Selection */
1615 *(core_select_P+RMII_SEL) = CORE_SELECTED;
1617 /* External Interrupt 0-9 selection */
1618 *(core_select_P+UIC_0_3) = CORE_SELECTED;
1619 *(core_select_P+UIC_4_9) = CORE_SELECTED;
1621 *(core_select_P+SCP_CORE) = CORE_SELECTED;
1622 *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
1623 *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
1624 *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
1626 if (is_nand_selected()) {
1627 *(core_select_P+NAND_FLASH) = CORE_SELECTED;
1630 *config_val_P = CONFIG_IS_VALID;
1634 /*----------------------------------------------------------------------------+
1635 | configure_ppc440ep_pins.
1636 +----------------------------------------------------------------------------*/
1637 void configure_ppc440ep_pins(void)
1639 uart_config_nb_t uart_configuration;
1640 config_validity_t config_val = CONFIG_IS_INVALID;
1642 /* Create Core Selection Table */
1643 core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1645 CORE_NOT_SELECTED, /* IIC_CORE, */
1646 CORE_NOT_SELECTED, /* SPC_CORE, */
1647 CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
1648 CORE_NOT_SELECTED, /* UIC_4_9, */
1649 CORE_NOT_SELECTED, /* USB2_HOST, */
1650 CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
1651 CORE_NOT_SELECTED, /* USB2_DEVICE, */
1652 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
1653 CORE_NOT_SELECTED, /* USB1_DEVICE, */
1654 CORE_NOT_SELECTED, /* EBC_MASTER, */
1655 CORE_NOT_SELECTED, /* NAND_FLASH, */
1656 CORE_NOT_SELECTED, /* UART_CORE0, */
1657 CORE_NOT_SELECTED, /* UART_CORE1, */
1658 CORE_NOT_SELECTED, /* UART_CORE2, */
1659 CORE_NOT_SELECTED, /* UART_CORE3, */
1660 CORE_NOT_SELECTED, /* MII_SEL, */
1661 CORE_NOT_SELECTED, /* RMII_SEL, */
1662 CORE_NOT_SELECTED, /* SMII_SEL, */
1663 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
1664 CORE_NOT_SELECTED, /* UIC_0_3 */
1665 CORE_NOT_SELECTED, /* USB1_HOST */
1666 CORE_NOT_SELECTED /* PCI_PATCH */
1669 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
1671 /* Table Default Initialisation + FPGA Access */
1672 init_default_gpio(gpio_tab);
1673 set_chip_gpio_configuration(GPIO0, gpio_tab);
1674 set_chip_gpio_configuration(GPIO1, gpio_tab);
1677 force_bup_core_selection(ppc440ep_core_selection, &config_val);
1678 #if 0 /* test-only */
1679 /* If we are running PIBS 1, force known configuration */
1680 update_core_selection_table(ppc440ep_core_selection, &config_val);
1683 /*----------------------------------------------------------------------------+
1684 | SDR + ios table update + fpga initialization
1685 +----------------------------------------------------------------------------*/
1686 unsigned long sdr0_pfc1 = 0;
1687 unsigned long sdr0_usb0 = 0;
1688 unsigned long sdr0_mfr = 0;
1690 /* PCI Always selected */
1693 if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1695 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1696 iic1_selection_in_fpga();
1700 if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1702 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1703 scp_selection_in_fpga();
1706 /* UIC 0:3 Selection */
1707 if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1709 update_uic_0_3_irq_ios(gpio_tab);
1710 dma_a_b_unselect_in_fpga();
1713 /* UIC 4:9 Selection */
1714 if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1716 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
1717 update_uic_4_9_irq_ios(gpio_tab);
1720 /* DMA AB Selection */
1721 if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1723 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
1724 update_dma_a_b_ios(gpio_tab);
1725 dma_a_b_selection_in_fpga();
1728 /* DMA CD Selection */
1729 if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1731 update_dma_c_d_ios(gpio_tab);
1732 dma_c_d_selection_in_fpga();
1735 /* EBC Master Selection */
1736 if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1738 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1739 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1740 update_ebc_master_ios(gpio_tab);
1743 /* PCI Patch Enable */
1744 if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1746 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1747 update_pci_patch_ios(gpio_tab);
1750 /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1751 if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1753 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1754 printf("Invalid configuration => USB2 Host selected\n");
1757 /*usb2_host_selection_in_fpga(); */
1760 /* USB2.0 Device Selection */
1761 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1763 update_usb2_device_ios(gpio_tab);
1764 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1765 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1767 mfsdr(SDR0_USB0, sdr0_usb0);
1768 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1769 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
1770 mtsdr(SDR0_USB0, sdr0_usb0);
1772 usb2_device_selection_in_fpga();
1775 /* USB1.1 Device Selection */
1776 if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1778 mfsdr(SDR0_USB0, sdr0_usb0);
1779 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1780 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
1781 mtsdr(SDR0_USB0, sdr0_usb0);
1784 /* USB1.1 Host Selection */
1785 if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1787 mfsdr(SDR0_USB0, sdr0_usb0);
1788 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1789 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
1790 mtsdr(SDR0_USB0, sdr0_usb0);
1793 /* NAND Flash Selection */
1794 if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
1796 update_ndfc_ios(gpio_tab);
1798 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
1799 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
1800 SDR0_CUST0_NDFC_ENABLE |
1801 SDR0_CUST0_NDFC_BW_8_BIT |
1802 SDR0_CUST0_NDFC_ARE_MASK |
1803 SDR0_CUST0_CHIPSELGAT_EN1 |
1804 SDR0_CUST0_CHIPSELGAT_EN2);
1806 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
1807 SDR0_CUST0_NDFC_ENABLE |
1808 SDR0_CUST0_NDFC_BW_8_BIT |
1809 SDR0_CUST0_NDFC_ARE_MASK |
1810 SDR0_CUST0_CHIPSELGAT_EN0 |
1811 SDR0_CUST0_CHIPSELGAT_EN2);
1814 ndfc_selection_in_fpga();
1818 /* Set Mux on EMAC */
1819 mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL);
1823 if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
1825 update_zii_ios(gpio_tab);
1826 mfsdr(SDR0_MFR, sdr0_mfr);
1827 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
1828 mtsdr(SDR0_MFR, sdr0_mfr);
1830 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
1833 /* RMII Selection */
1834 if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
1836 update_zii_ios(gpio_tab);
1837 mfsdr(SDR0_MFR, sdr0_mfr);
1838 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
1839 mtsdr(SDR0_MFR, sdr0_mfr);
1841 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
1844 /* SMII Selection */
1845 if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
1847 update_zii_ios(gpio_tab);
1848 mfsdr(SDR0_MFR, sdr0_mfr);
1849 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
1850 mtsdr(SDR0_MFR, sdr0_mfr);
1852 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
1855 /* UART Selection */
1856 uart_configuration = get_uart_configuration();
1857 switch (uart_configuration)
1859 case L1: /* L1 Selection */
1860 /* UART0 8 pins Only */
1861 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
1862 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
1863 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
1865 case L2: /* L2 Selection */
1866 /* UART0 and UART1 4 pins */
1867 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1868 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1869 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1871 case L3: /* L3 Selection */
1872 /* UART0 4 pins, UART1 and UART2 2 pins */
1873 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1874 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1875 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1877 case L4: /* L4 Selection */
1878 /* UART0, UART1, UART2 and UART3 2 pins */
1879 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
1880 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1881 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1884 update_uart_ios(uart_configuration, gpio_tab);
1886 /* UART Selection in all cases */
1887 uart_selection_in_fpga(uart_configuration);
1889 /* Packet Reject Function Available */
1890 if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
1892 /* Set UPR Bit in SDR0_PFC1 Register */
1893 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
1896 /* Packet Reject Function Enable */
1897 if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
1899 mfsdr(SDR0_MFR, sdr0_mfr);
1900 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
1901 mtsdr(SDR0_MFR, sdr0_mfr);
1904 /* Perform effective access to hardware */
1905 mtsdr(SDR0_PFC1, sdr0_pfc1);
1906 set_chip_gpio_configuration(GPIO0, gpio_tab);
1907 set_chip_gpio_configuration(GPIO1, gpio_tab);
1909 /* USB2.0 Device Reset must be done after GPIO setting */
1910 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1911 usb2_device_reset_through_fpga();