3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
26 #include <spd_sdram.h>
30 void ext_bus_cntlr_init(void);
31 void configure_ppc440ep_pins(void);
33 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
35 { /* GPIO Alternate1 Alternate2 Alternate3 */
38 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
39 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
40 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
41 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
42 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
43 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
44 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
45 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
46 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
47 { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
48 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
49 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
50 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
51 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
52 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
53 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
54 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
55 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
56 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
57 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
58 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
59 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
60 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
61 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
62 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
63 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
64 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
65 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
66 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
67 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
68 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
69 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
73 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
74 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
75 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
76 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
77 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
78 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
79 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
80 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
81 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
82 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
83 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
84 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
85 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
86 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
87 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
88 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
89 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
90 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
91 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
92 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
93 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
94 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
95 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
96 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
97 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
98 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
99 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
100 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
101 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
102 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
103 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
104 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
109 /*----------------------------------------------------------------------------+
110 | EBC Devices Characteristics
111 | Peripheral Bank Access Parameters - EBC0_BnAP
112 | Peripheral Bank Configuration Register - EBC0_BnCR
113 +----------------------------------------------------------------------------*/
115 #define EBC0_BNAP_SMALL_FLASH EBC0_BNAP_BME_DISABLED | \
116 EBC0_BNAP_TWT_ENCODE(6) | \
117 EBC0_BNAP_CSN_ENCODE(0) | \
118 EBC0_BNAP_OEN_ENCODE(1) | \
119 EBC0_BNAP_WBN_ENCODE(1) | \
120 EBC0_BNAP_WBF_ENCODE(3) | \
121 EBC0_BNAP_TH_ENCODE(1) | \
122 EBC0_BNAP_RE_ENABLED | \
123 EBC0_BNAP_SOR_DELAYED | \
124 EBC0_BNAP_BEM_WRITEONLY | \
125 EBC0_BNAP_PEN_DISABLED
127 #define EBC0_BNCR_SMALL_FLASH_CS0 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
132 #define EBC0_BNCR_SMALL_FLASH_CS4 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
137 /* Large Flash or SRAM */
138 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM EBC0_BNAP_BME_DISABLED | \
139 EBC0_BNAP_TWT_ENCODE(8) | \
140 EBC0_BNAP_CSN_ENCODE(0) | \
141 EBC0_BNAP_OEN_ENCODE(1) | \
142 EBC0_BNAP_WBN_ENCODE(1) | \
143 EBC0_BNAP_WBF_ENCODE(1) | \
144 EBC0_BNAP_TH_ENCODE(2) | \
145 EBC0_BNAP_SOR_DELAYED | \
147 EBC0_BNAP_PEN_DISABLED
149 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
155 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
161 #define EBC0_BNAP_NVRAM_FPGA EBC0_BNAP_BME_DISABLED | \
162 EBC0_BNAP_TWT_ENCODE(9) | \
163 EBC0_BNAP_CSN_ENCODE(0) | \
164 EBC0_BNAP_OEN_ENCODE(1) | \
165 EBC0_BNAP_WBN_ENCODE(1) | \
166 EBC0_BNAP_WBF_ENCODE(0) | \
167 EBC0_BNAP_TH_ENCODE(2) | \
168 EBC0_BNAP_RE_ENABLED | \
169 EBC0_BNAP_SOR_DELAYED | \
170 EBC0_BNAP_BEM_WRITEONLY | \
171 EBC0_BNAP_PEN_DISABLED
173 #define EBC0_BNCR_NVRAM_FPGA_CS5 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
179 #define EBC0_BNAP_NAND_FLASH EBC0_BNAP_BME_DISABLED | \
180 EBC0_BNAP_TWT_ENCODE(3) | \
181 EBC0_BNAP_CSN_ENCODE(0) | \
182 EBC0_BNAP_OEN_ENCODE(0) | \
183 EBC0_BNAP_WBN_ENCODE(0) | \
184 EBC0_BNAP_WBF_ENCODE(0) | \
185 EBC0_BNAP_TH_ENCODE(1) | \
186 EBC0_BNAP_RE_ENABLED | \
187 EBC0_BNAP_SOR_NOT_DELAYED | \
189 EBC0_BNAP_PEN_DISABLED
192 #define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
195 #define EBC0_BNCR_NAND_FLASH_CS1 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
200 #define EBC0_BNCR_NAND_FLASH_CS2 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
206 #define EBC0_BNCR_NAND_FLASH_CS3 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
211 int board_early_init_f(void)
213 ext_bus_cntlr_init();
215 /*--------------------------------------------------------------------
216 * Setup the interrupt controller polarities, triggers, etc.
217 *-------------------------------------------------------------------*/
218 mtdcr(uic0sr, 0xffffffff); /* clear all */
219 mtdcr(uic0er, 0x00000000); /* disable all */
220 mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
221 mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
222 mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
223 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
224 mtdcr(uic0sr, 0xffffffff); /* clear all */
226 mtdcr(uic1sr, 0xffffffff); /* clear all */
227 mtdcr(uic1er, 0x00000000); /* disable all */
228 mtdcr(uic1cr, 0x00000000); /* all non-critical */
229 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
230 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
231 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
232 mtdcr(uic1sr, 0xffffffff); /* clear all */
234 /*--------------------------------------------------------------------
235 * Setup the GPIO pins
236 *-------------------------------------------------------------------*/
237 out32(GPIO0_OSRL, 0x00000400);
238 out32(GPIO0_OSRH, 0x00000000);
239 out32(GPIO0_TSRL, 0x00000400);
240 out32(GPIO0_TSRH, 0x00000000);
241 out32(GPIO0_ISR1L, 0x00000000);
242 out32(GPIO0_ISR1H, 0x00000000);
243 out32(GPIO0_ISR2L, 0x00000000);
244 out32(GPIO0_ISR2H, 0x00000000);
245 out32(GPIO0_ISR3L, 0x00000000);
246 out32(GPIO0_ISR3H, 0x00000000);
248 out32(GPIO1_OSRL, 0x0C380000);
249 out32(GPIO1_OSRH, 0x00000000);
250 out32(GPIO1_TSRL, 0x0C380000);
251 out32(GPIO1_TSRH, 0x00000000);
252 out32(GPIO1_ISR1L, 0x0FC30000);
253 out32(GPIO1_ISR1H, 0x00000000);
254 out32(GPIO1_ISR2L, 0x0C010000);
255 out32(GPIO1_ISR2H, 0x00000000);
256 out32(GPIO1_ISR3L, 0x01400000);
257 out32(GPIO1_ISR3H, 0x00000000);
259 configure_ppc440ep_pins();
267 unsigned char *s = getenv("serial#");
269 get_sys_info(&sysinfo);
271 printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
278 printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
279 printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
280 printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
281 printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
282 printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
287 /*************************************************************************
289 * fixed_sdram_init -- Bamboo has one bank onboard sdram (plus DIMM)
291 * Fixed memory is composed of :
292 * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
293 * 13 row add bits, 10 column add bits (but 12 row used only).
294 * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
295 * 12 row add bits, 10 column add bits.
296 * Prepare a subset (only the used ones) of SPD data
298 * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
299 * the corresponding bank is divided by 2 due to number of Row addresses
300 * 12 in the ECC module
302 * Assumes: 64 MB, ECC, non-registered
305 ************************************************************************/
306 void fixed_sdram_init(void)
309 * clear this first, if the DDR is enabled by a debugger
310 * then you can not make changes.
312 mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
314 /*--------------------------------------------------------------------
315 * Setup for board-specific specific mem
316 *------------------------------------------------------------------*/
318 * Following for CAS Latency = 2.5 @ 133 MHz PLB
320 mtsdram(mem_b0cr, 0x00082001);
321 mtsdram(mem_b1cr, 0x00000000);
322 mtsdram(mem_b2cr, 0x00000000);
323 mtsdram(mem_b3cr, 0x00000000);
326 long int initdram (int board_type)
331 * First init bank0 (onboard sdram) and then configure the DIMM-slots
334 dram_size = spd_sdram (0);
339 #if defined(CFG_DRAM_TEST)
342 unsigned long *mem = (unsigned long *)0;
343 const unsigned long kend = (1024 / sizeof(unsigned long));
348 for (k = 0; k < CFG_KBYTES_SDRAM;
349 ++k, mem += (1024 / sizeof(unsigned long))) {
350 if ((k & 1023) == 0) {
351 printf("%3d MB\r", k / 1024);
354 memset(mem, 0xaaaaaaaa, 1024);
355 for (n = 0; n < kend; ++n) {
356 if (mem[n] != 0xaaaaaaaa) {
357 printf("SDRAM test fails at: %08x\n",
363 memset(mem, 0x55555555, 1024);
364 for (n = 0; n < kend; ++n) {
365 if (mem[n] != 0x55555555) {
366 printf("SDRAM test fails at: %08x\n",
372 printf("SDRAM test passes\n");
377 /*************************************************************************
380 * This routine is called just prior to registering the hose and gives
381 * the board the opportunity to check things. Returning a value of zero
382 * indicates that things are bad & PCI initialization should be aborted.
384 * Different boards may wish to customize the pci controller structure
385 * (add regions, override default access routines, etc) or perform
386 * certain pre-initialization actions.
388 ************************************************************************/
389 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
390 int pci_pre_init(struct pci_controller *hose)
395 /*--------------------------------------------------------------------------+
396 * Bamboo is always configured as the host & requires the
397 * PCI arbiter to be enabled.
398 *--------------------------------------------------------------------------*/
399 mfsdr(sdr_sdstp1, strap);
400 if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
401 printf("PCI: SDR0_STRP1[PAE] not set.\n");
402 printf("PCI: Configuration aborted.\n");
406 /*-------------------------------------------------------------------------+
407 | Set priority for all PLB3 devices to 0.
408 | Set PLB3 arbiter to fair mode.
409 +-------------------------------------------------------------------------*/
410 mfsdr(sdr_amp1, addr);
411 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
412 addr = mfdcr(plb3_acr);
413 mtdcr(plb3_acr, addr | 0x80000000);
415 /*-------------------------------------------------------------------------+
416 | Set priority for all PLB4 devices to 0.
417 +-------------------------------------------------------------------------*/
418 mfsdr(sdr_amp0, addr);
419 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
420 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
421 mtdcr(plb4_acr, addr);
423 /*-------------------------------------------------------------------------+
424 | Set Nebula PLB4 arbiter to fair mode.
425 +-------------------------------------------------------------------------*/
427 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
428 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
429 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
430 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
431 mtdcr(plb0_acr, addr);
434 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
435 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
436 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
437 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
438 mtdcr(plb1_acr, addr);
442 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
444 /*************************************************************************
447 * The bootstrap configuration provides default settings for the pci
448 * inbound map (PIM). But the bootstrap config choices are limited and
449 * may not be sufficient for a given board.
451 ************************************************************************/
452 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
453 void pci_target_init(struct pci_controller *hose)
455 /*--------------------------------------------------------------------------+
456 * Set up Direct MMIO registers
457 *--------------------------------------------------------------------------*/
458 /*--------------------------------------------------------------------------+
459 | PowerPC440 EP PCI Master configuration.
460 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
461 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
462 | Use byte reversed out routines to handle endianess.
463 | Make this region non-prefetchable.
464 +--------------------------------------------------------------------------*/
465 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
466 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
467 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
468 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
469 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
471 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
472 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
473 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
474 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
475 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
477 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
478 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
479 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
480 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
482 /*--------------------------------------------------------------------------+
483 * Set up Configuration registers
484 *--------------------------------------------------------------------------*/
486 /* Program the board's subsystem id/vendor id */
487 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
488 CFG_PCI_SUBSYS_VENDORID);
489 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
491 /* Configure command register as bus master */
492 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
494 /* 240nS PCI clock */
495 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
497 /* No error reporting */
498 pci_write_config_word(0, PCI_ERREN, 0);
500 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
503 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
505 /*************************************************************************
508 ************************************************************************/
509 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
510 void pci_master_init(struct pci_controller *hose)
512 unsigned short temp_short;
514 /*--------------------------------------------------------------------------+
515 | Write the PowerPC440 EP PCI Configuration regs.
516 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
517 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
518 +--------------------------------------------------------------------------*/
519 pci_read_config_word(0, PCI_COMMAND, &temp_short);
520 pci_write_config_word(0, PCI_COMMAND,
521 temp_short | PCI_COMMAND_MASTER |
524 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
526 /*************************************************************************
529 * This routine is called to determine if a pci scan should be
530 * performed. With various hardware environments (especially cPCI and
531 * PPMC) it's insufficient to depend on the state of the arbiter enable
532 * bit in the strap register, or generic host/adapter assumptions.
534 * Rather than hard-code a bad assumption in the general 440 code, the
535 * 440 pci code requires the board to decide at runtime.
537 * Return 0 for adapter mode, non-zero for host (monarch) mode.
540 ************************************************************************/
541 #if defined(CONFIG_PCI)
542 int is_pci_host(struct pci_controller *hose)
544 /* Bamboo is always configured as host. */
547 #endif /* defined(CONFIG_PCI) */
549 /*----------------------------------------------------------------------------+
550 | is_powerpc440ep_pass1.
551 +----------------------------------------------------------------------------*/
552 int is_powerpc440ep_pass1(void)
558 if (pvr == PVR_POWERPC_440EP_PASS1)
560 else if (pvr == PVR_POWERPC_440EP_PASS2)
563 printf("brdutil error 3\n");
571 /*----------------------------------------------------------------------------+
573 +----------------------------------------------------------------------------*/
574 int is_nand_selected(void)
576 return FALSE; /* test-only */
579 /*----------------------------------------------------------------------------+
580 | config_on_ebc_cs4_is_small_flash => from EPLD
581 +----------------------------------------------------------------------------*/
582 unsigned char config_on_ebc_cs4_is_small_flash(void)
584 /* Not implemented yet => returns constant value */
588 /*----------------------------------------------------------------------------+
589 | Ext_bus_cntlr_init.
590 | Initialize the external bus controller
591 +----------------------------------------------------------------------------*/
592 void ext_bus_cntlr_init(void)
594 unsigned long sdr0_pstrp0, sdr0_sdstp1;
595 unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
596 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
597 unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
598 unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
599 unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
600 unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
601 unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
604 /*-------------------------------------------------------------------------+
606 | PART 1 : Initialize EBC Bank 5
607 | ==============================
608 | Bank5 is always associated to the NVRAM/EPLD.
609 | It has to be initialized prior to other banks settings computation since
610 | some board registers values may be needed
612 +-------------------------------------------------------------------------*/
614 mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
615 mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
617 /*-------------------------------------------------------------------------+
619 | PART 2 : Determine which boot device was selected
620 | =========================================
622 | Read Pin Strap Register in PPC440EP
623 | In case of boot from IIC, read Serial Device Strap Register1
625 | Result can either be :
626 | - Boot from EBC 8bits => SMALL FLASH
627 | - Boot from EBC 16bits => Large Flash or SRAM
628 | - Boot from NAND Flash
631 +-------------------------------------------------------------------------*/
632 /* Read Pin Strap Register in PPC440EP */
633 mfsdr(sdr_pstrp0, sdr0_pstrp0);
634 bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
636 /*-------------------------------------------------------------------------+
638 +-------------------------------------------------------------------------*/
639 if (is_powerpc440ep_pass1() == TRUE) {
640 switch(bootstrap_settings) {
641 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
642 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
643 /* Boot from Small Flash */
644 computed_boot_device = BOOT_FROM_SMALL_FLASH;
646 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
647 /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
649 computed_boot_device = BOOT_FROM_PCI;
652 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
653 /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
654 /* Boot from Nand Flash */
655 computed_boot_device = BOOT_FROM_NAND_FLASH0;
658 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
659 /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
660 /* Boot from Small Flash */
661 computed_boot_device = BOOT_FROM_SMALL_FLASH;
664 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
665 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
666 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
667 /* Read Serial Device Strap Register1 in PPC440EP */
668 mfsdr(sdr_sdstp1, sdr0_sdstp1);
669 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
670 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
672 switch(boot_selection) {
673 case SDR0_SDSTP1_BOOT_SEL_EBC:
674 switch(ebc_boot_size) {
675 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
676 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
678 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
679 computed_boot_device = BOOT_FROM_SMALL_FLASH;
684 case SDR0_SDSTP1_BOOT_SEL_PCI:
685 computed_boot_device = BOOT_FROM_PCI;
688 case SDR0_SDSTP1_BOOT_SEL_NDFC:
689 computed_boot_device = BOOT_FROM_NAND_FLASH0;
696 /*-------------------------------------------------------------------------+
698 +-------------------------------------------------------------------------*/
700 switch(bootstrap_settings) {
701 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
702 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
703 /* Boot from Small Flash */
704 computed_boot_device = BOOT_FROM_SMALL_FLASH;
706 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
707 /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
709 computed_boot_device = BOOT_FROM_PCI;
712 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
713 /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
714 /* Boot from Nand Flash */
715 computed_boot_device = BOOT_FROM_NAND_FLASH0;
718 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
719 /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
720 /* Boot from Large Flash or SRAM */
721 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
724 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
725 /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
726 /* Boot from Large Flash or SRAM */
727 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
730 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
731 /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
733 computed_boot_device = BOOT_FROM_PCI;
736 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
737 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
738 /* Default Strap Settings 5-7 */
739 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
740 /* Read Serial Device Strap Register1 in PPC440EP */
741 mfsdr(sdr_sdstp1, sdr0_sdstp1);
742 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
743 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
745 switch(boot_selection) {
746 case SDR0_SDSTP1_BOOT_SEL_EBC:
747 switch(ebc_boot_size) {
748 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
749 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
751 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
752 computed_boot_device = BOOT_FROM_SMALL_FLASH;
757 case SDR0_SDSTP1_BOOT_SEL_PCI:
758 computed_boot_device = BOOT_FROM_PCI;
761 case SDR0_SDSTP1_BOOT_SEL_NDFC:
762 computed_boot_device = BOOT_FROM_NAND_FLASH0;
769 /*-------------------------------------------------------------------------+
771 | PART 3 : Compute EBC settings depending on selected boot device
772 | ====== ======================================================
774 | Resulting EBC init will be among following configurations :
776 | - Boot from EBC 8bits => boot from SMALL FLASH selected
777 | EBC-CS0 = Small Flash
778 | EBC-CS1,2,3 = NAND Flash or
779 | Exp.Slot depending on Soft Config
780 | EBC-CS4 = SRAM/Large Flash or
781 | Large Flash/SRAM depending on jumpers
782 | EBC-CS5 = NVRAM / EPLD
784 | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
785 | EBC-CS0 = SRAM/Large Flash or
786 | Large Flash/SRAM depending on jumpers
787 | EBC-CS1,2,3 = NAND Flash or
788 | Exp.Slot depending on Software Configuration
789 | EBC-CS4 = Small Flash
790 | EBC-CS5 = NVRAM / EPLD
792 | - Boot from NAND Flash
793 | EBC-CS0 = NAND Flash0
794 | EBC-CS1,2,3 = NAND Flash1
795 | EBC-CS4 = SRAM/Large Flash or
796 | Large Flash/SRAM depending on jumpers
797 | EBC-CS5 = NVRAM / EPLD
801 | EBC-CS1,2,3 = NAND Flash or
802 | Exp.Slot depending on Software Configuration
803 | EBC-CS4 = SRAM/Large Flash or
804 | Large Flash/SRAM or
805 | Small Flash depending on jumpers
806 | EBC-CS5 = NVRAM / EPLD
808 +-------------------------------------------------------------------------*/
810 switch(computed_boot_device) {
811 /*------------------------------------------------------------------------- */
812 case BOOT_FROM_SMALL_FLASH:
813 /*------------------------------------------------------------------------- */
814 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
815 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
816 if ((is_nand_selected()) == TRUE) {
818 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
819 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
820 /*ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
821 ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
822 ebc0_cs3_bnap_value = EBC0_BNAP_NAND_FLASH;
823 ebc0_cs3_bncr_value = EBC0_BNCR_NAND_FLASH_CS3;*/
824 ebc0_cs2_bnap_value = 0;
825 ebc0_cs2_bncr_value = 0;
826 ebc0_cs3_bnap_value = 0;
827 ebc0_cs3_bncr_value = 0;
830 ebc0_cs1_bnap_value = 0;
831 ebc0_cs1_bncr_value = 0;
832 ebc0_cs2_bnap_value = 0;
833 ebc0_cs2_bncr_value = 0;
834 ebc0_cs3_bnap_value = 0;
835 ebc0_cs3_bncr_value = 0;
837 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
838 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
842 /*------------------------------------------------------------------------- */
843 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
844 /*------------------------------------------------------------------------- */
845 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
846 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
847 if ((is_nand_selected()) == TRUE) {
849 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
850 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
851 ebc0_cs2_bnap_value = 0;
852 ebc0_cs2_bncr_value = 0;
853 ebc0_cs3_bnap_value = 0;
854 ebc0_cs3_bncr_value = 0;
857 ebc0_cs1_bnap_value = 0;
858 ebc0_cs1_bncr_value = 0;
859 ebc0_cs2_bnap_value = 0;
860 ebc0_cs2_bncr_value = 0;
861 ebc0_cs3_bnap_value = 0;
862 ebc0_cs3_bncr_value = 0;
864 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
865 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
869 /*------------------------------------------------------------------------- */
870 case BOOT_FROM_NAND_FLASH0:
871 /*------------------------------------------------------------------------- */
872 ebc0_cs0_bnap_value = 0;
873 ebc0_cs0_bncr_value = 0;
875 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
876 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
877 ebc0_cs2_bnap_value = 0;
878 ebc0_cs2_bncr_value = 0;
879 ebc0_cs3_bnap_value = 0;
880 ebc0_cs3_bncr_value = 0;
882 /* Large Flash or SRAM */
883 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
884 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
888 /*------------------------------------------------------------------------- */
890 /*------------------------------------------------------------------------- */
891 ebc0_cs0_bnap_value = 0;
892 ebc0_cs0_bncr_value = 0;
894 if ((is_nand_selected()) == TRUE) {
896 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
897 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
898 ebc0_cs2_bnap_value = 0;
899 ebc0_cs2_bncr_value = 0;
900 ebc0_cs3_bnap_value = 0;
901 ebc0_cs3_bncr_value = 0;
904 ebc0_cs1_bnap_value = 0;
905 ebc0_cs1_bncr_value = 0;
906 ebc0_cs2_bnap_value = 0;
907 ebc0_cs2_bncr_value = 0;
908 ebc0_cs3_bnap_value = 0;
909 ebc0_cs3_bncr_value = 0;
912 if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
914 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
915 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
917 /* Large Flash or SRAM */
918 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
919 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
924 /*------------------------------------------------------------------------- */
925 case BOOT_DEVICE_UNKNOWN:
926 /*------------------------------------------------------------------------- */
933 /*-------------------------------------------------------------------------+
934 | Initialize EBC CONFIG
935 +-------------------------------------------------------------------------*/
936 mtdcr(ebccfga, xbcfg);
937 mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
938 EBC0_CFG_PTD_ENABLED |
939 EBC0_CFG_RTC_2048PERCLK |
942 EBC0_CFG_CSTC_DRIVEN |
945 EBC0_CFG_PME_DISABLED |
946 EBC0_CFG_PMT_ENCODE(0) );
948 /*-------------------------------------------------------------------------+
949 | Initialize EBC Bank 0-4
950 +-------------------------------------------------------------------------*/
952 mtebc(pb0ap, ebc0_cs0_bnap_value);
953 mtebc(pb0cr, ebc0_cs0_bncr_value);
955 mtebc(pb1ap, ebc0_cs1_bnap_value);
956 mtebc(pb1cr, ebc0_cs1_bncr_value);
958 mtebc(pb2ap, ebc0_cs2_bnap_value);
959 mtebc(pb2cr, ebc0_cs2_bncr_value);
961 mtebc(pb3ap, ebc0_cs3_bnap_value);
962 mtebc(pb3cr, ebc0_cs3_bncr_value);
964 mtebc(pb4ap, ebc0_cs4_bnap_value);
965 mtebc(pb4cr, ebc0_cs4_bncr_value);
971 /*----------------------------------------------------------------------------+
972 | get_uart_configuration.
973 +----------------------------------------------------------------------------*/
974 uart_config_nb_t get_uart_configuration(void)
976 return (L4); /* test-only */
979 /*----------------------------------------------------------------------------+
980 | set_phy_configuration_through_fpga => to EPLD
981 +----------------------------------------------------------------------------*/
982 void set_phy_configuration_through_fpga(zmii_config_t config)
985 unsigned long fpga_selection_reg;
987 fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
991 case ZMII_CONFIGURATION_IS_MII:
992 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
994 case ZMII_CONFIGURATION_IS_RMII:
995 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
997 case ZMII_CONFIGURATION_IS_SMII:
998 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
1000 case ZMII_CONFIGURATION_UNKNOWN:
1004 out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
1008 /*----------------------------------------------------------------------------+
1009 | scp_selection_in_fpga.
1010 +----------------------------------------------------------------------------*/
1011 void scp_selection_in_fpga(void)
1013 unsigned long fpga_selection_2_reg;
1015 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1016 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
1017 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1020 /*----------------------------------------------------------------------------+
1021 | iic1_selection_in_fpga.
1022 +----------------------------------------------------------------------------*/
1023 void iic1_selection_in_fpga(void)
1025 unsigned long fpga_selection_2_reg;
1027 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1028 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
1029 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1032 /*----------------------------------------------------------------------------+
1033 | dma_a_b_selection_in_fpga.
1034 +----------------------------------------------------------------------------*/
1035 void dma_a_b_selection_in_fpga(void)
1037 unsigned long fpga_selection_2_reg;
1039 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
1040 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1043 /*----------------------------------------------------------------------------+
1044 | dma_a_b_unselect_in_fpga.
1045 +----------------------------------------------------------------------------*/
1046 void dma_a_b_unselect_in_fpga(void)
1048 unsigned long fpga_selection_2_reg;
1050 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
1051 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1054 /*----------------------------------------------------------------------------+
1055 | dma_c_d_selection_in_fpga.
1056 +----------------------------------------------------------------------------*/
1057 void dma_c_d_selection_in_fpga(void)
1059 unsigned long fpga_selection_2_reg;
1061 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
1062 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1065 /*----------------------------------------------------------------------------+
1066 | dma_c_d_unselect_in_fpga.
1067 +----------------------------------------------------------------------------*/
1068 void dma_c_d_unselect_in_fpga(void)
1070 unsigned long fpga_selection_2_reg;
1072 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
1073 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1076 /*----------------------------------------------------------------------------+
1077 | usb2_device_selection_in_fpga.
1078 +----------------------------------------------------------------------------*/
1079 void usb2_device_selection_in_fpga(void)
1081 unsigned long fpga_selection_1_reg;
1083 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
1084 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1087 /*----------------------------------------------------------------------------+
1088 | usb2_device_reset_through_fpga.
1089 +----------------------------------------------------------------------------*/
1090 void usb2_device_reset_through_fpga(void)
1092 /* Perform soft Reset pulse */
1093 unsigned long fpga_reset_reg;
1096 fpga_reset_reg = in8(FPGA_RESET_REG);
1097 out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1098 for (i=0; i<500; i++)
1100 out8(FPGA_RESET_REG,fpga_reset_reg);
1103 /*----------------------------------------------------------------------------+
1104 | usb2_host_selection_in_fpga.
1105 +----------------------------------------------------------------------------*/
1106 void usb2_host_selection_in_fpga(void)
1108 unsigned long fpga_selection_1_reg;
1110 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1111 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1114 /*----------------------------------------------------------------------------+
1115 | ndfc_selection_in_fpga.
1116 +----------------------------------------------------------------------------*/
1117 void ndfc_selection_in_fpga(void)
1119 unsigned long fpga_selection_1_reg;
1121 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1122 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
1123 /*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2; */
1124 /*fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS3; */
1125 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1128 /*----------------------------------------------------------------------------+
1129 | uart_selection_in_fpga.
1130 +----------------------------------------------------------------------------*/
1131 void uart_selection_in_fpga(uart_config_nb_t uart_config)
1134 unsigned char fpga_selection_3_reg;
1136 /* Read FPGA Reagister */
1137 fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1139 switch (uart_config)
1142 /* ----------------------------------------------------------------------- */
1143 /* L1 configuration: UART0 = 8 pins */
1144 /* ----------------------------------------------------------------------- */
1145 /* Configure FPGA */
1146 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1147 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
1148 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1153 /* ----------------------------------------------------------------------- */
1154 /* L2 configuration: UART0 = 4 pins */
1155 /* UART1 = 4 pins */
1156 /* ----------------------------------------------------------------------- */
1157 /* Configure FPGA */
1158 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1159 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
1160 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1165 /* ----------------------------------------------------------------------- */
1166 /* L3 configuration: UART0 = 4 pins */
1167 /* UART1 = 2 pins */
1168 /* UART2 = 2 pins */
1169 /* ----------------------------------------------------------------------- */
1170 /* Configure FPGA */
1171 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1172 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
1173 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1177 /* Configure FPGA */
1178 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1179 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
1180 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1185 /* Unsupported UART configuration number */
1194 /*----------------------------------------------------------------------------+
1196 +----------------------------------------------------------------------------*/
1197 void init_default_gpio(void)
1202 for(i=0; i<GPIO_MAX; i++)
1204 gpio_tab[GPIO0][i].add = GPIO0_BASE;
1205 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1206 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1210 for(i=0; i<GPIO_MAX; i++)
1212 gpio_tab[GPIO1][i].add = GPIO1_BASE;
1213 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1214 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1217 /* EBC_CS_N(5) - GPIO0_10 */
1218 gpio_tab[GPIO0][10].in_out = GPIO_OUT;
1219 gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
1221 /* EBC_CS_N(4) - GPIO0_9 */
1222 gpio_tab[GPIO0][9].in_out = GPIO_OUT;
1223 gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
1226 /*----------------------------------------------------------------------------+
1228 +------------------------------------------------------------------------------
1230 | Set UART Configuration in PowerPC440EP
1232 | +---------------------------------------------------------------------+
1233 | | Configuartion | Connector | Nb of pins | Pins | Associated |
1234 | | Number | Port Name | available | naming | CORE |
1235 | +-----------------+---------------+------------+--------+-------------+
1236 | | L1 | Port_A | 8 | UART | UART core 0 |
1237 | +-----------------+---------------+------------+--------+-------------+
1238 | | L2 | Port_A | 4 | UART1 | UART core 0 |
1239 | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
1240 | +-----------------+---------------+------------+--------+-------------+
1241 | | L3 | Port_A | 4 | UART1 | UART core 0 |
1242 | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
1243 | | | Port_C | 2 | UART3 | UART core 2 |
1244 | +-----------------+---------------+------------+--------+-------------+
1245 | | | Port_A | 2 | UART1 | UART core 0 |
1246 | | L4 | Port_B | 2 | UART2 | UART core 1 |
1247 | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
1248 | | | Port_D | 2 | UART4 | UART core 3 |
1249 | +-----------------+---------------+------------+--------+-------------+
1253 | +------------------------------------------------------------------------------+
1254 | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
1255 | +---------+------------------+-----+-----------------+-----+-------------+-----+
1256 | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
1257 | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
1258 | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
1259 | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
1260 | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
1261 | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
1262 | +------------------------------------------------------------------------------+
1265 +----------------------------------------------------------------------------*/
1267 void update_uart_ios(uart_config_nb_t uart_config)
1269 switch (uart_config)
1272 /* ----------------------------------------------------------------------- */
1273 /* L1 configuration: UART0 = 8 pins */
1274 /* ----------------------------------------------------------------------- */
1275 /* Update GPIO Configuration Table */
1276 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1277 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1279 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1280 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1282 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1283 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1285 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1286 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1288 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1289 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1291 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1292 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1297 /* ----------------------------------------------------------------------- */
1298 /* L2 configuration: UART0 = 4 pins */
1299 /* UART1 = 4 pins */
1300 /* ----------------------------------------------------------------------- */
1301 /* Update GPIO Configuration Table */
1302 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1303 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1305 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1306 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1308 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1309 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1311 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1312 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1314 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1315 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1317 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1318 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1323 /* ----------------------------------------------------------------------- */
1324 /* L3 configuration: UART0 = 4 pins */
1325 /* UART1 = 2 pins */
1326 /* UART2 = 2 pins */
1327 /* ----------------------------------------------------------------------- */
1328 /* Update GPIO Configuration Table */
1329 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1330 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1332 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1333 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1335 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1336 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1338 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1339 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1341 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1342 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1344 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1345 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1350 /* ----------------------------------------------------------------------- */
1351 /* L4 configuration: UART0 = 2 pins */
1352 /* UART1 = 2 pins */
1353 /* UART2 = 2 pins */
1354 /* UART3 = 2 pins */
1355 /* ----------------------------------------------------------------------- */
1356 /* Update GPIO Configuration Table */
1357 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1358 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1360 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1361 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1363 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1364 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1366 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1367 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1369 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1370 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1372 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1373 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1378 /* Unsupported UART configuration number */
1379 printf("ERROR - Unsupported UART configuration number.\n\n");
1386 /* Set input Selection Register on Alt_Receive for UART Input Core */
1387 out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1388 out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1389 out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1392 /*----------------------------------------------------------------------------+
1393 | update_ndfc_ios(void).
1394 +----------------------------------------------------------------------------*/
1395 void update_ndfc_ios(void)
1397 /* Update GPIO Configuration Table */
1398 gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
1399 gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
1402 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
1403 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1405 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
1406 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1410 /*----------------------------------------------------------------------------+
1411 | update_zii_ios(void).
1412 +----------------------------------------------------------------------------*/
1413 void update_zii_ios(void)
1415 /* Update GPIO Configuration Table */
1416 gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
1417 gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
1419 gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
1420 gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
1422 gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
1423 gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
1425 gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
1426 gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
1428 gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
1429 gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
1431 gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
1432 gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
1434 gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
1435 gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
1437 gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
1438 gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
1440 gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
1441 gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
1443 gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
1444 gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
1446 gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
1447 gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
1449 gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
1450 gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
1452 gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
1453 gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
1455 gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
1456 gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
1460 /*----------------------------------------------------------------------------+
1461 | update_uic_0_3_irq_ios().
1462 +----------------------------------------------------------------------------*/
1463 void update_uic_0_3_irq_ios(void)
1465 gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
1466 gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1468 gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
1469 gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1471 gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
1472 gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1474 gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
1475 gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1478 /*----------------------------------------------------------------------------+
1479 | update_uic_4_9_irq_ios().
1480 +----------------------------------------------------------------------------*/
1481 void update_uic_4_9_irq_ios(void)
1483 gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
1484 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1486 gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
1487 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1489 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
1490 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1492 gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
1493 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1495 gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
1496 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1499 /*----------------------------------------------------------------------------+
1500 | update_dma_a_b_ios().
1501 +----------------------------------------------------------------------------*/
1502 void update_dma_a_b_ios(void)
1504 gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
1505 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1507 gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
1508 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1510 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
1511 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1513 gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
1514 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1516 gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
1517 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1520 /*----------------------------------------------------------------------------+
1521 | update_dma_c_d_ios().
1522 +----------------------------------------------------------------------------*/
1523 void update_dma_c_d_ios(void)
1525 gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
1526 gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1528 gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
1529 gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1531 gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
1532 gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1534 gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
1535 gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1537 gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
1538 gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1540 gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
1541 gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1545 /*----------------------------------------------------------------------------+
1546 | update_ebc_master_ios().
1547 +----------------------------------------------------------------------------*/
1548 void update_ebc_master_ios(void)
1550 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
1551 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1553 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1554 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1556 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
1557 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1559 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
1560 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1563 /*----------------------------------------------------------------------------+
1564 | update_usb2_device_ios().
1565 +----------------------------------------------------------------------------*/
1566 void update_usb2_device_ios(void)
1568 gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
1569 gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1571 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
1572 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1574 gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
1575 gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1577 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
1578 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1580 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
1581 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1583 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
1584 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1586 gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
1587 gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1589 gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
1590 gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1594 /*----------------------------------------------------------------------------+
1595 | update_pci_patch_ios().
1596 +----------------------------------------------------------------------------*/
1597 void update_pci_patch_ios(void)
1599 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1600 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1603 /*----------------------------------------------------------------------------+
1604 | set_chip_gpio_configuration(unsigned char gpio_core)
1605 | Put the core impacted by clock modification and sharing in reset.
1606 | Config the select registers to resolve the sharing depending of the config.
1607 | Configure the GPIO registers.
1609 +----------------------------------------------------------------------------*/
1610 void set_chip_gpio_configuration(unsigned char gpio_core)
1612 unsigned char i=0, j=0, reg_offset = 0;
1613 unsigned long gpio_reg, gpio_core_add;
1615 /* GPIO config of the GPIOs 0 to 31 */
1616 for (i=0; i<GPIO_MAX; i++, j++)
1618 if (i == GPIO_MAX/2)
1624 gpio_core_add = gpio_tab[gpio_core][i].add;
1626 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1627 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1629 switch (gpio_tab[gpio_core][i].alt_nb)
1635 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1636 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1637 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1641 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1642 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1643 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1647 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1648 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1649 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1653 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1654 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1657 switch (gpio_tab[gpio_core][i].alt_nb)
1662 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1663 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1664 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1665 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1666 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1667 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1670 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1671 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1672 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1673 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1674 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1675 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1678 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1679 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1680 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1681 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1682 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1683 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1690 /*----------------------------------------------------------------------------+
1691 | force_bup_core_selection.
1692 +----------------------------------------------------------------------------*/
1693 void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1695 /* Pointer invalid */
1696 if (core_select_P == NULL)
1698 printf("Configuration invalid pointer 1\n");
1704 *(core_select_P+UART_CORE0) = CORE_SELECTED;
1705 *(core_select_P+UART_CORE1) = CORE_SELECTED;
1706 *(core_select_P+UART_CORE2) = CORE_SELECTED;
1707 *(core_select_P+UART_CORE3) = CORE_SELECTED;
1709 /* RMII Selection */
1710 *(core_select_P+RMII_SEL) = CORE_SELECTED;
1712 /* External Interrupt 0-9 selection */
1713 *(core_select_P+UIC_0_3) = CORE_SELECTED;
1714 *(core_select_P+UIC_4_9) = CORE_SELECTED;
1716 *(core_select_P+SCP_CORE) = CORE_SELECTED;
1717 *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
1718 *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
1719 *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
1721 *config_val_P = CONFIG_IS_VALID;
1725 /*----------------------------------------------------------------------------+
1726 | configure_ppc440ep_pins.
1727 +----------------------------------------------------------------------------*/
1728 void configure_ppc440ep_pins(void)
1730 uart_config_nb_t uart_configuration;
1731 config_validity_t config_val = CONFIG_IS_INVALID;
1733 /* Create Core Selection Table */
1734 core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1736 CORE_NOT_SELECTED, /* IIC_CORE, */
1737 CORE_NOT_SELECTED, /* SPC_CORE, */
1738 CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
1739 CORE_NOT_SELECTED, /* UIC_4_9, */
1740 CORE_NOT_SELECTED, /* USB2_HOST, */
1741 CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
1742 CORE_NOT_SELECTED, /* USB2_DEVICE, */
1743 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
1744 CORE_NOT_SELECTED, /* USB1_DEVICE, */
1745 CORE_NOT_SELECTED, /* EBC_MASTER, */
1746 CORE_NOT_SELECTED, /* NAND_FLASH, */
1747 CORE_NOT_SELECTED, /* UART_CORE0, */
1748 CORE_NOT_SELECTED, /* UART_CORE1, */
1749 CORE_NOT_SELECTED, /* UART_CORE2, */
1750 CORE_NOT_SELECTED, /* UART_CORE3, */
1751 CORE_NOT_SELECTED, /* MII_SEL, */
1752 CORE_NOT_SELECTED, /* RMII_SEL, */
1753 CORE_NOT_SELECTED, /* SMII_SEL, */
1754 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
1755 CORE_NOT_SELECTED, /* UIC_0_3 */
1756 CORE_NOT_SELECTED, /* USB1_HOST */
1757 CORE_NOT_SELECTED /* PCI_PATCH */
1761 /* Table Default Initialisation + FPGA Access */
1762 init_default_gpio();
1763 set_chip_gpio_configuration(GPIO0);
1764 set_chip_gpio_configuration(GPIO1);
1767 force_bup_core_selection(ppc440ep_core_selection, &config_val);
1768 #if 0 /* test-only */
1769 /* If we are running PIBS 1, force known configuration */
1770 update_core_selection_table(ppc440ep_core_selection, &config_val);
1773 /*----------------------------------------------------------------------------+
1774 | SDR + ios table update + fpga initialization
1775 +----------------------------------------------------------------------------*/
1776 unsigned long sdr0_pfc1 = 0;
1777 unsigned long sdr0_usb0 = 0;
1778 unsigned long sdr0_mfr = 0;
1780 /* PCI Always selected */
1783 if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1785 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1786 iic1_selection_in_fpga();
1790 if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1792 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1793 scp_selection_in_fpga();
1796 /* UIC 0:3 Selection */
1797 if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1799 update_uic_0_3_irq_ios();
1800 dma_a_b_unselect_in_fpga();
1803 /* UIC 4:9 Selection */
1804 if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1806 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
1807 update_uic_4_9_irq_ios();
1810 /* DMA AB Selection */
1811 if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1813 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
1814 update_dma_a_b_ios();
1815 dma_a_b_selection_in_fpga();
1818 /* DMA CD Selection */
1819 if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1821 update_dma_c_d_ios();
1822 dma_c_d_selection_in_fpga();
1825 /* EBC Master Selection */
1826 if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1828 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1829 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1830 update_ebc_master_ios();
1833 /* PCI Patch Enable */
1834 if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1836 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1837 update_pci_patch_ios();
1840 /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1841 if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1843 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1844 printf("Invalid configuration => USB2 Host selected\n");
1847 /*usb2_host_selection_in_fpga(); */
1850 /* USB2.0 Device Selection */
1851 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1853 update_usb2_device_ios();
1854 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1855 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1857 mfsdr(sdr_usb0, sdr0_usb0);
1858 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1859 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
1860 mtsdr(sdr_usb0, sdr0_usb0);
1862 usb2_device_selection_in_fpga();
1865 /* USB1.1 Device Selection */
1866 if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1868 mfsdr(sdr_usb0, sdr0_usb0);
1869 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1870 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
1871 mtsdr(sdr_usb0, sdr0_usb0);
1874 /* USB1.1 Host Selection */
1875 if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1877 mfsdr(sdr_usb0, sdr0_usb0);
1878 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1879 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
1880 mtsdr(sdr_usb0, sdr0_usb0);
1883 /* NAND Flash Selection */
1884 if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
1888 mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
1889 SDR0_CUST0_NDFC_ENABLE |
1890 SDR0_CUST0_NDFC_BW_8_BIT |
1891 SDR0_CUST0_NDFC_ARE_MASK |
1892 SDR0_CUST0_CHIPSELGAT_EN1 );
1893 /*SDR0_CUST0_CHIPSELGAT_EN2 ); */
1894 /*SDR0_CUST0_CHIPSELGAT_EN3 ); */
1896 ndfc_selection_in_fpga();
1900 /* Set Mux on EMAC */
1901 mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
1905 if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
1908 mfsdr(sdr_mfr, sdr0_mfr);
1909 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
1910 mtsdr(sdr_mfr, sdr0_mfr);
1912 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
1915 /* RMII Selection */
1916 if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
1919 mfsdr(sdr_mfr, sdr0_mfr);
1920 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
1921 mtsdr(sdr_mfr, sdr0_mfr);
1923 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
1926 /* SMII Selection */
1927 if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
1930 mfsdr(sdr_mfr, sdr0_mfr);
1931 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
1932 mtsdr(sdr_mfr, sdr0_mfr);
1934 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
1937 /* UART Selection */
1938 uart_configuration = get_uart_configuration();
1939 switch (uart_configuration)
1941 case L1: /* L1 Selection */
1942 /* UART0 8 pins Only */
1943 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
1944 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
1945 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
1947 case L2: /* L2 Selection */
1948 /* UART0 and UART1 4 pins */
1949 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1950 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1951 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1953 case L3: /* L3 Selection */
1954 /* UART0 4 pins, UART1 and UART2 2 pins */
1955 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1956 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1957 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1959 case L4: /* L4 Selection */
1960 /* UART0, UART1, UART2 and UART3 2 pins */
1961 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
1962 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1963 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1966 update_uart_ios(uart_configuration);
1968 /* UART Selection in all cases */
1969 uart_selection_in_fpga(uart_configuration);
1971 /* Packet Reject Function Available */
1972 if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
1974 /* Set UPR Bit in SDR0_PFC1 Register */
1975 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
1978 /* Packet Reject Function Enable */
1979 if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
1981 mfsdr(sdr_mfr, sdr0_mfr);
1982 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
1983 mtsdr(sdr_mfr, sdr0_mfr);
1986 /* Perform effective access to hardware */
1987 mtsdr(sdr_pfc1, sdr0_pfc1);
1988 set_chip_gpio_configuration(GPIO0);
1989 set_chip_gpio_configuration(GPIO1);
1991 /* USB2.0 Device Reset must be done after GPIO setting */
1992 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1993 usb2_device_reset_through_fpga();