2 * Bluestone board support
4 * Copyright (c) 2010, Applied Micro Circuits Corporation
5 * Author: Tirumala R Marri <tmarri@apm.com>
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/apm821xx.h>
13 #include <fdt_support.h>
15 #include <asm/processor.h>
18 #include <asm/ppc4xx-gpio.h>
20 int board_early_init_f(void)
23 * Setup the interrupt controller polarities, triggers, etc.
25 mtdcr(UIC0SR, 0xffffffff); /* clear all */
26 mtdcr(UIC0ER, 0x00000000); /* disable all */
27 mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
28 mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
29 mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
30 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
31 mtdcr(UIC0SR, 0xffffffff); /* clear all */
33 mtdcr(UIC1SR, 0xffffffff); /* clear all */
34 mtdcr(UIC1ER, 0x00000000); /* disable all */
35 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
36 mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
37 mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
38 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
39 mtdcr(UIC1SR, 0xffffffff); /* clear all */
41 mtdcr(UIC2SR, 0xffffffff); /* clear all */
42 mtdcr(UIC2ER, 0x00000000); /* disable all */
43 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
44 mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
45 mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
46 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
47 mtdcr(UIC2SR, 0xffffffff); /* clear all */
49 mtdcr(UIC3SR, 0xffffffff); /* clear all */
50 mtdcr(UIC3ER, 0x00000000); /* disable all */
51 mtdcr(UIC3CR, 0x00000000); /* all non-critical */
52 mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
53 mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
54 mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
55 mtdcr(UIC3SR, 0xffffffff); /* clear all */
58 * Configure PFC (Pin Function Control) registers
61 mtsdr(SDR0_PFC1, 0x0000000);
69 int i = getenv_f("serial#", buf, sizeof(buf));
71 puts("Board: Bluestone Evaluation Board");
86 /* Setup PLB4-AHB bridge based on the system address map */
87 mtdcr(AHB_TOP, 0x8000004B);
88 mtdcr(AHB_BOT, 0x8000004B);
91 * The AHB Bridge core is held in reset after power-on or reset
94 mfsdr(SDR0_SRST1, sdr0_srst1);
95 sdr0_srst1 &= ~SDR0_SRST1_AHB;
96 mtsdr(SDR0_SRST1, sdr0_srst1);