3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/ppc440.h>
11 #include <fdt_support.h>
13 #include <asm/processor.h>
16 #include <asm/4xx_pcie.h>
17 #include <asm/ppc4xx-gpio.h>
18 #include <asm/errno.h>
20 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
22 DECLARE_GLOBAL_DATA_PTR;
36 #define BOARD_CANYONLANDS_PCIE 1
37 #define BOARD_CANYONLANDS_SATA 2
38 #define BOARD_GLACIER 3
39 #define BOARD_ARCHES 4
42 * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
43 * board specific values.
45 #if defined(CONFIG_ARCHES)
46 u32 ddr_wrdtr(u32 default_val) {
47 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823);
50 u32 ddr_wrdtr(u32 default_val) {
51 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
54 u32 ddr_clktr(u32 default_val) {
55 return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
59 #if defined(CONFIG_ARCHES)
61 * FPGA read/write helper macros
63 static inline int board_fpga_read(int offset)
67 data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
72 static inline void board_fpga_write(int offset, int data)
74 out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
78 * CPLD read/write helper macros
80 static inline int board_cpld_read(int offset)
84 out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
85 data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
90 static inline void board_cpld_write(int offset, int data)
92 out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
93 out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
96 static int pvr_460ex(void)
100 if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA) ||
101 (pvr == PVR_460EX_RB))
106 #endif /* defined(CONFIG_ARCHES) */
108 int board_early_init_f(void)
110 #if !defined(CONFIG_ARCHES)
112 struct board_bcsr *bcsr_data =
113 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
118 * Setup the interrupt controller polarities, triggers, etc.
120 mtdcr(UIC0SR, 0xffffffff); /* clear all */
121 mtdcr(UIC0ER, 0x00000000); /* disable all */
122 mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
123 mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
124 mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
125 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
126 mtdcr(UIC0SR, 0xffffffff); /* clear all */
128 mtdcr(UIC1SR, 0xffffffff); /* clear all */
129 mtdcr(UIC1ER, 0x00000000); /* disable all */
130 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
131 mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
132 mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
133 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
134 mtdcr(UIC1SR, 0xffffffff); /* clear all */
136 mtdcr(UIC2SR, 0xffffffff); /* clear all */
137 mtdcr(UIC2ER, 0x00000000); /* disable all */
138 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
139 mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
140 mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
141 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
142 mtdcr(UIC2SR, 0xffffffff); /* clear all */
144 mtdcr(UIC3SR, 0xffffffff); /* clear all */
145 mtdcr(UIC3ER, 0x00000000); /* disable all */
146 mtdcr(UIC3CR, 0x00000000); /* all non-critical */
147 mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
148 mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
149 mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
150 mtdcr(UIC3SR, 0xffffffff); /* clear all */
152 #if !defined(CONFIG_ARCHES)
153 /* SDR Setting - enable NDFC */
154 mfsdr(SDR0_CUST0, sdr0_cust0);
155 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
156 SDR0_CUST0_NDFC_ENABLE |
157 SDR0_CUST0_NDFC_BW_8_BIT |
158 SDR0_CUST0_NDFC_ARE_MASK |
159 SDR0_CUST0_NDFC_BAC_ENCODE(3) |
160 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
161 mtsdr(SDR0_CUST0, sdr0_cust0);
165 * Configure PFC (Pin Function Control) registers
168 mtsdr(SDR0_PFC1, 0x00040000);
170 /* Enable PCI host functionality in SDR0_PCI0 */
171 mtsdr(SDR0_PCI0, 0xe0000000);
173 #if !defined(CONFIG_ARCHES)
174 /* Enable ethernet and take out of reset */
175 out_8(&bcsr_data->eth_ctrl, 0) ;
177 /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
178 out_8(&bcsr_data->flash_ctrl, 0) ;
179 mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
181 /* Setup PLB4-AHB bridge based on the system address map */
182 mtdcr(AHB_TOP, 0x8000004B);
183 mtdcr(AHB_BOT, 0x8000004B);
190 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
191 int usb_board_init(void)
193 struct board_bcsr *bcsr_data =
194 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
197 /* Enable USB host & USB-OTG */
198 val = in_8(&bcsr_data->usb_ctrl);
199 val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
200 out_8(&bcsr_data->usb_ctrl, val);
203 * Configure USB-STP pins as alternate and not GPIO
204 * It seems to be neccessary to configure the STP pins as GPIO
205 * input at powerup (perhaps while USB reset is asserted). So
206 * we configure those pins to their "real" function now.
208 gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
209 gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
214 int usb_board_stop(void)
216 struct board_bcsr *bcsr_data =
217 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
220 /* Disable USB host & USB-OTG */
221 val = in_8(&bcsr_data->usb_ctrl);
222 val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
223 out_8(&bcsr_data->usb_ctrl, val);
225 /* Reconfigure USB-STP pins as input */
226 gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
227 gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
232 int usb_board_init_fail(void)
234 return usb_board_stop();
236 #endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
238 #if !defined(CONFIG_ARCHES)
239 static void canyonlands_sata_init(int board_type)
243 if (board_type == BOARD_CANYONLANDS_SATA) {
244 /* Put SATA in reset */
245 SDR_WRITE(SDR0_SRST1, 0x00020001);
247 /* Set the phy for SATA, not PCI-E port 0 */
248 reg = SDR_READ(PESDR0_PHY_CTL_RST);
249 SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
250 reg = SDR_READ(PESDR0_L0CLK);
251 SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
252 SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
253 SDR_WRITE(PESDR0_L0DRV, 0x00000104);
255 /* Bring SATA out of reset */
256 SDR_WRITE(SDR0_SRST1, 0x00000000);
259 #endif /* !defined(CONFIG_ARCHES) */
261 int get_cpu_num(void)
263 int cpu = NA_OR_UNKNOWN_CPU;
265 #if defined(CONFIG_ARCHES)
268 cpu_num = board_fpga_read(0x3);
270 /* sanity check; assume cpu numbering starts and increments from 0 */
271 if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
278 #if !defined(CONFIG_ARCHES)
281 struct board_bcsr *bcsr_data =
282 (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
284 int i = getenv_f("serial#", buf, sizeof(buf));
287 printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
288 if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
289 gd->board_type = BOARD_CANYONLANDS_PCIE;
291 gd->board_type = BOARD_CANYONLANDS_SATA;
293 printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
294 gd->board_type = BOARD_GLACIER;
297 switch (gd->board_type) {
298 case BOARD_CANYONLANDS_PCIE:
303 case BOARD_CANYONLANDS_SATA:
304 puts(", 1*PCIe/1*SATA");
308 printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
316 canyonlands_sata_init(gd->board_type);
321 #else /* defined(CONFIG_ARCHES) */
325 char *s = getenv("serial#");
327 printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
328 printf(" Revision %02x.%02x ",
329 board_fpga_read(0x0), board_fpga_read(0x1));
331 gd->board_type = BOARD_ARCHES;
333 /* Only CPU0 has access to CPLD registers */
334 if (get_cpu_num() == 0) {
335 u8 cfg_sw = board_cpld_read(0x1);
336 printf("(FPGA=%02x, CPLD=%02x)\n",
337 board_fpga_read(0x2), board_cpld_read(0x0));
338 printf(" Configuration Switch %d%d%d%d\n",
339 ((cfg_sw >> 3) & 0x01),
340 ((cfg_sw >> 2) & 0x01),
341 ((cfg_sw >> 1) & 0x01),
342 ((cfg_sw >> 0) & 0x01));
344 printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
348 printf(" Serial# %s\n", s);
352 #endif /* !defined(CONFIG_ARCHES) */
354 #if defined(CONFIG_PCI)
355 int board_pcie_first(void)
358 * Canyonlands with SATA enabled has only one PCIe slot
361 if (gd->board_type == BOARD_CANYONLANDS_SATA)
366 #endif /* CONFIG_PCI */
368 int board_early_init_r (void)
371 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
372 * boot EBC mapping only supports a maximum of 16MBytes
373 * (4.ff00.0000 - 4.ffff.ffff).
374 * To solve this problem, the FLASH has to get remapped to another
375 * EBC address which accepts bigger regions:
377 * 0xfc00.0000 -> 4.cc00.0000
380 /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
381 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
382 mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
384 mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
387 /* Remove TLB entry of boot EBC mapping */
388 remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
390 /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
391 program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
395 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
396 * 0xfc00.0000 is possible
400 * Clear potential errors resulting from auto-calibration.
401 * If not done, then we could get an interrupt later on when
402 * exceptions are enabled.
404 set_mcsr(get_mcsr());
409 #if !defined(CONFIG_ARCHES)
410 int misc_init_r(void)
417 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
418 * This is board specific, so let's do it here.
420 mfsdr(SDR0_ETH_CFG, eth_cfg);
421 /* disable SGMII mode */
422 eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
423 SDR0_ETH_CFG_SGMII1_ENABLE |
424 SDR0_ETH_CFG_SGMII0_ENABLE);
425 /* Set the for 2 RGMII mode */
426 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
427 eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
429 eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
431 eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
432 mtsdr(SDR0_ETH_CFG, eth_cfg);
435 * The AHB Bridge core is held in reset after power-on or reset
438 mfsdr(SDR0_SRST1, sdr0_srst1);
439 sdr0_srst1 &= ~SDR0_SRST1_AHB;
440 mtsdr(SDR0_SRST1, sdr0_srst1);
444 * Disable square wave output: Batterie will be drained
445 * quickly, when this output is not disabled
447 val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
449 i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
454 #else /* defined(CONFIG_ARCHES) */
456 int misc_init_r(void)
463 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
464 * This is board specific, so let's do it here.
467 /* enable SGMII mode */
468 eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
469 SDR0_ETH_CFG_SGMII1_ENABLE |
470 SDR0_ETH_CFG_SGMII2_ENABLE);
472 /* Set EMAC for MDIO */
473 eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
475 /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
476 eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
478 mtsdr(SDR0_ETH_CFG, eth_cfg);
480 /* reset all SGMII interfaces */
481 mfsdr(SDR0_SRST1, reg);
482 reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
483 mtsdr(SDR0_SRST1, reg);
484 mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
485 mtsdr(SDR0_SRST1, 0x00000000);
488 mfsdr(SDR0_ETH_PLL, eth_pll);
489 } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
493 #endif /* !defined(CONFIG_ARCHES) */
495 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
496 extern void __ft_board_setup(void *blob, bd_t *bd);
498 void ft_board_setup(void *blob, bd_t *bd)
500 __ft_board_setup(blob, bd);
502 if (gd->board_type == BOARD_CANYONLANDS_SATA) {
504 * When SATA is selected we need to disable the first PCIe
505 * node in the device tree, so that Linux doesn't initialize
508 fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
509 "disabled", sizeof("disabled"), 1);
512 if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
514 * When PCIe is selected we need to disable the SATA
515 * node in the device tree, so that Linux doesn't initialize
518 fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
519 "disabled", sizeof("disabled"), 1);
522 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */