3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <fdt_support.h>
25 #include <asm/processor.h>
28 #include <asm/4xx_pcie.h>
31 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
33 DECLARE_GLOBAL_DATA_PTR;
35 #define CFG_BCSR3_PCIE 0x10
37 #define BOARD_CANYONLANDS_PCIE 1
38 #define BOARD_CANYONLANDS_SATA 2
39 #define BOARD_GLACIER 3
41 int board_early_init_f(void)
46 /*------------------------------------------------------------------+
47 * Setup the interrupt controller polarities, triggers, etc.
48 *------------------------------------------------------------------*/
49 mtdcr(uic0sr, 0xffffffff); /* clear all */
50 mtdcr(uic0er, 0x00000000); /* disable all */
51 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
52 mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
53 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
54 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
55 mtdcr(uic0sr, 0xffffffff); /* clear all */
57 mtdcr(uic1sr, 0xffffffff); /* clear all */
58 mtdcr(uic1er, 0x00000000); /* disable all */
59 mtdcr(uic1cr, 0x00000000); /* all non-critical */
60 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
61 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
62 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
63 mtdcr(uic1sr, 0xffffffff); /* clear all */
65 mtdcr(uic2sr, 0xffffffff); /* clear all */
66 mtdcr(uic2er, 0x00000000); /* disable all */
67 mtdcr(uic2cr, 0x00000000); /* all non-critical */
68 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
69 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
70 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
71 mtdcr(uic2sr, 0xffffffff); /* clear all */
73 mtdcr(uic3sr, 0xffffffff); /* clear all */
74 mtdcr(uic3er, 0x00000000); /* disable all */
75 mtdcr(uic3cr, 0x00000000); /* all non-critical */
76 mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
77 mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
78 mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
79 mtdcr(uic3sr, 0xffffffff); /* clear all */
81 /* SDR Setting - enable NDFC */
82 mfsdr(SDR0_CUST0, sdr0_cust0);
83 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
84 SDR0_CUST0_NDFC_ENABLE |
85 SDR0_CUST0_NDFC_BW_8_BIT |
86 SDR0_CUST0_NDFC_ARE_MASK |
87 SDR0_CUST0_NDFC_BAC_ENCODE(3) |
88 (0x80000000 >> (28 + CFG_NAND_CS));
89 mtsdr(SDR0_CUST0, sdr0_cust0);
92 * Configure PFC (Pin Function Control) registers
95 mtsdr(SDR0_PFC1, 0x00040000);
97 /* Enable PCI host functionality in SDR0_PCI0 */
98 mtsdr(SDR0_PCI0, 0xe0000000);
100 /* Enable ethernet and take out of reset */
101 out_8((void *)CFG_BCSR_BASE + 6, 0);
103 /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
104 out_8((void *)CFG_BCSR_BASE + 5, 0);
106 /* Enable USB host & USB-OTG */
107 out_8((void *)CFG_BCSR_BASE + 7, 0);
109 mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
111 /* Setup PLB4-AHB bridge based on the system address map */
112 mtdcr(AHB_TOP, 0x8000004B);
113 mtdcr(AHB_BOT, 0x8000004B);
115 if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
117 * Configure USB-STP pins as alternate and not GPIO
118 * It seems to be neccessary to configure the STP pins as GPIO
119 * input at powerup (perhaps while USB reset is asserted). So
120 * we configure those pins to their "real" function now.
122 gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
123 gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
129 int checkboard (void)
131 char *s = getenv("serial#");
134 if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) {
135 printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
136 gd->board_type = BOARD_GLACIER;
138 printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
139 if (in_8((void *)(CFG_BCSR_BASE + 3)) & CFG_BCSR3_PCIE)
140 gd->board_type = BOARD_CANYONLANDS_PCIE;
142 gd->board_type = BOARD_CANYONLANDS_SATA;
145 switch (gd->board_type) {
146 case BOARD_CANYONLANDS_PCIE:
151 case BOARD_CANYONLANDS_SATA:
152 puts(", 1*PCIe/1*SATA");
156 printf(", Rev. %X", in_8((void *)(CFG_BCSR_BASE + 0)));
168 * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
169 * board specific values.
171 u32 ddr_wrdtr(u32 default_val) {
172 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
175 u32 ddr_clktr(u32 default_val) {
176 return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
179 #if defined(CONFIG_NAND_U_BOOT)
181 * NAND booting U-Boot version uses a fixed initialization, since the whole
182 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
185 long int initdram(int board_type)
187 return CFG_MBYTES_SDRAM << 20;
191 #if defined(CFG_DRAM_TEST)
194 unsigned long *mem = (unsigned long *)0;
195 const unsigned long kend = (1024 / sizeof(unsigned long));
200 for (k = 0; k < CFG_KBYTES_SDRAM;
201 ++k, mem += (1024 / sizeof(unsigned long))) {
202 if ((k & 1023) == 0) {
203 printf("%3d MB\r", k / 1024);
206 memset(mem, 0xaaaaaaaa, 1024);
207 for (n = 0; n < kend; ++n) {
208 if (mem[n] != 0xaaaaaaaa) {
209 printf("SDRAM test fails at: %08x\n",
215 memset(mem, 0x55555555, 1024);
216 for (n = 0; n < kend; ++n) {
217 if (mem[n] != 0x55555555) {
218 printf("SDRAM test fails at: %08x\n",
224 printf("SDRAM test passes\n");
229 /*************************************************************************
232 * The bootstrap configuration provides default settings for the pci
233 * inbound map (PIM). But the bootstrap config choices are limited and
234 * may not be sufficient for a given board.
236 ************************************************************************/
237 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
238 void pci_target_init(struct pci_controller * hose )
240 /*-------------------------------------------------------------------+
242 *-------------------------------------------------------------------*/
243 out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
244 out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
245 out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
246 out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
248 /*-------------------------------------------------------------------+
249 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
250 * strapping options to not support sizes such as 128/256 MB.
251 *-------------------------------------------------------------------*/
252 out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
253 out_le32((void *)PCIX0_PIM0LAH, 0);
254 out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
255 out_le32((void *)PCIX0_BAR0, 0);
257 /*-------------------------------------------------------------------+
258 * Program the board's subsystem id/vendor id
259 *-------------------------------------------------------------------*/
260 out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
261 out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
263 out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
265 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
267 #if defined(CONFIG_PCI)
271 * This routine is called to determine if a pci scan should be
272 * performed. With various hardware environments (especially cPCI and
273 * PPMC) it's insufficient to depend on the state of the arbiter enable
274 * bit in the strap register, or generic host/adapter assumptions.
276 * Rather than hard-code a bad assumption in the general 440 code, the
277 * 440 pci code requires the board to decide at runtime.
279 * Return 0 for adapter mode, non-zero for host (monarch) mode.
281 int is_pci_host(struct pci_controller *hose)
283 /* Board is always configured as host. */
287 static struct pci_controller pcie_hose[2] = {{0},{0}};
289 void pcie_setup_hoses(int busno)
291 struct pci_controller *hose;
299 * assume we're called after the PCIX hose is initialized, which takes
300 * bus ID 0 and therefore start numbering PCIe's from 1.
305 * Canyonlands with SATA enabled has only one PCIe slot
308 if (gd->board_type == BOARD_CANYONLANDS_SATA)
313 for (i = start; i <= 1; i++) {
316 ret = ppc4xx_init_pcie_endport(i);
318 ret = ppc4xx_init_pcie_rootport(i);
320 printf("PCIE%d: initialization as %s failed\n", i,
321 is_end_point(i) ? "endpoint" : "root-complex");
325 hose = &pcie_hose[i];
326 hose->first_busno = bus;
327 hose->last_busno = bus;
328 hose->current_busno = bus;
330 /* setup mem resource */
331 pci_set_region(hose->regions + 0,
332 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
333 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
336 hose->region_count = 1;
337 pci_register_hose(hose);
339 if (is_end_point(i)) {
340 ppc4xx_setup_pcie_endpoint(hose, i);
342 * Reson for no scanning is endpoint can not generate
343 * upstream configuration accesses.
346 ppc4xx_setup_pcie_rootpoint(hose, i);
347 env = getenv ("pciscandelay");
349 delay = simple_strtoul(env, NULL, 10);
351 printf("Warning, expect noticable delay before "
352 "PCIe scan due to 'pciscandelay' value!\n");
353 mdelay(delay * 1000);
357 * Config access can only go down stream
359 hose->last_busno = pci_hose_scan(hose);
360 bus = hose->last_busno + 1;
364 #endif /* CONFIG_PCI */
366 int board_early_init_r (void)
369 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
370 * boot EBC mapping only supports a maximum of 16MBytes
371 * (4.ff00.0000 - 4.ffff.ffff).
372 * To solve this problem, the FLASH has to get remapped to another
373 * EBC address which accepts bigger regions:
375 * 0xfc00.0000 -> 4.cc00.0000
378 /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
379 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
380 mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
382 mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
385 /* Remove TLB entry of boot EBC mapping */
386 remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);
388 /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
389 program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
393 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
394 * 0xfc00.0000 is possible
398 * Clear potential errors resulting from auto-calibration.
399 * If not done, then we could get an interrupt later on when
400 * exceptions are enabled.
402 set_mcsr(get_mcsr());
407 int misc_init_r(void)
414 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
415 * This is board specific, so let's do it here.
417 mfsdr(SDR0_ETH_CFG, eth_cfg);
418 /* disable SGMII mode */
419 eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
420 SDR0_ETH_CFG_SGMII1_ENABLE |
421 SDR0_ETH_CFG_SGMII0_ENABLE);
422 /* Set the for 2 RGMII mode */
423 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
424 eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
425 if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
426 eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
428 eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
429 mtsdr(SDR0_ETH_CFG, eth_cfg);
432 * The AHB Bridge core is held in reset after power-on or reset
435 mfsdr(SDR0_SRST1, sdr0_srst1);
436 sdr0_srst1 &= ~SDR0_SRST1_AHB;
437 mtsdr(SDR0_SRST1, sdr0_srst1);
442 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
443 void ft_board_setup(void *blob, bd_t *bd)
448 ft_cpu_setup(blob, bd);
450 /* Fixup NOR mapping */
451 val[0] = 0; /* chip select number */
452 val[1] = 0; /* always 0 */
453 val[2] = CFG_FLASH_BASE_PHYS_L; /* we fixed up this address */
454 val[3] = gd->bd->bi_flashsize;
455 rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
456 val, sizeof(val), 1);
458 printf("Unable to update property NOR mapping, err=%s\n",
461 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */